There are general changes pending to make the /aliases/serial* entries
number the serial ports on the system. On Tegra, so far the ports have
been just numbered dynamically as they are configured so that makes them
change.
To avoid this, add specific aliases per board to keep the old numbers.
This allows us to change the numbering by default on future SoCs while
keeping the numbering on existing boards.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Thierry Reding <treding@nvidia.com>
These properties are deprecated and no longer of any use.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
These new properties more accurately reflect the real connections of the
boards and therefore make it easier to match them up with schematics.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This supply controls the +5V pin on the HDMI connector, which in turn is
used by attached sinks to return the hotplug detect signal.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add backlight and panel nodes for the Harmony TFT LCD panel.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
tegra124-venice2.dts isn't touched yet since we haven't added any off-
SoC RTC device to its device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use key code macros for all key code refernced for keys.
For tegra20-seaboard.dts and tegra20-harmony.dts:
The key comment for key (16th row and 1st column) is KEY_KPSLASH but
code is 0x004e which is the key code for KEY_KPPLUS. As there other
key exist with KY_KPPLUS, I am assuming key code is wrong and comment
is fine. With this assumption, I am keeping the key code as KEY_KPSLASH.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
For Tegra DT files, I've been attempting to keep the nodes sorted in
the order:
1) Nodes with reg, in order of reg.
2) Nodes without reg, alphabetically.
This patch fixes a few escapees that I missed:-(
The diffs look larger than they really are, because sometimes when one
node was moved up or down, diff chose to represent this as many other
nodes being moved the other way!
Signed-off-by: Stephen Warren <swarren@nvidia.com>
DT node names should include a unit address iff the node has a reg
property. For Tegra DTs at least, we were previously applying a different
rule, namely that node names only needed to include a unit address if it
was required to make the node name unique. Consequently, many unit
addresses are missing. Add them.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
With the device tree support in place, probe the PCIe controller from
the device tree and remove the corresponding workaround in the board
file.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enabling the LP1 suspend mode for Tegra devices.
Tested-by: Marc Dietrich <marvin24@gmx.de> # paz00 board
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use the Tegra20 CAR binding header (tegra20-car.h) to replace magic
numbers in the device tree. For example,
- clocks = <&tegra_car 28>;
+ clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
[swarren, updated since tegra20-car.h moved for consistency]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
and some interrupts properties. Use standard GPIO flag defines too.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.
This allows future use of #defines and header files in order to define
names for various constants, such as the IDs and flags in GPIO
specifiers. Use of those features will increase the readability of the
device tree files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch updates all Tegra board files so that they contain all the
properties required by the updated USB DT binding. Note that this patch
only adds the new properties and does not yet remove the old properties,
in order to maintain bisectability. The old properties will be removed
once the driver has been updated to assume the new bindings.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
[swarren: fixed some newly added regulator-name properties to better
match schematic, avoided duplicate regulator-name on Whistler.]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active
low nature of the GPIO.
2. Placed USB PHY DT node immediately below the EHCI controller DT nodes
and corrected reg value in the name of USB PHY DT node.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Adding the PM configuration of PMC when the platform support suspend
function.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This adds the power gpio key to DT and enable the wakeup of the gpio key
for the device. The Seaboard and paz00 already had the power gpio key
binding and the power key of Whistler was on KBC. So these boards' device
tree didn't include in this patch.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The GPIO pin of SD slot card detection should active low.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Numerous updates to the various Tegra device trees are made:
* Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris
carrier boards.
* Enablement of the HDMI connector on most boards.
* Enablement of the keyboard controller on a few boards.
* Addition of the AC'97 controller to Tegra20.
* Addition of a GPIO poweroff node for TrimSlice.
* Changes to support the new "high speed UART" (DMA-capable) driver for
Tegra serial ports, and enablement for Cardhu's UART C.
* A few cleanups, such as compatible flag fixes, node renames, node
ordering fixes, commonizing properties into SoC .dtsi files, etc..
This pull request is based on (most of) the previous pull request with
tag tegra-for-3.9-soc-t114.
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Merge tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
From Stephen Warren:
ARM: tegra: device tree updates
Numerous updates to the various Tegra device trees are made:
* Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris
carrier boards.
* Enablement of the HDMI connector on most boards.
* Enablement of the keyboard controller on a few boards.
* Addition of the AC'97 controller to Tegra20.
* Addition of a GPIO poweroff node for TrimSlice.
* Changes to support the new "high speed UART" (DMA-capable) driver for
Tegra serial ports, and enablement for Cardhu's UART C.
* A few cleanups, such as compatible flag fixes, node renames, node
ordering fixes, commonizing properties into SoC .dtsi files, etc..
This pull request is based on (most of) the previous pull request with
tag tegra-for-3.9-soc-t114.
* tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (22 commits)
ARM: dt: tegra30: Rename "smmu" to "iommu"
ARM: dt: tegra20: Rename "gart" to "iommu"
ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
ARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COM
ARM: tegra: Add Colibri T20 512MB COM device tree
ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
ARM: tegra: harmony: enable keyboard in DT
ARM: tegra: whistler: enable keyboard in DT
ARM: tegra: cardhu: register UARTC
ARM: tegra: seaboard: enable keyboard in DT
ARM: tegra: add DT entry for KBC controller
ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT
ASoC: tegra: add ac97 host controller to device tree
ARM: DT: tegra: Add Tegra30 Beaver board support
ARM: DT: tegra: Add board level compatible properties
ARM: tegra: paz00: enable HDMI port
ARM: tegra: ventana: enable HDMI port
ARM: tegra: seaboard: enable HDMI port
ARM: tegra: trimslice: add gpio-poweroff node to DT
ARM: DT: tegra: Unify the description of Tegra20 boards
...
As reset GPIO information is PHY specific detail, adding
it to PHY DT node.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable Tegra based keyboard interfacing for keys and provide
all key mapping through DTS file.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable host1x, and the HDMI output. Harmony also has an optional LCD,
and a VGA output. The former isn't enabled due to potential issues with
having multiple outputs enabled. The latter isn't enabled since the
driver doesn't support VGA yet anyway.
Correct DDC I2C frequency to 100KHz.
Based on work by Thierry Reding for TrimSlice.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Harmony board has an Analog Devices ADT7461 temperature sensor
connected to the DVC bus. It can be used to monitor the ambient (local)
and on-die (remote) temperatures.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Commit 13511de "regulator: deprecate regulator-compatible DT property"
now allows for simpler content within the regulators node within a PMIC.
Modify all the Tegra device tree files to take advantage of this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
On Harmony, LDO7 does not feed vdd_fuse. Correct the regulator name.
This issue was probably the result of copying Ventana's regulator setup
when creating the Harmony .dts file. No other naming issues appear to
exist.
Reported-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add DT property to tell the TPS6586x that it should provide the
pm_power_off() implementation. This allows "shutdown" to work.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Harmony uses a TPS6586x regulator. Instantiate this, and hook up a
couple of fixed GPIO-controlled regulators too.
Based on Ventana regulator patch by Stephen Warren <swarren@nvidia.com>
and converted to Harmony.
swarren made the following changes:
* Added ldo0 regulator configuration to device tree, and updated
board-harmony-pcie.c for the new regulator name.
* Fixed vdd_1v05's voltage from 10.5V to 1.05V.
* Modified board-harmony-pcie.c to obtain the en_vdd_1v05 GPIO number at
run-time from device tree instead of hard-coding it.
* Removed board-harmony{-power.c,.h} now that they're unused.
* Disabled vdd_1v05 regulator; the code in board-harmony-pcie.c hijacks
this GPIO for now. This will be fixed when the PCIe driver is re-
written as a driver. The code can't regulator_get("vdd_1v05") right
now, because the vdd_1v05 regulator's probe gets deferred due to its
supply being the PMIC, which gets probed after the regulator the first
time around, and this dependency is only resolved by repeated probing,
which happens when deferred_probe_initcall() is called, which happens
in a late initcall, whose runtime order relative to harmony_pcie_init()
is undefined, since that's also called from a late initcall.
* Removed unused harmony_pcie_initcall().
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Most ARM ${board}.dts files are already named ${soc}-${board}.dts. This
change modifies the Tegra board files to be named the same way for
consistency.
Once a related change is made in U-Boot, this will cause both U-Boot and
the kernel to use the same names for the .dts files and SoC identifiers,
thus allowing U-Boot's recently added "soc" and "board" environment
variables to be used to construct the name of Tegra .dtb files, and hence
allow board-generic U-Boot bootcmd scripts to be written.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Olof Johansson