Commit Graph

17642 Commits

Author SHA1 Message Date
Marc Zyngier 9f03db6673 Merge branch kvm-arm64/mmu/mte into kvmarm-master/next
KVM/arm64 support for MTE, courtesy of Steven Price.
It allows the guest to use memory tagging, and offers
a new userspace API to save/restore the tags.

* kvm-arm64/mmu/mte:
  KVM: arm64: Document MTE capability and ioctl
  KVM: arm64: Add ioctl to fetch/store tags in a guest
  KVM: arm64: Expose KVM_ARM_CAP_MTE
  KVM: arm64: Save/restore MTE registers
  KVM: arm64: Introduce MTE VM feature
  arm64: mte: Sync tags for pages where PTE is untagged

Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-06-22 15:09:34 +01:00
Steven Price f0376edb1d KVM: arm64: Add ioctl to fetch/store tags in a guest
The VMM may not wish to have it's own mapping of guest memory mapped
with PROT_MTE because this causes problems if the VMM has tag checking
enabled (the guest controls the tags in physical RAM and it's unlikely
the tags are correct for the VMM).

Instead add a new ioctl which allows the VMM to easily read/write the
tags from guest memory, allowing the VMM's mapping to be non-PROT_MTE
while the VMM can still read/write the tags for the purpose of
migration.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-6-steven.price@arm.com
2021-06-22 14:08:06 +01:00
Steven Price 673638f434 KVM: arm64: Expose KVM_ARM_CAP_MTE
It's now safe for the VMM to enable MTE in a guest, so expose the
capability to user space.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-5-steven.price@arm.com
2021-06-22 14:08:06 +01:00
Steven Price e1f358b504 KVM: arm64: Save/restore MTE registers
Define the new system registers that MTE introduces and context switch
them. The MTE feature is still hidden from the ID register as it isn't
supported in a VM yet.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-4-steven.price@arm.com
2021-06-22 14:08:05 +01:00
Steven Price ea7fc1bb1c KVM: arm64: Introduce MTE VM feature
Add a new VM feature 'KVM_ARM_CAP_MTE' which enables memory tagging
for a VM. This will expose the feature to the guest and automatically
tag memory pages touched by the VM as PG_mte_tagged (and clear the tag
storage) to ensure that the guest cannot see stale tags, and so that
the tags are correctly saved/restored across swap.

Actually exposing the new capability to user space happens in a later
patch.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
[maz: move VM_SHARED sampling into the critical section]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-3-steven.price@arm.com
2021-06-22 14:08:05 +01:00
Raphael Gault cf292e93f4 arm64: Restrict undef hook for cpufeature registers
This commit modifies the mask of the mrs_hook declared in
arch/arm64/kernel/cpufeatures.c which emulates only feature register
access. This is necessary because this hook's mask was too large and
thus masking any mrs instruction, even if not related to the emulated
registers which made the pmu emulation inefficient.

Signed-off-by: Raphael Gault <raphael.gault@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210517180256.2881891-1-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-22 11:57:03 +01:00
Liang Chen 01610a24ce arm64: dts: rockchip: add basic dts for RK3568 EVB
This patch add rk3568-evb1-v10.dts for RK3568 evaluation board.
add uart/emmc/i2c/rk809 node for basic function.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Link: https://lore.kernel.org/r/20210622020517.13100-5-cl@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-22 12:21:55 +02:00
Liang Chen a3adc0b907 arm64: dts: rockchip: add core dtsi for RK3568 SoC
RK3568 is a high-performance and low power quad-core application processor
designed for personal mobile internet device and AIoT equipment. This patch
add basic core dtsi file for it.

We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that
kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will
enalbe a special high-performance PLL when high frequency is required. The
smci_clk code is in ATF, and clkid for cpu is 0, as below:

    cpu0: cpu@0 {
        device_type = "cpu";
        compatible = "arm,cortex-a55";
        reg = <0x0 0x0>;
        clocks = <&scmi_clk 0>;
    };

Signed-off-by: Liang Chen <cl@rock-chips.com>
Link: https://lore.kernel.org/r/20210622020517.13100-4-cl@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-22 12:21:55 +02:00
Liang Chen ef0bff8ba8 arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs
The pinconfig settings for Rockchip SoCs are pretty similar on all socs,
so move them to a shared dtsi to be included, instead of redefining them
for each soc.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Link: https://lore.kernel.org/r/20210622020517.13100-3-cl@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-22 12:06:08 +02:00
Steven Price 69e3b846d8 arm64: mte: Sync tags for pages where PTE is untagged
A KVM guest could store tags in a page even if the VMM hasn't mapped
the page with PROT_MTE. So when restoring pages from swap we will
need to check to see if there are any saved tags even if !pte_tagged().

However don't check pages for which pte_access_permitted() returns false
as these will not have been swapped out.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-2-steven.price@arm.com
2021-06-22 09:38:50 +01:00
Anshuman Khandual 2062d44da3 arm64/mm: Rename ARM64_SWAPPER_USES_SECTION_MAPS
ARM64_SWAPPER_USES_SECTION_MAPS implies that a PMD level huge page mappings
are used for swapper, idmap and vmemmap. Lets make it PMD explicit removing
any possible confusion with generic memory sections and also bit generic as
it's applicable for idmap and vmemmap mappings as well. Hence rename it as
ARM64_KERNEL_USES_PMD_MAPS instead.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/1623991622-24294-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-21 18:22:23 +01:00
Robert Marko abe66bb7a2 arm64: dts: ipq8074: Add QUP6 I2C node
Add node to support the QUP6 I2C controller inside
of IPQ8074.
It is exactly the same as QUP2 and QUP3 controllers.

Some routers like Xiaomi AX9000 and Netgear RBK850
use this bus.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20210619162751.2336974-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-21 11:21:11 -05:00
Mark Rutland 69bb0585eb arm64: insn: avoid circular include dependency
Nathan reports that when building with CONFIG_LTO_CLANG_THIN=y, the
build fails due to BUILD_BUG_ON() not being defined before its uss in
<asm/insn.h>.

The problem is that with LTO, we patch READ_ONCE(), and <asm/rwonce.h>
includes <asm/insn.h>, creating a circular include chain:

        <linux/build_bug.h>
        <linux/compiler.h>
        <asm/rwonce.h>
        <asm/alternative-macros.h>
        <asm/insn.h>
        <linux/build-bug.h>

... and so when <asm/insn.h> includes <linux/build_bug.h>, none of the
BUILD_BUG* definitions have happened yet.

To avoid this, let's move AARCH64_INSN_SIZE into a header without any
dependencies, such that it can always be safely included. At the same
time, avoid including <asm/alternative.h> in <asm/insn.h>, which should
no longer be necessary (and doesn't make sense when insn.h is consumed
by userspace).

Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210621080830.GA37068@C02TD0UTHF1T.local
Fixes: 3e00e39d9d ("arm64: insn: move AARCH64_INSN_SIZE into <asm/insn.h>")
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-21 11:58:03 +01:00
Alex Bee eb607cd495 arm64: dts: rockchip: Re-add regulator-always-on for vcc_sdio for rk3399-roc-pc
Re-add the regulator-always-on property for vcc_sdio which supplies sdmmc,
since it gets disabled during reboot now and the bootrom expects it to be
enabled  when booting from SD card. This makes rebooting impossible in that
case and requires a hard reset to boot again.

Fixes: 04a0077fdb ("arm64: dts: rockchip: Remove always-on properties from regulator nodes on rk3399-roc-pc.")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210619121306.7740-1-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-19 23:55:10 +02:00
Alex Bee 06b2818678 arm64: dts: rockchip: Re-add regulator-boot-on, regulator-always-on for vdd_gpu on rk3399-roc-pc
This might be a limitation of either the current panfrost driver
devfreq implementation or how the gpu is implemented in RK3399 SoC.
The gpu regulator must never get disabled or the registers get
(randomly?) inaccessable by the driver. (see all other RK3399 boards)

Fixes: ec7d731d81 ("arm64: dts: rockchip: Add node for gpu on rk3399-roc-pc")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210619121446.7802-1-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-19 23:54:12 +02:00
Alex Bee e1d635bc94 arm64: dts: rockchip: add ir-receiver for rk3399-roc-pc
Like some other RK3399 boards RK3399-ROC-PC has an ir receiver
connected to pwm3 which can be used as gpio-ir-receiver.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210619121642.7892-1-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-19 23:49:14 +02:00
Peter Robinson a406bfda89 arm64: dts: rockchip: Add USB-C port details for rk3399 Firefly
Add the initial details for the USB-C port.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Link: https://lore.kernel.org/r/20210613215237.830160-4-pbrobinson@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-19 10:44:51 +02:00
Peter Robinson 5768c5ff07 arm64: dts: rockchip: Sort rk3399 firefly pinmux entries
Sort the rk3399 firefly pinmux entries in alphabetical
order and de-dupe the pmic entries.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Link: https://lore.kernel.org/r/20210613215237.830160-3-pbrobinson@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-19 10:43:57 +02:00
Peter Robinson 4fab8e3655 arm64: dts: rockchip: add infrared receiver node to RK3399 Firefly
This adds the RK3399 Firefly’s infrared receiver to its dts.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Link: https://lore.kernel.org/r/20210613215237.830160-2-pbrobinson@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-19 10:43:57 +02:00
Peter Robinson ba2401ab87 arm64: dts: rockchip: add SPDIF node for rk3399-firefly
This patch adds the SPDIF sound node and related settings
for rk3399-firefly.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Link: https://lore.kernel.org/r/20210613215237.830160-1-pbrobinson@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-19 10:43:57 +02:00
Chris Morgan edb39de5d7 arm64: dts: rockchip: Add Rotation Property for OGA Panel
Add rotation property for Odroid Go Advance panel to note that it is
rotated 270 degrees. Rotation affects DRM connector after this patch:

https://cgit.freedesktop.org/drm/drm/commit/drivers/gpu/drm/panel/panel-elida-kd35t133.c?id=610d9c311b1387f8c4ac602fee1f2a1cb0508707

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20210614161849.332-1-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-19 10:37:47 +02:00
Jakub Kicinski adc2e56ebe Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Trivial conflicts in net/can/isotp.c and
tools/testing/selftests/net/mptcp/mptcp_connect.sh

scaled_ppm_to_ppb() was moved from drivers/ptp/ptp_clock.c
to include/linux/ptp_clock_kernel.h in -next so re-apply
the fix there.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-06-18 19:47:02 -07:00
Shaik Sajida Bhanu 77b7cfd0dc arm64: dts: qcom: sc7180: bus votes for eMMC and SD card
Update peak bandwidth and average bandwidth vote values for eMMC and
SDCard. This patch calculates the new votes as per the comments from
https://lore.kernel.org/patchwork/patch/1399453/#1619566.

Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Link: https://lore.kernel.org/r/1623835344-29607-1-git-send-email-sbhanu@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 13:19:03 -05:00
Konrad Dybcio e76c7e1f15 arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen
Add Samsung touchscreen node and relevant pin configuration to make the phones
actually interactable with.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616122708.144770-6-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:43:33 -05:00
Konrad Dybcio 4a62a82428 arm64: dts: qcom: sm8250-edo: Enable GPI DMA
Enable GPI DMA for Edo devices.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616122708.144770-5-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:43:32 -05:00
Konrad Dybcio f0cedfc398 arm64: dts: qcom: sm8250-edo: Enable ADSP/CDSP/SLPI
Enabling the hardware thankfully comes down to a simple status = "okay".
We assume that the firmware is provided by the Linux distribution, as it's
signed and needs to come from the stock Android.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616122708.144770-4-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:42:32 -05:00
Konrad Dybcio db92d8cdde arm64: dts: qcom: sm8250-edo: Enable PCIe
Enable PCIe0 (Wi-Fi) and 2 (SDX55m) interfaces and PHYs and assign relevant
pins and regulators.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616122708.144770-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:42:25 -05:00
Konrad Dybcio 13e948a36d arm64: dts: qcom: sm8250: Commonize PCIe pins
Commonize PCIe pins, as the configuration is SoC-common
and doesn't change (or at least doesn't change much) between
boards.

While at it, remove "output-low" from the RB5 board, as it's
not necessary - we already explicitly pull the perst pin low.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616122708.144770-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:41:55 -05:00
Konrad Dybcio 46e14907c7 arm64: dts: qcom: sm8250-edo: Add hardware keys
Volume Down, GAssist (pdx206 only) and camera keys live on PMIC pins,
with the latter kind being broken for now.. Add these and PON-connected
Volume Up & PWR.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616122708.144770-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:39:22 -05:00
Bhupesh Sharma 5b85e8f222 arm64: dts: qcom: sa8155p-adp: Add base dts file
Add base DTS file for SA8155p Automotive Development Platform.
It enables boot to console, adds tlmm reserved range and ufs flash.
It also includes pmic file.

SA8155p-adp board is based on sa8155p Qualcomm Snapdragon SoC.
SA8155p platform is similar to the SM8150, so use this as base
for now.

Cc: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210617054548.353293-6-bhupesh.sharma@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:37:26 -05:00
Bhupesh Sharma b557471bb2 arm64: dts: qcom: pmm8155au_2: Add base dts file
Add base DTS file for pmm8155au_2 along with GPIOs, power-on, rtc and vadc
nodes.

Cc: Mark Brown <broonie@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210617054548.353293-5-bhupesh.sharma@linaro.org
[bjorn: Added gpio-ranges to pmm8155au_2_gpios]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:29:53 -05:00
Bhupesh Sharma 10489ef12f arm64: dts: qcom: pmm8155au_1: Add base dts file
Add base DTS file for pmm8155au_1 along with GPIOs, power-on, rtc and vadc
nodes.

Cc: Mark Brown <broonie@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210617054548.353293-4-bhupesh.sharma@linaro.org
[bjorn: Added gpio-ranges to pmm8155au_1_gpios]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18 12:28:46 -05:00
Marc Zyngier 85c653fcc6 Merge branch arm64/for-next/caches into kvmarm-master/next
arm64 cache management function cleanup from Fuad Tabba,
shared with the arm64 tree.

* arm64/for-next/caches:
  arm64: Rename arm64-internal cache maintenance functions
  arm64: Fix cache maintenance function comments
  arm64: sync_icache_aliases to take end parameter instead of size
  arm64: __clean_dcache_area_pou to take end parameter instead of size
  arm64: __clean_dcache_area_pop to take end parameter instead of size
  arm64: __clean_dcache_area_poc to take end parameter instead of size
  arm64: __flush_dcache_area to take end parameter instead of size
  arm64: dcache_by_line_op to take end parameter instead of size
  arm64: __inval_dcache_area to take end parameter instead of size
  arm64: Fix comments to refer to correct function __flush_icache_range
  arm64: Move documentation of dcache_by_line_op
  arm64: assembler: remove user_alt
  arm64: Downgrade flush_icache_range to invalidate
  arm64: Do not enable uaccess for invalidate_icache_range
  arm64: Do not enable uaccess for flush_icache_range
  arm64: Apply errata to swsusp_arch_suspend_exit
  arm64: assembler: add conditional cache fixups
  arm64: assembler: replace `kaddr` with `addr`

Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-06-18 17:30:39 +01:00
Suman Anna d71abfcc6c arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs
Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within the MAIN domain on the TI AM642 EVM
and SK boards. These nodes are assigned to the respective rproc device
nodes as well. The first region will be used as the DMA pool for the rproc
devices, and the second region will furnish the static carveout regions
for the firmware memory.

An additional reserved memory node is also added to reserve a portion of
the DDR memory to be used for performing inter-processor communication
between all the remote processors running RTOS or baremetal firmwares.
8 MB of memory is reserved for this purpose, and this accounts for all
the vrings and vring buffers between all the possible pairs of remote
processors.

The current carveout addresses and sizes are defined statically for each
rproc device. The R5F processors do not have an MMU, and as such require
the exact memory used by the firmwares to be set-aside. The firmware
images do not require any RSC_CARVEOUT entries in their resource tables
to allocate the memory for firmware memory segments.

NOTE:
1. The R5F1 carveouts are needed only if the R5F cluster is running in
   Split (non Single-CPU) mode. The reserved memory nodes can be disabled
   later on if there is no use-case defined to use the corresponding
   remote processor.
2. The AM64x SoCs do not have any DSPs and one less R5F cluster compared
   to J721E SoCs. So, while the carveout memories reserved for the R5F
   clusters present on the SoC match to those on J721E, the overall
   memory map reserved for firmwares is quite different. The number of
   R5F clusters on AM64x SoCs are same as on J7200 SoCs, but the AM64x
   SoCs also have an additional M4F core, so the RTOS IPC memory region
   is 1 MB higher than on J7200 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210615195718.15898-4-s-anna@ti.com
2021-06-18 09:47:40 -05:00
Suman Anna 0afadba435 arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
Add the required 'mboxes' property to all the R5F processors for the
TI AM642 EVM and SK boards. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Note that any R5F Core1 resources are needed and used only when that
R5F cluster is configured for Split-mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210615195718.15898-3-s-anna@ti.com
2021-06-18 09:47:40 -05:00
Suman Anna a4f221cd68 arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
The AM64x SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. Both the R5F clusters are present within the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a new "Single-CPU" mode
or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
The mode is restricted to "Single-CPU" on some devices with the
appropriate eFuse bit set, but the most common devices support both
modes. These subsystems have 64 KB each Tightly-Coupled Memory (TCM)
internal memories for each core split between two banks - ATCM and
BTCM (further interleaved into two banks). The TCMs of both Cores
are combined in Single-CPU mode to provide a larger 128 KB of memory.
The other notable difference is that the TCMs are spaced 1 MB apart
on these SoCs unlike the existing SoCs.

Add the DT nodes for both these MAIN domain R5F cluster/subsystems,
the two R5F cores are added as child nodes to each of the corresponding
R5F cluster node. Both the clusters are configured to run in Split mode
by default, with the ATCMs enabled to allow the R5 cores to execute
code from DDR with boot-strapping code from ATCM. The inter-processor
communication between the main A72 cores and these processors is
achieved through shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
  MAIN R5FSS0 Core0: am64-main-r5f0_0-fw (both in Single-CPU & Split modes)
  MAIN R5FSS0 Core1: am64-main-r5f0_1-fw (needed only in Split mode)
  MAIN R5FSS1 Core0: am64-main-r5f1_0-fw (both in Single-CPU & Split modes)
  MAIN R5FSS1 Core1: am64-main-r5f1_1-fw (needed only in Split mode)

NOTE:
A R5FSS cluster can be configured in "Single-CPU" mode by using a
value of 2 for the "ti,cluster-mode" property. Value of 1 is not
permitted (fails the dtbs_check).

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210615195718.15898-2-s-anna@ti.com
2021-06-18 09:47:40 -05:00
Marc Zyngier cb5faa8c7d Merge branch kvm-arm64/pmu-fixes into kvmarm-master/next
Fixes for the PMUv3 emulation of PMCR_EL0:
- Don't spuriously reset the cycle counter when resetting other counters
- Force PMCR_EL0 to become effective after having restored it

* kvm-arm64/pmu-fixes:
  KVM: arm64: Restore PMU configuration on first run
  KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
2021-06-18 14:25:59 +01:00
Marc Zyngier d0c94c4979 KVM: arm64: Restore PMU configuration on first run
Restoring a guest with an active virtual PMU results in no perf
counters being instanciated on the host side. Not quite what
you'd expect from a restore.

In order to fix this, force a writeback of PMCR_EL0 on the first
run of a vcpu (using a new request so that it happens once the
vcpu has been loaded). This will in turn create all the host-side
counters that were missing.

Reported-by: Jinank Jain <jinankj@amazon.de>
Tested-by: Jinank Jain <jinankj@amazon.de>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/87wnrbylxv.wl-maz@kernel.org
Link: https://lore.kernel.org/r/b53dfcf9bbc4db7f96154b1cd5188d72b9766358.camel@amazon.de
2021-06-18 14:18:37 +01:00
Alexandru Elisei 2a71fabf6a KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:

"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."

Similar behaviour is described for AArch32 on page G8-7022. Make it so.

Fixes: c01d6a1802 ("KVM: arm64: pmu: Only handle supported event counters")
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210618105139.83795-1-alexandru.elisei@arm.com
2021-06-18 13:23:50 +01:00
Marc Zyngier b88835a89d Merge branch kvm-arm64/mmu/stage2-cmos into kvmarm-master/next
Cache maintenance updates from Yanan Wang, moving the CMOs
down into the page-table code. This ensures that we only issue
them when actually performing a mapping rather than upfront.

* kvm-arm64/mmu/stage2-cmos:
  KVM: arm64: Move guest CMOs to the fault handlers
  KVM: arm64: Tweak parameters of guest cache maintenance functions
  KVM: arm64: Introduce mm_ops member for structure stage2_attr_data
  KVM: arm64: Introduce two cache maintenance callbacks
2021-06-18 12:36:30 +01:00
Yanan Wang 25aa28691b KVM: arm64: Move guest CMOs to the fault handlers
We currently uniformly perform CMOs of D-cache and I-cache in function
user_mem_abort before calling the fault handlers. If we get concurrent
guest faults(e.g. translation faults, permission faults) or some really
unnecessary guest faults caused by BBM, CMOs for the first vcpu are
necessary while the others later are not.

By moving CMOs to the fault handlers, we can easily identify conditions
where they are really needed and avoid the unnecessary ones. As it's a
time consuming process to perform CMOs especially when flushing a block
range, so this solution reduces much load of kvm and improve efficiency
of the stage-2 page table code.

We can imagine two specific scenarios which will gain much benefit:
1) In a normal VM startup, this solution will improve the efficiency of
handling guest page faults incurred by vCPUs, when initially populating
stage-2 page tables.
2) After live migration, the heavy workload will be resumed on the
destination VM, however all the stage-2 page tables need to be rebuilt
at the moment. So this solution will ease the performance drop during
resuming stage.

Reviewed-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210617105824.31752-5-wangyanan55@huawei.com
2021-06-18 12:35:35 +01:00
Yanan Wang 378e6a9c78 KVM: arm64: Tweak parameters of guest cache maintenance functions
Adjust the parameter "kvm_pfn_t pfn" of __clean_dcache_guest_page
and __invalidate_icache_guest_page to "void *va", which paves the
way for converting these two guest CMO functions into callbacks in
structure kvm_pgtable_mm_ops. No functional change.

Reviewed-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210617105824.31752-4-wangyanan55@huawei.com
2021-06-18 12:35:35 +01:00
Yanan Wang a4d5ca5c7c KVM: arm64: Introduce mm_ops member for structure stage2_attr_data
Also add a mm_ops member for structure stage2_attr_data, since we
will move I-cache maintenance for guest stage-2 to the permission
path and as a result will need mm_ops for some callbacks.

Reviewed-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210617105824.31752-3-wangyanan55@huawei.com
2021-06-18 12:35:35 +01:00
Yanan Wang 6204004de3 KVM: arm64: Introduce two cache maintenance callbacks
To prepare for performing CMOs for guest stage-2 in the fault handlers
in pgtable.c, here introduce two cache maintenance callbacks in struct
kvm_pgtable_mm_ops. We also adjust the comment alignment for the
existing part but make no real content change at all.

Reviewed-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
[maz: fixed up comments and renamed callbacks]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210617105824.31752-2-wangyanan55@huawei.com
2021-06-18 12:34:52 +01:00
Peter Zijlstra b03fbd4ff2 sched: Introduce task_is_running()
Replace a bunch of 'p->state == TASK_RUNNING' with a new helper:
task_is_running(p).

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Davidlohr Bueso <dave@stgolabs.net>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210611082838.222401495@infradead.org
2021-06-18 11:43:07 +02:00
Ingo Molnar b2c0931a07 Merge branch 'sched/urgent' into sched/core, to resolve conflicts
This commit in sched/urgent moved the cfs_rq_is_decayed() function:

  a7b359fc6a37: ("sched/fair: Correctly insert cfs_rq's to list on unthrottle")

and this fresh commit in sched/core modified it in the old location:

  9e077b52d86a: ("sched/pelt: Check that *_avg are null when *_sum are")

Merge the two variants.

Conflicts:
	kernel/sched/fair.c

Signed-off-by: Ingo Molnar <mingo@kernel.org>
2021-06-18 11:31:25 +02:00
Lee Jones cf814bcfa1 arm64: smp: Bump debugging information print down to KERN_DEBUG
This sort of information is only generally useful when debugging.

No need to have these sprinkled through the kernel log otherwise.

Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210617073059.315542-1-lee.jones@linaro.org
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-17 22:43:12 +01:00
Paolo Bonzini e3cb6fa0e2 KVM: switch per-VM stats to u64
Make them the same type as vCPU stats.  There is no reason
to limit the counters to unsigned long.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-17 14:25:27 -04:00
Konrad Dybcio f515dcce2d arm64: dts: qcom: sm8250-edo: Fix up double "pinctrl-1"
When bringing the SDC pins back to edo.dtsi I managed to define
and overwrite pinctrl-1 instead of defining pinctrl-0 and 1. Fix it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616161536.206044-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-17 13:07:07 -05:00
Marc Zyngier 77345ef704 arm64: suspend: Use cpuidle context helpers in cpu_suspend()
Use cpuidle context helpers to switch to using DAIF.IF instead
of PMR to mask interrupts, ensuring that we suspend with
interrupts being able to reach the CPU interface.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Link: https://lore.kernel.org/r/20210615111227.2454465-5-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-17 18:00:39 +01:00
Marc Zyngier d4dc102772 arm64: Convert cpu_do_idle() to using cpuidle context helpers
Now that we have helpers that are aware of the pseudo-NMI
feature, introduce them to cpu_do_idle(). This allows for
some nice cleanup.

No functional change intended.

Tested-by: Valentin Schneider <valentin.schneider@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210615111227.2454465-3-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-17 18:00:39 +01:00
Marc Zyngier 8848f0665b arm64: Add cpuidle context save/restore helpers
As we need to start doing some additional work on all idle
paths, let's introduce a set of macros that will perform
the work related to the GICv3 pseudo-NMI idle entry exit.

Stubs are introduced to 32bit ARM for compatibility.
As these helpers are currently unused, there is no functional
change.

Tested-by: Valentin Schneider <valentin.schneider@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210615111227.2454465-2-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-17 18:00:39 +01:00
Konstantin Porotchkin e3850467bf arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
Eliminate 1MB gap between Linux and filesystem partitions.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-06-17 17:01:21 +02:00
Joerg Roedel 1c461ef9c4 Arm SMMU updates for 5.14
- SMMUv3:
 
   * Support stalling faults for platform devices
 
   * Decrease defaults sizes for the event and PRI queues
 
 - SMMUv2:
 
   * Support for a new '->probe_finalize' hook, needed by Nvidia
 
   * Even more Qualcomm compatible strings
 
   * Avoid Adreno TTBR1 quirk for DB820C platform
 
 - Misc:
 
   * Trivial cleanups/refactoring
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Merge tag 'arm-smmu-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu

Arm SMMU updates for 5.14

- SMMUv3:

  * Support stalling faults for platform devices

  * Decrease defaults sizes for the event and PRI queues

- SMMUv2:

  * Support for a new '->probe_finalize' hook, needed by Nvidia

  * Even more Qualcomm compatible strings

  * Avoid Adreno TTBR1 quirk for DB820C platform

- Misc:

  * Trivial cleanups/refactoring
2021-06-17 16:57:28 +02:00
Marcin Wojtas f2c6d6b271 arm64: dts: ensure backward compatibility of the AP807 Xenon
A recent switch to a dedicated AP807 compatible string for the Xenon
SD/MMC controller result in the driver not being probed when
using updated device tree with the older kernel revisions.
It may also be problematic for other OSs/firmware that use
Linux device tree sources as a reference. Resolve the problem
with backward compatibility by restoring a previous compatible
string as secondary one.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-06-17 15:13:29 +02:00
Pali Rohár 3a52a48973 arm64: dts: marvell: armada-37xx: move firmware node to generic dtsi file
Move the turris-mox-rwtm firmware node from Turris MOX' device tree into
the generic armada-37xx.dtsi file and use the generic compatible string
'marvell,armada-3700-rwtm-firmware' instead of the current one.

Turris MOX DTS file contains also old compatible string for backward
compatibility.

The Turris MOX rWTM firmware can be used on any Armada 37xx device,
giving them access to the rWTM hardware random number generator, which
is otherwise unavailable.

This change allows Linux to load the turris-mox-rwtm.ko module on these
boards.

Tested on ESPRESSObin v5 with both default Marvell WTMI firmware and
CZ.NIC's firmware. With default WTMI firmware the turris-mox-rwtm fails
to probe, while with CZ.NIC's firmware it registers the HW random number
generator.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-06-17 15:03:59 +02:00
Hao Fang e3211e414d arm64: dts: hisilicon: use the correct HiSilicon copyright
s/Hisilicon/HiSilicon/.
It should use capital S, according to the official website
https://www.hisilicon.com/en.

Signed-off-by: Hao Fang <fanghao11@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-06-17 01:28:15 +00:00
Olof Johansson 194eb4eab5 Amlogic ARM64 DT changes for v5.14 round 2:
-  various fixes for Odroid C4/HC4 regulators handling, USB and SPI NOR Flash for HC4
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Merge tag 'amlogic-arm64-dt-for-v5.14-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/dt

Amlogic ARM64 DT changes for v5.14 round 2:
-  various fixes for Odroid C4/HC4 regulators handling, USB and SPI NOR Flash for HC4

* tag 'amlogic-arm64-dt-for-v5.14-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  arm64: dts: meson-sm1-odroid-c4: remove invalid hub_5v regulator
  arm64: dts: meson-sm1-odroid-hc4: add spifc node to ODROID-HC4
  arm64: dts: meson-sm1-odroid-hc4: add regulators controlled by GPIOH_8
  arm64: dts: meson-sm1-odroid-hc4: disable unused USB PHY0
  arm64: dts: meson-sm1-odroid: add 5v regulator gpio
  arm64: dts: meson-sm1-odroid: set tf_io regulator gpio as open source
  arm64: dts: meson-sm1-odroid: add missing enable gpio and supply for tf_io regulator

Link: https://lore.kernel.org/r/c953e97a-f901-a749-1fb6-b1caa75b4748@baylibre.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-16 17:32:58 -07:00
Olof Johansson c8700d80d7 Visconti defconfig updates for v5.14
- Enable Visconti's PWM in the ARM64 defconfig as a module.
 - Enable Visconti's GPIO in the ARM64 defconfig.
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Merge tag 'visconti-arm-defconfig-for-v5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti into arm/defconfig

Visconti defconfig updates for v5.14

- Enable Visconti's PWM in the ARM64 defconfig as a module.
- Enable Visconti's GPIO in the ARM64 defconfig.

* tag 'visconti-arm-defconfig-for-v5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti:
  arm64: defconfig: Visconti: Enable GPIO
  arm64: defconfig: Visconti: Enable PWM

Link: https://lore.kernel.org/r/20210615231232.pllzlqoamkmnsqq6@toshiba.co.jp
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-16 17:32:28 -07:00
Aswath Govindraju 3de27ef12c arm64: dts: ti: k3-am64-main: Update TF-A load address to workaround USB DFU limitation
Due to a limitation for USB DFU boot mode, SPL load address has to be less
than  or equal to 0x70001000. So, load address of SPL and TF-A have been
moved to 0x70000000 and 0x701c0000 respectively, in U-Boot version 2021.10.

Therefore, update TF-A's location in the device tree node.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210616171224.24635-4-a-govindraju@ti.com
2021-06-16 19:06:52 -05:00
Aswath Govindraju 454a9d4aaa arm64: dts: ti: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication
The final 128KB in SRAM is reserved by default for DMSC-lite code and
secure proxy communication buffer. The memory region used for DMSC-lite
code can be optionally freed up by secure firmware API[1]. However, the
buffer for secure proxy communication is not configurable. This default
hardware configuration is unique for AM64.

Therefore, indicate the area reserved for DMSC-lite code and secure proxy
communication buffer in the oc_sram device tree node.

[1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210616171224.24635-3-a-govindraju@ti.com
2021-06-16 19:05:28 -05:00
Aswath Govindraju 263820efa3 arm64: dts: ti: k3-am64-main: Update TF-A's maximum size and node name
The maximum size of TF-A 2.5 has been increased to 0x1c000 [1]. In order to
account for future expansions too, increase the allocated size for TF-A to
0x20000, in the device tree node.

Also, update the node name to "tfa-sram".

[1] - https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=2fb5312f61a7de8b7a70e1639199c4f14a10b6f9

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210616171224.24635-2-a-govindraju@ti.com
2021-06-16 19:05:28 -05:00
Konrad Dybcio b135d097eb arm64: dts: qcom: sm8[12]50-pm8150: Move RESIN to pm8150 dtsi
It's not worth duplicating the same node over and over and over and over again,
so let's keep the common bits in the pm8150 DTSI, making only changing the
status and keycode necessary.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613124822.124039-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 21:34:27 -05:00
Konrad Dybcio 69cdb97ef6 arm64: dts: qcom: sm8250: Add support for SONY Xperia 1 II / 5 II (Edo platform)
Add support for SONY Xperia 1 II and 5 II smartphones (read one/five mark two).
They are based on the Qualcomm SM8250 chipset and both feature 5G modems. There
also exists a third Edo board, namely the Xperia PRO (PDX204), but it's $2500
and no developers have obtained it so far (to my knowledge).

The devices are affected by a scary UFS behaviour where sending a certain UFS
command (which is worked around on downstream) renders the device unbootable,
by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly
disabled for now.

Downstream workaround:
2e7a9ee1c9

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-4-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 19:38:58 -05:00
Konrad Dybcio 759488004f arm64: dts: qcom: sm8250: Move gpio.h inclusion to SoC DTSI
Almost any board that boots and has a way to interact with it
(say for the rare cases of just-pstore or let's-rely-on-bootloader-setup)
needs to set some GPIOs, so it makes no sense to include gpio.h separately
each time. Hence move it to SoC DTSI.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 19:34:42 -05:00
Konrad Dybcio 8eaa6501ef arm64: dts: qcom: sm8250: Add SDHCI2 sleep mode pinctrl
Add required pins for SDHCI2, so that the interface can work reliably.
This commit adds sleep_state setup to the SoC DTSI, as it is common for
all boards.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 19:33:59 -05:00
Vinod Koul 8ae030c34d arm64: defconfig: Enable renesas usb xhci pci host controller
96Boards RB3 has a USB XHCI PCI Renesas host controller. This controller
requires firmware to be loaded on its ROM/RAM, so enable the module
CONFIG_USB_XHCI_PCI_RENESAS. This depends on CONFIG_USB_XHCI_PCI so
enable that as well.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210615081749.3210344-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 19:19:58 -05:00
Konrad Dybcio d0a6ce59ea arm64: dts: qcom: sm8150: Add support for SONY Xperia 1 / 5 (Kumano platform)
Add support for SONY Xperia 1 and 5 smartphones, both based on the
Qualcomm SM8150 chipset. There also exist 5G-capable versions of these
devices, but they weren't sold much (if at all) outside Japan.

The devices are affected by a scary UFS behaviour where sending a certain UFS
command (which is worked around on downstream) renders the device unbootable,
by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly
disabled for now.

Downstream workaround:
2e7a9ee1c9

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> (On Bahamut)
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210611203301.101067-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 18:59:11 -05:00
Konrad Dybcio b1dc3c6b3d arm64: dts: qcom: sm8150: Disable Adreno and modem by default
Components that rely on proprietary (not to mention signed!) firmware should
not be enabled by default, as lack of the aforementioned firmware could cause
various issues, from random errors to straight-up failing to boot.

Not enabling modem back on the HDK, as it uses a sa8150.

Also fixed a sorting mistake in both boards' dt while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210611203301.101067-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 18:54:12 -05:00
Konrad Dybcio ece28cb5ed arm64: dts: qcom: sm8250: Disable Adreno and Venus by default
Components that rely on proprietary (not to mention signed!) firmware should
not be enabled by default, as lack of the aforementioned firmware could cause
various issues, from random errors to straight-up failing to boot.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210612192358.62602-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 18:37:06 -05:00
Konrad Dybcio 15049bb597 arm64: dts: qcom: sm8250: Add GPI DMA nodes
Add and configure GPI DMA nodes to enable the way for peripherals to make
DMA transfers.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210614235630.445501-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 18:36:33 -05:00
Konrad Dybcio dc2f86369b arm64: dts: qcom: sm8250: Fix pcie2_lane unit address
The previous one was likely a mistaken copy from pcie1_lane.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613185334.306225-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 18:33:51 -05:00
Konrad Dybcio 40f7d36db8 arm64: dts: qcom: sm8250: Add size/address-cells to dsi[01]
Add the aforementioned properties in the SoC DTSI so that everybody doesn't
have to copy that into their device DTs, effectively reducing code
duplication.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613114356.82358-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 18:33:47 -05:00
Konrad Dybcio 0c25dad9f2 arm64: dts: qcom: sm8250: Don't disable MDP explicitly
DPU/MDSS is borderline useless without MDP, so disabling
both of them makes little sense. With this change, enabling
mdss will be enough.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613110635.46537-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-15 18:33:40 -05:00
Dong Aisheng 7957a3db01 arm64: head: fix code comments in set_cpu_boot_mode_flag
Up to here, the CPU boot mode can either be EL1 or EL2.
Correct the code comments a bit.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210518101405.1048860-5-aisheng.dong@nxp.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 19:05:28 +01:00
Dong Aisheng f91671b541 arm64: mm: drop unused __pa(__idmap_text_start)
x5 is not used in the following map_memory. Instead,
__pa(__idmap_text_start) is stored in x3 which is used later.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210518101405.1048860-4-aisheng.dong@nxp.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 19:05:28 +01:00
Dong Aisheng c70fe14f83 arm64: mm: fix the count comments in compute_indices
'count - 1' is confusing and not comply with the real code running.
'count' actually represents the extra entries required, no need minus 1.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210518101405.1048860-3-aisheng.dong@nxp.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 19:05:28 +01:00
Anshuman Khandual 9163f01130 arm64/mm: Fix ttbr0 values stored in struct thread_info for software-pan
When using CONFIG_ARM64_SW_TTBR0_PAN, a task's thread_info::ttbr0 must be
the TTBR0_EL1 value used to run userspace. With 52-bit PAs, the PA must be
packed into the TTBR using phys_to_ttbr(), but we forget to do this in some
of the SW PAN code. Thus, if the value is installed into TTBR0_EL1 (as may
happen in the uaccess routines), this could result in UNPREDICTABLE
behaviour.

Since hardware with 52-bit PA support almost certainly has HW PAN, which
will be used in preference, this shouldn't be a practical issue, but let's
fix this for consistency.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Fixes: 529c4b05a3 ("arm64: handle 52-bit addresses in TTBR")
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/1623749578-11231-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 19:03:24 +01:00
Olof Johansson d7fe0d42b5 arm64: tegra: Device tree changes for v5.14-rc1
Contains changes to consolidate audio card names, adds audio support on
 Jetson Xavier NX and enables SMMU on Tegra194.
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Merge tag 'tegra-for-5.14-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.14-rc1

Contains changes to consolidate audio card names, adds audio support on
Jetson Xavier NX and enables SMMU on Tegra194.

* tag 'tegra-for-5.14-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Enable SMMU support on Tegra194
  arm64: tegra: Hook up memory controller to SMMU on Tegra186
  arm64: tegra: Use correct compatible string for Tegra186 SMMU
  arm64: tegra: Audio graph sound card for Jetson Xavier NX
  arm64: tegra: Consolidate audio card names
  arm64: tegra: Add PMU node for Tegra194

Link: https://lore.kernel.org/r/20210611164437.3568059-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-15 08:37:30 -07:00
Olof Johansson e6640fa697 Visconti device tree updates for 5.14
- Add DT support for Toshiba Visconti5 PWM driver
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Merge tag 'visconti-arm-dt-for-v5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti into arm/dt

Visconti device tree updates for 5.14

- Add DT support for Toshiba Visconti5 PWM driver

* tag 'visconti-arm-dt-for-v5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti:
  arm64: dts: visconti: Add PWM support for TMPV7708 SoC

Link: https://lore.kernel.org/r/20210614234654.2u3xetnn5rwhymwz@toshiba.co.jp
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-15 08:18:11 -07:00
Olof Johansson 2e2ec371a4 Qualcomm ARM64 DT updates for v5.14
MSM8916 gains new support for Huawei Ascend G7, with NFC, sensors and
 touchscreen. The Samsung Galaxy A3/A5 gains battery support, touch keys,
 NFC.
 
 MSM8996 received more cleanup and refactoring, preparing for upcoming
 new devices. Note worthy is the long pending enablement of CPUfreq.
 
 SC7180 continues to stabilize, with a range of small fixes for various
 bits and pieces, and new revisions for the CoachZ and pompom devices.
 
 SC7280 continues to grow, with more clock controllers, thermal sensors,
 thermal zones, CPUfreq and interconnect providers.
 
 Xiaomi Poco F1 gaines audio support and the OnePlus 6/6T gaines IPA
 support.
 
 SM8350 gains some cleanups and the IPA device is enabled.
 
 Initial support for the Microsoft Surface Duo, based on SM8150, is
 added.
 
 IPQ8074 gained support for the HK10 board.
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Merge tag 'qcom-arm64-for-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DT updates for v5.14

MSM8916 gains new support for Huawei Ascend G7, with NFC, sensors and
touchscreen. The Samsung Galaxy A3/A5 gains battery support, touch keys,
NFC.

MSM8996 received more cleanup and refactoring, preparing for upcoming
new devices. Note worthy is the long pending enablement of CPUfreq.

SC7180 continues to stabilize, with a range of small fixes for various
bits and pieces, and new revisions for the CoachZ and pompom devices.

SC7280 continues to grow, with more clock controllers, thermal sensors,
thermal zones, CPUfreq and interconnect providers.

Xiaomi Poco F1 gaines audio support and the OnePlus 6/6T gaines IPA
support.

SM8350 gains some cleanups and the IPA device is enabled.

Initial support for the Microsoft Surface Duo, based on SM8150, is
added.

IPQ8074 gained support for the HK10 board.

* tag 'qcom-arm64-for-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (85 commits)
  arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card
  arm64: dts: sc7280: Add interconnect provider DT nodes
  arm64: dts: qcom: msm8916-huawei-g7: Add NFC
  arm64: dts: qcom: msm8916-huawei-g7: Add display regulator
  arm64: dts: qcom: msm8916-huawei-g7: Add sensors
  arm64: dts: qcom: msm8916-huawei-g7: Add touchscreen
  arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7
  arm64: dts: qcom: sc7180-trogdor: Update flash freq to match reality
  arm64: dts: qcom: sc7180: Add wakeup delay for adau codec
  arm64: dts: qcom: sdm845: Remove cros-pd-update on Cheza
  arm64: dts: qcom: sc7180: Remove cros-pd-update on Trogdor
  arm64: dts: qcom: sc7180: Disable PON on Trogdor
  arm64: dts: qcom: sc7180: Modify SPI_CLK voltage level for trogdor
  arm64: dts: qcom: add initial device-tree for Microsoft Surface Duo
  arm64: dts: qcom: sdm845-mtp: enable IPA
  arm64: dts: qcom: sc7180: SD-card GPIO pin set bias-pull up
  arm64: dts: qcom: sc7180: Move sdc pinconf to board specific DT files
  arm64: dts: qcom: msm8916-samsung-a2015: Add NFC
  arm64: dts: qcom: msm8916-samsung-a2015: Add rt5033 battery
  arm64: dts: qcom: msm8916-samsung-a5u: Add touch key regulator
  ...

Link: https://lore.kernel.org/r/20210614223712.393096-1-bjorn.andersson@linaro.org
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-15 08:14:59 -07:00
Olof Johansson 3e7e3b9748 Qualcomm ARM64 defconfig udpates for v5.14
This enables VADC, audio codecs and Venus (video decoder) found on
 MSM8916 among others and the SM8350 interconnect provider driver.
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Merge tag 'qcom-arm64-defconfig-for-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/defconfig

Qualcomm ARM64 defconfig udpates for v5.14

This enables VADC, audio codecs and Venus (video decoder) found on
MSM8916 among others and the SM8350 interconnect provider driver.

* tag 'qcom-arm64-defconfig-for-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  arm64: defconfig: add drivers needed for DragonBoard410c
  arm64: defconfig: qcom: enable interconnect for SM8350

Link: https://lore.kernel.org/r/20210614223704.393042-1-bjorn.andersson@linaro.org
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-15 08:13:53 -07:00
Olof Johansson a996c70e4d Samsung defconfig changes for v5.14
1. Enable Exynos Universal Flash Storage (UFS) driver for Exynos7 arm64
    boards.
 2. Restore framebuffer support in exynos_defconfig.
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Merge tag 'samsung-defconfig-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/defconfig

Samsung defconfig changes for v5.14

1. Enable Exynos Universal Flash Storage (UFS) driver for Exynos7 arm64
   boards.
2. Restore framebuffer support in exynos_defconfig.

* tag 'samsung-defconfig-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: exynos_defconfig: restore framebuffer support
  arm64: defconfig: Enable Exynos UFS driver

Link: https://lore.kernel.org/r/20210614193309.20248-3-krzysztof.kozlowski@canonical.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-15 08:13:06 -07:00
Krzysztof Kozlowski c2d0501cdc arm64: dts: exynos: enable PMIC wakeup from suspend on TM2
The RTC on S2MPS13 PMIC can wakeup the system from suspend to RAM.
Add a generic property for this.

Link: https://lore.kernel.org/r/20210614193309.20248-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210420164943.11152-11-krzysztof.kozlowski@canonical.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-15 08:12:45 -07:00
Olof Johansson dfde897bb1 i.MX defconfig update for 5.14:
- Enable LT8912B DRM bridge and Layerscape EDAC driver support in arm64
   defconfig.
 - Enable WiFi ath10k SDIO driver in imx_v6_v7_defconfig.
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Merge tag 'imx-defconfig-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig

i.MX defconfig update for 5.14:

- Enable LT8912B DRM bridge and Layerscape EDAC driver support in arm64
  defconfig.
- Enable WiFi ath10k SDIO driver in imx_v6_v7_defconfig.

* tag 'imx-defconfig-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx_v6_v7_defconfig: Select the Wifi ath10k sdio driver
  arm64: defconfig: enable Layerscape EDAC driver
  arm64: defconfig: Enable LT8912B DRM bridge driver

Link: https://lore.kernel.org/r/20210613082544.16067-6-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-15 08:12:14 -07:00
Olof Johansson 989e7e357c i.MX arm64 device tree chagnes for 5.14:
- New board support: i.MX8MM Gateworks GW7901 board.
 - Add SPBA bus description for i.MX8MN and i.MX8MM.
 - A series of update on imx8mq-nitrogen board to add USB OTG/Host and
   LT8912 MIPI-DSI to HDMI support.
 - Correct enet clock description for i.MX8 Connection Subsystem.
 - A couple of patches from Heiko Schocher to add FlexSPI device for
   i.MX8MP SoC and enable SPI NOR Flash support on imx8mp-phycore-som.
 - Remove the reference to audio IPG clock on i.MX8MP.
 - Enable EQOS Ethernet and PMIC device support for imx8mp-evk.
 - Disable USB over-current on imx8mm-evk and imx8mn-evk.
 - Add dma-ranges description for i.MX8MM and i.MX8MN SoC.
 - Add PCIe clock description for i.MX8MQ SoC.
 - Enable PCIe support on freeway board.
 - Enable OPTEE support on ls1028a-rdb board.
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Merge tag 'imx-dt64-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree chagnes for 5.14:

- New board support: i.MX8MM Gateworks GW7901 board.
- Add SPBA bus description for i.MX8MN and i.MX8MM.
- A series of update on imx8mq-nitrogen board to add USB OTG/Host and
  LT8912 MIPI-DSI to HDMI support.
- Correct enet clock description for i.MX8 Connection Subsystem.
- A couple of patches from Heiko Schocher to add FlexSPI device for
  i.MX8MP SoC and enable SPI NOR Flash support on imx8mp-phycore-som.
- Remove the reference to audio IPG clock on i.MX8MP.
- Enable EQOS Ethernet and PMIC device support for imx8mp-evk.
- Disable USB over-current on imx8mm-evk and imx8mn-evk.
- Add dma-ranges description for i.MX8MM and i.MX8MN SoC.
- Add PCIe clock description for i.MX8MQ SoC.
- Enable PCIe support on freeway board.
- Enable OPTEE support on ls1028a-rdb board.

* tag 'imx-dt64-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (24 commits)
  arm64: dts: imx8mn-evk: disable over current for usb
  arm64: dts: imx8mm-evk: disable over current for usb1
  arm64: dts: freescale: Separate each group of data in the property 'reg'
  arm64: dts: imx8: conn: fix enet clock setting
  arm64: dts: imx8mq: assign PCIe clocks
  arm64: dts: imx8mn: specify dma-ranges
  arm64: dts: imx8mm: specify dma-ranges
  arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
  arm64: dts: imx8mn-beacon-som: Assign PMIC clock
  arm64: dts: ls208xa: remove bus-num from dspi node
  arm64: dts: ls1012a: enable PCIe on freeway board
  arm64: dts: imx8mp-evk: enable EQOS ethernet
  arm64: dts: imx8mp: Remove the reference to audio ipg clock on imx8mp
  arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy
  arm64: dts: imx8mm: Add spba1 and spba2 buses
  arm64: dts: imx8mn: Add spba1 bus
  arm64: dts: imx8mq-nitrogen: add lt8912 MIPI-DSI to HDMI
  arm64: dts: imx8mq-nitrogen: add USB HOST support
  arm64: dts: imx8mq-nitrogen: add USB OTG support
  arm64: dts: imx8mp-phycore-som: enable spi nor
  ...

Link: https://lore.kernel.org/r/20210613082544.16067-5-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-15 08:11:56 -07:00
Gavin Shan 84c5e23ede arm64: mm: Pass original fault address to handle_mm_fault()
Currently, the lower bits of fault address is cleared before it's
passed to handle_mm_fault(). It's unnecessary since generic code
does same thing since the commit 1a29d85eb0 ("mm: use vmf->address
instead of of vmf->virtual_address").

This passes the original fault address to handle_mm_fault() in case
the generic code needs to know the exact fault address.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20210614122701.100515-1-gshan@redhat.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 12:39:30 +01:00
Anshuman Khandual 4aaa87ab3d arm64/mm: Drop SECTION_[SHIFT|SIZE|MASK]
SECTION_[SHIFT|SIZE|MASK] are essentially PMD_[SHIFT|SIZE|MASK]. But these
create confusion being similar to generic sparsemem memory sections, which
are derived from SECTION_SIZE_BITS. Section references have always implied
PMD level block mapping. Instead just use all PMD level macros which would
make it explicit and also remove confusion with sparsmem memory sections.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/1623658706-7182-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 12:08:39 +01:00
Anshuman Khandual ca6ece6a76 arm64/mm: Use CONT_PMD_SHIFT for ARM64_MEMSTART_SHIFT
ARM64_MEMSTART_SIZE needs to be aligned with CONT_PMD_SIZE on 16K page size
config. Hence just directly use CONT_PMD_SHIFT.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/1623663755-8949-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 12:08:25 +01:00
Anshuman Khandual 0f473ac746 arm64/mm: Drop SWAPPER_INIT_MAP_SIZE
The commit cdef5f6e9e ("arm64: mm: allocate pagetables anywhere") had
dropped the last reference to SWAPPER_INIT_MAP_SIZE. Hence just clean up.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Link: https://lore.kernel.org/r/1623665411-20055-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 12:08:11 +01:00
Daniel Kiss d053e71ac8 arm64: Conditionally configure PTR_AUTH key of the kernel.
If the kernel is not compiled with CONFIG_ARM64_PTR_AUTH_KERNEL=y,
then no PACI/AUTI instructions are expected while the kernel is running
so the kernel's key will not be used. Write of a system registers
is expensive therefore avoid if not required.

Signed-off-by: Daniel Kiss <daniel.kiss@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210613092632.93591-3-daniel.kiss@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 11:32:31 +01:00
Daniel Kiss b27a9f4119 arm64: Add ARM64_PTR_AUTH_KERNEL config option
This patch add the ARM64_PTR_AUTH_KERNEL config and deals with the
build aspect of it.

Userspace support has no dependency on the toolchain therefore all
toolchain checks and build flags are controlled the new config
option.
The default config behavior will not be changed.

Signed-off-by: Daniel Kiss <daniel.kiss@arm.com>
Acked-by: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210613092632.93591-2-daniel.kiss@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-15 11:32:31 +01:00
Nobuhiro Iwamatsu d1588b22dc arm64: defconfig: Visconti: Enable GPIO
Enable Visconti's GPIO in the ARM64 defconfig.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-06-15 09:03:32 +09:00
Nobuhiro Iwamatsu 1ba39c2b8b arm64: defconfig: Visconti: Enable PWM
Enable Visconti's PWM in the ARM64 defconfig as a module.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-06-15 09:03:32 +09:00
Nobuhiro Iwamatsu 172cdcaefe arm64: dts: visconti: Add PWM support for TMPV7708 SoC
Add PWM node in TMPV7708's dtsi, and tmpv7708-rm-mbrc boards's dts.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-06-15 08:25:28 +09:00
Marek Szyprowski e9cd414c11 arm64: defconfig: add drivers needed for DragonBoard410c
Add modules with drivers needed for DragonBoard410c board
(arch/arm64/boot/dts/qcom/apq8016-sbc.dts).

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20210528140625.6972-1-m.szyprowski@samsung.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-14 16:59:27 -05:00
Shaik Sajida Bhanu 81cfa462e4 arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card
The calculations for the DLL register values are based on the clock rate
of the reference clock. Provide the reference clock in the definition of
the two SDHCI controllers to not rely on the default values.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Link: https://lore.kernel.org/r/1623309107-27833-1-git-send-email-sbhanu@codeaurora.org
[bjorn: Rewrote commit message]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-14 11:29:46 -05:00
Mark Rutland 590e8a082a CFI: Move function_nocfi() into compiler.h
Currently the common definition of function_nocfi() is provided by
<linux/mm.h>, and architectures are expected to provide a definition in
<asm/memory.h>. Due to header dependencies, this can make it hard to use
function_nocfi() in low-level headers.

As function_nocfi() has no dependency on any mm code, nor on any memory
definitions, it doesn't need to live in <linux/mm.h> or <asm/memory.h>.
Generally, it would make more sense for it to live in
<linux/compiler.h>, where an architecture can override it in
<asm/compiler.h>.

Move the definitions accordingly.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Nathan Chancellor <nathan@kernel.org>
Cc: Sami Tolvanen <samitolvanen@google.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20210602153701.35957-1-mark.rutland@arm.com
2021-06-14 09:12:09 -07:00
Vignesh Raghavendra d65f069e50 arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes
8250_omap compatible UART IPs on all SoCs have registers aligned at 4
byte address boundary and constant byte addressability. Thus there is no
need for reg-io-width or reg-shift DT properties.  These properties are
not used by 8250_omap driver nor documented as part of binding document.
Therefore drop them.

This is in preparation to move omap-serial.txt to YAML format.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com
2021-06-14 09:29:57 -05:00
Aswath Govindraju d3f1b155c0 arm64: dts: ti: k3-am642-evm: align ti,pindir-d0-out-d1-in property with dt-shema
ti,pindir-d0-out-d1-in property is expected to be of type boolean.
Therefore, fix the property accordingly.

Fixes: 4fb6c04683 ("arm64: dts: ti: k3-am642-evm: Add support for SPI EEPROM")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210608051414.14873-3-a-govindraju@ti.com
2021-06-14 09:29:56 -05:00
Aswath Govindraju 4f76ea7b4d arm64: dts: ti: am65: align ti,pindir-d0-out-d1-in property with dt-shema
ti,pindir-d0-out-d1-in property is expected to be of type boolean.
Therefore, fix the property accordingly.

Fixes: e180f76d06 ("arm64: dts: ti: Add support for Siemens IOT2050 boards")
Fixes: 5da94b5047 ("arm64: dts: ti: k3-am654: Enable main domain McSPI0")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210608051414.14873-2-a-govindraju@ti.com
2021-06-14 09:29:56 -05:00
Grygorii Strashko 50c9bfca1b arm64: dts: ti: k3-am642-main: fix ports mac properties
The current device tree CPSW3g node adds non-zero "mac-address" property to
the ports, which prevents random MAC address assignment to network devices
if bootloader failed to update DT. This may cause more then one host to
have the same MAC in the network.

 mac-address = [00 00 de ad be ef];
 mac-address = [00 01 de ad be ef];

In addition, there is one MAC address available in eFuse registers which
can be used for default port 1.

Hence, fix ports MAC properties by:
- resetting "mac-address" property to 0
- adding ti,syscon-efuse = <&main_conf 0x200> to Port 1

Fixes: 3753b12877 ("arm64: dts: ti: k3-am64-main: Add CPSW DT node")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210608184940.25934-1-grygorii.strashko@ti.com
2021-06-14 09:29:56 -05:00
Neil Armstrong 303d2af21a arm64: dts: meson-sm1-odroid-c4: remove invalid hub_5v regulator
Drop the hub_5v regulator which controls the HUB Reset line with GPIOH_4 which
is already controlled by a GPIO HOG.

Until we can properly describe how to control USB HUBs reset lines, keeping
the GPIO HOG is an acceptable solution we use on multiple boards.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-8-narmstrong@baylibre.com
2021-06-14 09:57:45 +02:00
Christian Hewitt 7178f340e9 arm64: dts: meson-sm1-odroid-hc4: add spifc node to ODROID-HC4
Add a node for the XT25F128B SPI-NOR flash to make it accessible
from Linux.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-7-narmstrong@baylibre.com
2021-06-14 09:57:45 +02:00
Neil Armstrong 164147f094 arm64: dts: meson-sm1-odroid-hc4: add regulators controlled by GPIOH_8
As described in the HC4 schematics, GPIOH_8 controls the USB 5V and 12V
regulators used to power the SATA drives.

And is set as Open Drain since this GPIO doesn't support Push-Pull.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-6-narmstrong@baylibre.com
2021-06-14 09:57:45 +02:00
Neil Armstrong 703e84d661 arm64: dts: meson-sm1-odroid-hc4: disable unused USB PHY0
As described in the HC4 schematics, only the USB port B is used,
port A is left unconnected. Thus disable PHY0 and remove it from PHYs list.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-5-narmstrong@baylibre.com
2021-06-14 09:57:45 +02:00
Neil Armstrong 45d736ab17 arm64: dts: meson-sm1-odroid: add 5v regulator gpio
As described in the Odroid-C4 & Odroid-HC4 schematics, the 5V regulator is controlled
by GPIOH_8 and in Open Drain since this GPIO doesn't support Push-Pull.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-4-narmstrong@baylibre.com
2021-06-14 09:57:45 +02:00
Neil Armstrong 7881df5136 arm64: dts: meson-sm1-odroid: set tf_io regulator gpio as open source
According to Odroid-C4 & HC4 Schematics, the TF_3V3N_1V8_EN can be in Hi-Z for 3v3,
and since it's the default GPIOAO_6 mode at reset, let switch this GPIO as Open-Source
to drive for 1, and input for 0.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-3-narmstrong@baylibre.com
2021-06-14 09:57:45 +02:00
Neil Armstrong 1f80a5cf74 arm64: dts: meson-sm1-odroid: add missing enable gpio and supply for tf_io regulator
As described in the schematics of Odroid-C4 and Odroid-HC4, the TF_IO regulator
is enabled by the GPIOE_2 GPIO and gets it's supply from VCC_5V.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-2-narmstrong@baylibre.com
2021-06-14 09:57:45 +02:00
Guenter Roeck ab6cef1d14 ARM: 9095/1: ARM64: Remove arm_pm_restart()
All users of arm_pm_restart() have been converted to use the kernel
restart handler.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2021-06-13 18:16:47 +01:00
Uwe Kleine-König 51094deb33 arm64: dts: rockchip: Add support for USB on helios64
This enables the USB hardware needed to access devices on the sockets J1
and J13.

Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Link: https://lore.kernel.org/r/20210611081414.1448786-1-uwe@kleine-koenig.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-13 18:18:42 +02:00
Olof Johansson e60cb06cde Fix PCIe address ranges that are affected by recent PCI changes.
There are 3 additional patches pending that handle the backward
 compatiblity inside the PCI subsystem, but the address ranges
 should be fixed anyway.
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Merge tag 'v5.13-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes

Fix PCIe address ranges that are affected by recent PCI changes.
There are 3 additional patches pending that handle the backward
compatiblity inside the PCI subsystem, but the address ranges
should be fixed anyway.

* tag 'v5.13-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory

Link: https://lore.kernel.org/r/3405741.0S5aU1g85B@diego
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:55:17 -07:00
Olof Johansson b0545d11a9 Our usual bunch of patches to improve the Allwinner SoCs support,
mainly:
   - I2S Support for the V3
   - Audio Codec Support for the V3s
   - DMA support for the V3s
   - PWM support for the V3s
   - Support for Bluetooth Audio on the pinephone
   - Add A10-like timers to the A64 and R40
   - New boards: Forlinx OKA40i-C, Forlinx OKA40i-C, NanoPi R1S H5
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Merge tag 'sunxi-dt-for-5.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Our usual bunch of patches to improve the Allwinner SoCs support,
mainly:
  - I2S Support for the V3
  - Audio Codec Support for the V3s
  - DMA support for the V3s
  - PWM support for the V3s
  - Support for Bluetooth Audio on the pinephone
  - Add A10-like timers to the A64 and R40
  - New boards: Forlinx OKA40i-C, Forlinx OKA40i-C, NanoPi R1S H5

* tag 'sunxi-dt-for-5.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (29 commits)
  ARM: dts: sun8i: v3s: enable emac for zero Dock
  arm64: dts: allwinner: pinephone: Set audio card name
  ARM: dts: sun8i: r40: Add timer node
  ARM: dts: sun8i: V3: add I2S interface to V3 dts
  dt-bindings: sound: sun4i-i2s: add Allwinner V3 I2S compatible
  ARM: dts: sun8i: V3: add codec analog frontend to V3 dts
  ASoC: dt-bindings: sun8i-a23-codec-analog: add compatible for Allwinner V3
  ARM: dts: sun8i: v3s: add analog codec and frontend to v3s dts
  ARM: dts: sun8i: v3s: add DMA properties to peripherals supporting DMA
  ARM: dts: sun8i: v3s: add DMA controller to v3s dts
  ARM: dts: sun8i: v3s: add pwm controller to v3s dts
  dt-bindings: pwm: allwinner: add v3s pwm compatible
  arm64: dts: allwinner: h5: Add NanoPi R1S H5 support
  dt-bindings: arm: Add NanoPi R1S H5
  arm64: dts: allwinner: pinephone: Add support for Bluetooth audio
  arm64: dts: allwinner: a64: Allow multiple DAI links
  arm64: dts: allwinner: a64: Add pinmux nodes for AIF2/AIF3
  arm64: dts: allwinner: a64: Allow using multiple codec DAIs
  ARM: dts: sun8i-a33: Allow using multiple codec DAIs
  ASoC: dt-bindings: sun8i-codec: Increase #sound-dai-cells
  ...

Link: https://lore.kernel.org/r/96cc77ec-139d-4685-8a66-a60964cf39fd.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:54:30 -07:00
Olof Johansson 2f80e8b45c One patch to select one of our timer in the arm64 Kconfig option.
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Merge tag 'sunxi-core-for-5.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/soc

One patch to select one of our timer in the arm64 Kconfig option.

* tag 'sunxi-core-for-5.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: sunxi: Build the sun4i timer driver

Link: https://lore.kernel.org/r/bf3431f6-2196-425c-9b43-0bf4de0b6d30.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:54:03 -07:00
Olof Johansson 37c2a42930 Two patches to fix the GMAC PHY mode on some boards.
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Merge tag 'sunxi-fixes-for-5.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes

Two patches to fix the GMAC PHY mode on some boards.

* tag 'sunxi-fixes-for-5.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: a64-sopine-baseboard: change RGMII mode to TXID
  ARM: dts: sun8i: h3: orangepi-plus: Fix ethernet phy-mode

Link: https://lore.kernel.org/r/ad7ba352-315c-4201-b922-4bf914a00d98.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:53:40 -07:00
Olof Johansson 65a4030123 - Delete MTK_PMIC_WRAP added twice.
- Set MMC_MTK as built-in to be able to boot from MMC device.
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Merge tag 'v5.13-next-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/defconfig

- Delete MTK_PMIC_WRAP added twice.
- Set MMC_MTK as built-in to be able to boot from MMC device.

* tag 'v5.13-next-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: defconfig: Allow Mediatek boards to boot from the mmc
  arm64: defconfig: Do not override the MTK_PMIC_WRAP symbol

Link: https://lore.kernel.org/r/ad6f7f4e-7e4d-08b9-8781-71bd78444929@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:48:22 -07:00
Olof Johansson 796f0ae8e7 mt8173:
- split hardware encoder block into two devices.
 
 mt8167:
 - add pm domains, multi-media system (mmsys), SMI, local arbiter
   (larb) and IOMMU nodes.
 
 mt8183:
 - Add new chromebooks: HP Chromebook 11a, Acer Chromebook 311, HP
   Chromebook x360 11MK G3 EE, Lenovo IdeaPad Flex 3.
 - add power domain to SMI common node.
 - add power supplies for EEPROM node.
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Merge tag 'v5.13-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8173:
- split hardware encoder block into two devices.

mt8167:
- add pm domains, multi-media system (mmsys), SMI, local arbiter
  (larb) and IOMMU nodes.

mt8183:
- Add new chromebooks: HP Chromebook 11a, Acer Chromebook 311, HP
  Chromebook x360 11MK G3 EE, Lenovo IdeaPad Flex 3.
- add power domain to SMI common node.
- add power supplies for EEPROM node.

* tag 'v5.13-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (21 commits)
  arm64: dts: mt8183: Add node for the Mali GPU
  arm64: dts: mt8183-kukui: Add tboard thermal zones
  arm64: dts: mt8183: add cbas node under cros_ec
  arm64: dts: mt8183: add supply name for eeprom
  arm64: dts: mt8183: remove syscon from smi_common node
  arm64: dts: mt8183: Add kukui-jacuzzi-fennel board
  arm64: dts: mt8183: Add kukui-jacuzzi-kenzo board
  arm64: dts: mt8183: Add kukui-jacuzzi-burnet board
  arm64: dts: mt8183: Add kukui-jacuzzi-willow board
  arm64: dts: mt8183: Add kukui-jacuzzi-kappa board
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-fennel
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kenzo
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-burnet
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-willow
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kappa
  arm64: dts: mediatek: mt8167: add iommu node
  arm64: dts: mediatek: mt8167: add larb nodes
  arm64: dts: mediatek: mt8167: add smi_common node
  arm64: dts: mediatek: mt8167: add mmsys node
  arm64: dts: mediatek: mt8167: add power domains
  ...

Link: https://lore.kernel.org/r/117d5eb5-bc99-70bb-a1a9-d7141fe96527@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:47:56 -07:00
Olof Johansson d4dd469936 Renesas ARM DT updates for v5.14 (take two)
- External interrupt (INTC-EX) support for the R-Car M3-W+ SoC,
   - Initial support for the new RZ/G2L SoC on the RZ/G2L SMARC EVK
     board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.14 (take two)

  - External interrupt (INTC-EX) support for the R-Car M3-W+ SoC,
  - Initial support for the new RZ/G2L SoC on the RZ/G2L SMARC EVK
    board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r9a07g044: Add SYSC node
  arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK
  arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's
  dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
  arm64: dts: renesas: r8a779a0: Drop power-domains property from GIC node
  arm64: dts: renesas: r8a77961: Add INTC-EX device node
  ARM: dts: silk: Configure pull-up for SOFT_SW GPIO keys
  ARM: dts: gose: Configure pull-up for SOFT_SW GPIO keys
  ARM: dts: blanche: Configure pull-up for SOFT_SW and SW25 GPIO keys
  ARM: dts: lager: Configure pull-up for SOFT_SW GPIO keys
  arm64: dts: renesas: r8a7796[01]: Fix OPP table entry voltages
  arm64: dts: renesas: Add missing opp-suspend properties

Link: https://lore.kernel.org/r/cover.1623403796.git.geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:45:38 -07:00
Olof Johansson f1b1d76afd Renesas ARM defconfig updates for v5.14 (take two)
- Enable support for the new RZ/G2L SoC variants in the arm64
     defconfig.
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Merge tag 'renesas-arm-defconfig-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/defconfig

Renesas ARM defconfig updates for v5.14 (take two)

  - Enable support for the new RZ/G2L SoC variants in the arm64
    defconfig.

* tag 'renesas-arm-defconfig-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: defconfig: Enable ARCH_R9A07G044

Link: https://lore.kernel.org/r/cover.1623403795.git.geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:43:38 -07:00
Olof Johansson 9bfa382935 ARMv8 Juno fix for v5.14
Just a single fix to use standard and generic nodes names for SCMI
 power domain controller and clock controller devicetree nodes.
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Merge tag 'juno-fix-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt

ARMv8 Juno fix for v5.14

Just a single fix to use standard and generic nodes names for SCMI
power domain controller and clock controller devicetree nodes.

* tag 'juno-fix-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: Update SCPI nodes as per the YAML schema

Link: https://lore.kernel.org/r/20210611075805.2813712-1-sudeep.holla@arm.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:42:55 -07:00
Olof Johansson 93d84763c1 This pull request contains Broadcom ARM64-based SoCs changes for 5.14,
please pull the following:
 
 - Zhen fixes the Broadcom stingray serial node unit names to fix a DT
   binding warning
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Merge tag 'arm-soc/for-5.14/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM64-based SoCs changes for 5.14,
please pull the following:

- Zhen fixes the Broadcom stingray serial node unit names to fix a DT
  binding warning

* tag 'arm-soc/for-5.14/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: normalize the node name of the UART devices

Link: https://lore.kernel.org/r/20210610194836.309869-2-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:40:29 -07:00
Olof Johansson 010bf7346f This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.14, please pull the following:
 
 - Rafal updates the BCM5301x, HR2, BCM63xx, BCM5301x, NSP and Cygnus DTS
   files to resolve a number of DT binding check warnings pertaining to
   NAND, pinmux, clocks, SPI
 
 - Stefan provides a fix for an increase in the DWC2 controller's RX FIFO
   causing regressions on the Raspberry Pi 4B
 
 - Mateusz adds a BCM2711 specific VEC compatible string to allow keying
   off that variant properly
 
 - Stefan adds support for the Raspberry Pi 400 by doing some DTS/DTSI
   re-organization work and finally adding the DTS file proper
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Merge tag 'arm-soc/for-5.14/devicetree' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.14, please pull the following:

- Rafal updates the BCM5301x, HR2, BCM63xx, BCM5301x, NSP and Cygnus DTS
  files to resolve a number of DT binding check warnings pertaining to
  NAND, pinmux, clocks, SPI

- Stefan provides a fix for an increase in the DWC2 controller's RX FIFO
  causing regressions on the Raspberry Pi 4B

- Mateusz adds a BCM2711 specific VEC compatible string to allow keying
  off that variant properly

- Stefan adds support for the Raspberry Pi 400 by doing some DTS/DTSI
  re-organization work and finally adding the DTS file proper

* tag 'arm-soc/for-5.14/devicetree' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: Add reference to RPi 400
  ARM: dts: Add Raspberry Pi 400 support
  ARM: dts: bcm283x: Fix up GPIO LED node names
  dt-bindings: arm: bcm2835: Add Raspberry Pi 400 to DT schema
  ARM: dts: Move BCM2711 RPi specific into separate dtsi
  ARM: dts: bcm283x: Fix up MMC node names
  ARM: boot: dts: bcm2711: Add BCM2711 VEC compatible
  Revert "ARM: dts: bcm283x: increase dwc2's RX FIFO size"
  ARM: dts: BCM5301X: Fixup SPI binding
  dt-bindings: clock: brcm, iproc-clocks: convert to the json-schema
  ARM: dts: BCM5301X: Fix pinmux subnodes names
  ARM: dts: Hurricane 2: Fix NAND nodes names
  ARM: dts: BCM63xx: Fix NAND nodes names
  ARM: NSP: dts: fix NAND nodes names
  ARM: Cygnus: dts: fix NAND nodes names
  ARM: brcmstb: dts: fix NAND nodes names
  ARM: dts: BCM5301X: Fix NAND nodes names

Link: https://lore.kernel.org/r/20210610194836.309869-1-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:40:09 -07:00
Olof Johansson c7259477fe Amlogic ARM64 DT changed for v5.14:
- set 128bytes FIFO size on uart A
 - add Banana PI BPI-M5 board dts & bindings
 - meson-sm1: add toacodec node to use internal audio DAC
 - enable hdmi audio loopback on VIM3 board
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Merge tag 'amlogic-arm64-dt-for-v5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/dt

Amlogic ARM64 DT changed for v5.14:
- set 128bytes FIFO size on uart A
- add Banana PI BPI-M5 board dts & bindings
- meson-sm1: add toacodec node to use internal audio DAC
- enable hdmi audio loopback on VIM3 board

* tag 'amlogic-arm64-dt-for-v5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  arm64: dts: meson: set 128bytes FIFO size on uart A
  arm64: dts: meson-sm1: add Banana PI BPI-M5 board dts
  dt-bindings: arm: amlogic: add Banana PI M5 bindings
  arm64: dts: meson-sm1: add toacodec node
  arm64: dts: meson: vim3: enable hdmi audio loopback

Link: https://lore.kernel.org/r/bb207cf8-fc7a-3121-eea8-56618b5952aa@baylibre.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:34:14 -07:00
Olof Johansson 3f43257e3c Renesas ARM defconfig updates for v5.14
- Refresh shmobile_defconfig for v5.13-rc1
   - Enable R-Car USB2 clock selector support
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Merge tag 'renesas-arm-defconfig-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/defconfig

Renesas ARM defconfig updates for v5.14

  - Refresh shmobile_defconfig for v5.13-rc1
  - Enable R-Car USB2 clock selector support

* tag 'renesas-arm-defconfig-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: defconfig: Enable usb2_clksel for R-Car Gen3 and RZ/G2
  ARM: shmobile: defconfig: Refresh for v5.13-rc1

Link: https://lore.kernel.org/r/cover.1622188834.git.geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2021-06-12 08:25:59 -07:00
Li Jun 21cc1f222e arm64: dts: imx8mn-evk: disable over current for usb
imx8mn evk board usb port does not support over current detection,
so disable it.

Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 17:59:43 +08:00
Li Jun 4616c395be arm64: dts: imx8mm-evk: disable over current for usb1
imx8mm evk board usb1 port does not support over current detection,
so disable it.

Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 17:59:43 +08:00
Zhen Lei ce87d93688 arm64: dts: freescale: Separate each group of data in the property 'reg'
Do not write the 'reg' of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar to the following
will be reported by reg.yaml.

arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml:
 soc: pcie@3400000:reg:0: \
 [0, 54525952, 0, 1048576, 64, 0, 0, 8192] is too long

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Dong Aisheng dfda1fd16a arm64: dts: imx8: conn: fix enet clock setting
enet_clk_ref actually is sourced from internal gpr clocks
which needs a default rate. Also update enet lpcg clock
output names to be more straightforward.

Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Lucas Stach 15a5261e4d arm64: dts: imx8mq: assign PCIe clocks
This fixes multiple issues with the current non-existent PCIe clock setup:

The controller can run at up to 250MHz, so use a parent that provides this
clock.

The PHY needs an exact 100MHz reference clock to function if the PCIe
refclock is not fed in via the refclock pads. While this mode is not
supported (yet) in the driver it doesn't hurt to make sure we are
providing a clock with the right rate.

The AUX clock is specified to have a maximum clock rate of 10MHz. So
the current setup, which drives it straight from the 25MHz oscillator is
actually overclocking the AUX input.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Lucas Stach 8d923cdf2e arm64: dts: imx8mn: specify dma-ranges
DMA addressing capabilities on i.MX8MN are limited by the interconnect,
same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
the kernel know about this.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Lucas Stach 4251a3ac4d arm64: dts: imx8mm: specify dma-ranges
DMA addressing capabilities on i.MX8MM are limited by the interconnect,
same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
the kernel know about this.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Kornel Duleba 6bee93d931 arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
Currently all PCIE windows point to bus address 0x0, which does not match
the values obtained from hardware during EA.
Replace those values with CPU addresses, since in reality we
have a 1:1 mapping between the two.

Signed-off-by: Kornel Duleba <mindal@semihalf.com>
Acked-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Adam Ford 1de3aa8611 arm64: dts: imx8mn-beacon-som: Assign PMIC clock
The PMIC throws an errors because the clock isn't assigned to it.
Fix this by assigning the clocks info.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Mian Yousaf Kaukab 8240c972c1 arm64: dts: ls208xa: remove bus-num from dspi node
On LS2088A-RDB board, if the spi-fsl-dspi driver is built as module
then its probe fails with the following warning:

[   10.471363] couldn't get idr
[   10.471381] WARNING: CPU: 4 PID: 488 at drivers/spi/spi.c:2689 spi_register_controller+0x73c/0x8d0
...
[   10.471651] fsl-dspi 2100000.spi: Problem registering DSPI ctlr
[   10.471708] fsl-dspi: probe of 2100000.spi failed with error -16

Reason for the failure is that bus-num property is set for dspi node.
However, bus-num property is not set for the qspi node. If probe for
spi-fsl-qspi happens first then id 0 is dynamically allocated to it.
Call to spi_register_controller() from spi-fsl-dspi driver then fails.
Since commit 29d2daf2c3 ("spi: spi-fsl-dspi: Make bus-num property
optional") bus-num property is optional. Remove bus-num property from
dspi node to fix the issue.

Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Mian Yousaf Kaukab 03ce38ca69 arm64: dts: ls1012a: enable PCIe on freeway board
ls1012a-freeway board contains a M.2 2230 slot. Update the status of
pcei1 node to okay so that the pcie controller can be probed.

Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Joakim Zhang dc6d5dc89b arm64: dts: imx8mp-evk: enable EQOS ethernet
Enable EQOS ethernet on i.MX8MP EVK board.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Jacky Bai 88314aab23 arm64: dts: imx8mp: Remove the reference to audio ipg clock on imx8mp
On i.MX8MP, there is no audio ipg clock, so remove the wrong reference
to this clock in dts file.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Richard Zhu 9b95c44b41 arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy
Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Adam Ford 7923353b62 arm64: dts: imx8mm: Add spba1 and spba2 buses
The i.MX8MM reference manual shows there are two spba busses.
SPBA1 handles much of the serial interfaces, and SPBA2 covers much
of the audio.

Add both of them.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Adam Ford 292e0f487c arm64: dts: imx8mn: Add spba1 bus
The i.MX8MN has an SPBA bus which covers much of the audio, but
there is a second SPBA bus which covers many of the serial interfaces
like SPI and UARTs currently missing from the device tree. The reference
manual calls the bus handling the audio peripherals SPBA2, and the bus
handling the serial peripherals is called SPBA1.

Rename the existing spba bus to spba2 and add spba1.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Adrien Grassein 4b82e1f839 arm64: dts: imx8mq-nitrogen: add lt8912 MIPI-DSI to HDMI
Add support of the lt8912b in the DTB.
This adds the support of the DB_DSIHD daugther board from
Boundary Devices.

Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Adrien Grassein 4a085de205 arm64: dts: imx8mq-nitrogen: add USB HOST support
Add the description for the USB host port.
This port is linked to a resettable USB HUB so handle
this reset signal with a GPIO hog.

Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Adrien Grassein 77a1aa0393 arm64: dts: imx8mq-nitrogen: add USB OTG support
Add the description for the USB OTG port.
The OTG port uses a dedicated regulator for vbus.

Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Heiko Schocher a4f27c75ac arm64: dts: imx8mp-phycore-som: enable spi nor
enable the mt25qu256aba spi nor on the imx8mp-phycore-som.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-06-12 16:17:02 +08:00
Punit Agrawal 8efe01b438 arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory
The PCIe host bridge on RK3399 advertises a single 64-bit memory
address range even though it lies entirely below 4GB.

Previously the OF PCI range parser treated 64-bit ranges more
leniently (i.e., as 32-bit), but since commit 9d57e61bf7 ("of/pci:
Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses")
the code takes a stricter view and treats the ranges as advertised in
the device tree (i.e, as 64-bit).

The change in behaviour causes failure when allocating bus addresses
to devices connected behind a PCI-to-PCI bridge that require
non-prefetchable memory ranges. The allocation failure was observed
for certain Samsung NVMe drives connected to RockPro64 boards.

Update the host bridge window attributes to treat it as 32-bit address
memory. This fixes the allocation failure observed since commit
9d57e61bf7.

Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Link: https://lore.kernel.org/r/20210607112856.3499682-5-punitagrawal@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-06-11 23:44:00 +02:00
Jan Kiszka f1f55c6b77 arm64: dts: ti: iot2050: Configure r5f cluster on basic variant in split mode
Lockstep mode is not supported here. So turn it off to avoid warnings
during startup.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/3a241e50-80a3-992a-2445-345c629d7895@siemens.com
2021-06-11 13:21:55 -05:00
Marc Zyngier 46c886220a Merge branch kvm-arm64/mmu/reduce-vmemmap-overhead into kvmarm-master/next
Host stage-2 optimisations from Quentin Perret

* kvm-arm64/mmu/reduce-vmemmap-overhead:
  KVM: arm64: Use less bits for hyp_page refcount
  KVM: arm64: Use less bits for hyp_page order
  KVM: arm64: Remove hyp_pool pointer from struct hyp_page
  KVM: arm64: Unify MMIO and mem host stage-2 pools
  KVM: arm64: Remove list_head from hyp_page
  KVM: arm64: Use refcount at hyp to check page availability
  KVM: arm64: Move hyp_pool locking out of refcount helpers
2021-06-11 13:26:36 +01:00
Will Deacon 873c3e8977 arm64: Kill 32-bit applications scheduled on 64-bit-only CPUs
Scheduling a 32-bit application on a 64-bit-only CPU is a bad idea.

Ensure that 32-bit applications always take the slow-path when returning
to userspace on a system with mismatched support at EL0, so that we can
avoid trying to run on a 64-bit-only CPU and force a SIGKILL instead.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210608180313.11502-5-will@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-11 13:25:41 +01:00
Will Deacon 2f6a49bbc0 KVM: arm64: Kill 32-bit vCPUs on systems with mismatched EL0 support
If a vCPU is caught running 32-bit code on a system with mismatched
support at EL0, then we should kill it.

Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210608180313.11502-4-will@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-11 13:25:40 +01:00
Will Deacon 2122a83331 arm64: Allow mismatched 32-bit EL0 support
When confronted with a mixture of CPUs, some of which support 32-bit
applications and others which don't, we quite sensibly treat the system
as 64-bit only for userspace and prevent execve() of 32-bit binaries.

Unfortunately, some crazy folks have decided to build systems like this
with the intention of running 32-bit applications, so relax our
sanitisation logic to continue to advertise 32-bit support to userspace
on these systems and track the real 32-bit capable cores in a cpumask
instead. For now, the default behaviour remains but will be tied to
a command-line option in a later patch.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210608180313.11502-3-will@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2021-06-11 13:25:40 +01:00