Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
A recent switch to a dedicated AP807 compatible string for the Xenon
SD/MMC controller result in the driver not being probed when
using updated device tree with the older kernel revisions.
It may also be problematic for other OSs/firmware that use
Linux device tree sources as a reference. Resolve the problem
with backward compatibility by restoring a previous compatible
string as secondary one.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Move the turris-mox-rwtm firmware node from Turris MOX' device tree into
the generic armada-37xx.dtsi file and use the generic compatible string
'marvell,armada-3700-rwtm-firmware' instead of the current one.
Turris MOX DTS file contains also old compatible string for backward
compatibility.
The Turris MOX rWTM firmware can be used on any Armada 37xx device,
giving them access to the rWTM hardware random number generator, which
is otherwise unavailable.
This change allows Linux to load the turris-mox-rwtm.ko module on these
boards.
Tested on ESPRESSObin v5 with both default Marvell WTMI firmware and
CZ.NIC's firmware. With default WTMI firmware the turris-mox-rwtm fails
to probe, while with CZ.NIC's firmware it registers the HW random number
generator.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
s/Hisilicon/HiSilicon/.
It should use capital S, according to the official website
https://www.hisilicon.com/en.
Signed-off-by: Hao Fang <fanghao11@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Due to a limitation for USB DFU boot mode, SPL load address has to be less
than or equal to 0x70001000. So, load address of SPL and TF-A have been
moved to 0x70000000 and 0x701c0000 respectively, in U-Boot version 2021.10.
Therefore, update TF-A's location in the device tree node.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210616171224.24635-4-a-govindraju@ti.com
The final 128KB in SRAM is reserved by default for DMSC-lite code and
secure proxy communication buffer. The memory region used for DMSC-lite
code can be optionally freed up by secure firmware API[1]. However, the
buffer for secure proxy communication is not configurable. This default
hardware configuration is unique for AM64.
Therefore, indicate the area reserved for DMSC-lite code and secure proxy
communication buffer in the oc_sram device tree node.
[1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210616171224.24635-3-a-govindraju@ti.com
It's not worth duplicating the same node over and over and over and over again,
so let's keep the common bits in the pm8150 DTSI, making only changing the
status and keycode necessary.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613124822.124039-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add support for SONY Xperia 1 II and 5 II smartphones (read one/five mark two).
They are based on the Qualcomm SM8250 chipset and both feature 5G modems. There
also exists a third Edo board, namely the Xperia PRO (PDX204), but it's $2500
and no developers have obtained it so far (to my knowledge).
The devices are affected by a scary UFS behaviour where sending a certain UFS
command (which is worked around on downstream) renders the device unbootable,
by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly
disabled for now.
Downstream workaround:
2e7a9ee1c9
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-4-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Almost any board that boots and has a way to interact with it
(say for the rare cases of just-pstore or let's-rely-on-bootloader-setup)
needs to set some GPIOs, so it makes no sense to include gpio.h separately
each time. Hence move it to SoC DTSI.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add required pins for SDHCI2, so that the interface can work reliably.
This commit adds sleep_state setup to the SoC DTSI, as it is common for
all boards.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add support for SONY Xperia 1 and 5 smartphones, both based on the
Qualcomm SM8150 chipset. There also exist 5G-capable versions of these
devices, but they weren't sold much (if at all) outside Japan.
The devices are affected by a scary UFS behaviour where sending a certain UFS
command (which is worked around on downstream) renders the device unbootable,
by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly
disabled for now.
Downstream workaround:
2e7a9ee1c9
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> (On Bahamut)
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210611203301.101067-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Components that rely on proprietary (not to mention signed!) firmware should
not be enabled by default, as lack of the aforementioned firmware could cause
various issues, from random errors to straight-up failing to boot.
Not enabling modem back on the HDK, as it uses a sa8150.
Also fixed a sorting mistake in both boards' dt while at it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210611203301.101067-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Components that rely on proprietary (not to mention signed!) firmware should
not be enabled by default, as lack of the aforementioned firmware could cause
various issues, from random errors to straight-up failing to boot.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210612192358.62602-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the aforementioned properties in the SoC DTSI so that everybody doesn't
have to copy that into their device DTs, effectively reducing code
duplication.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613114356.82358-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
DPU/MDSS is borderline useless without MDP, so disabling
both of them makes little sense. With this change, enabling
mdss will be enough.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613110635.46537-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Contains changes to consolidate audio card names, adds audio support on
Jetson Xavier NX and enables SMMU on Tegra194.
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Merge tag 'tegra-for-5.14-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.14-rc1
Contains changes to consolidate audio card names, adds audio support on
Jetson Xavier NX and enables SMMU on Tegra194.
* tag 'tegra-for-5.14-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Enable SMMU support on Tegra194
arm64: tegra: Hook up memory controller to SMMU on Tegra186
arm64: tegra: Use correct compatible string for Tegra186 SMMU
arm64: tegra: Audio graph sound card for Jetson Xavier NX
arm64: tegra: Consolidate audio card names
arm64: tegra: Add PMU node for Tegra194
Link: https://lore.kernel.org/r/20210611164437.3568059-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add DT support for Toshiba Visconti5 PWM driver
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Merge tag 'visconti-arm-dt-for-v5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti into arm/dt
Visconti device tree updates for 5.14
- Add DT support for Toshiba Visconti5 PWM driver
* tag 'visconti-arm-dt-for-v5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti:
arm64: dts: visconti: Add PWM support for TMPV7708 SoC
Link: https://lore.kernel.org/r/20210614234654.2u3xetnn5rwhymwz@toshiba.co.jp
Signed-off-by: Olof Johansson <olof@lixom.net>
MSM8916 gains new support for Huawei Ascend G7, with NFC, sensors and
touchscreen. The Samsung Galaxy A3/A5 gains battery support, touch keys,
NFC.
MSM8996 received more cleanup and refactoring, preparing for upcoming
new devices. Note worthy is the long pending enablement of CPUfreq.
SC7180 continues to stabilize, with a range of small fixes for various
bits and pieces, and new revisions for the CoachZ and pompom devices.
SC7280 continues to grow, with more clock controllers, thermal sensors,
thermal zones, CPUfreq and interconnect providers.
Xiaomi Poco F1 gaines audio support and the OnePlus 6/6T gaines IPA
support.
SM8350 gains some cleanups and the IPA device is enabled.
Initial support for the Microsoft Surface Duo, based on SM8150, is
added.
IPQ8074 gained support for the HK10 board.
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Merge tag 'qcom-arm64-for-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 DT updates for v5.14
MSM8916 gains new support for Huawei Ascend G7, with NFC, sensors and
touchscreen. The Samsung Galaxy A3/A5 gains battery support, touch keys,
NFC.
MSM8996 received more cleanup and refactoring, preparing for upcoming
new devices. Note worthy is the long pending enablement of CPUfreq.
SC7180 continues to stabilize, with a range of small fixes for various
bits and pieces, and new revisions for the CoachZ and pompom devices.
SC7280 continues to grow, with more clock controllers, thermal sensors,
thermal zones, CPUfreq and interconnect providers.
Xiaomi Poco F1 gaines audio support and the OnePlus 6/6T gaines IPA
support.
SM8350 gains some cleanups and the IPA device is enabled.
Initial support for the Microsoft Surface Duo, based on SM8150, is
added.
IPQ8074 gained support for the HK10 board.
* tag 'qcom-arm64-for-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (85 commits)
arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card
arm64: dts: sc7280: Add interconnect provider DT nodes
arm64: dts: qcom: msm8916-huawei-g7: Add NFC
arm64: dts: qcom: msm8916-huawei-g7: Add display regulator
arm64: dts: qcom: msm8916-huawei-g7: Add sensors
arm64: dts: qcom: msm8916-huawei-g7: Add touchscreen
arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7
arm64: dts: qcom: sc7180-trogdor: Update flash freq to match reality
arm64: dts: qcom: sc7180: Add wakeup delay for adau codec
arm64: dts: qcom: sdm845: Remove cros-pd-update on Cheza
arm64: dts: qcom: sc7180: Remove cros-pd-update on Trogdor
arm64: dts: qcom: sc7180: Disable PON on Trogdor
arm64: dts: qcom: sc7180: Modify SPI_CLK voltage level for trogdor
arm64: dts: qcom: add initial device-tree for Microsoft Surface Duo
arm64: dts: qcom: sdm845-mtp: enable IPA
arm64: dts: qcom: sc7180: SD-card GPIO pin set bias-pull up
arm64: dts: qcom: sc7180: Move sdc pinconf to board specific DT files
arm64: dts: qcom: msm8916-samsung-a2015: Add NFC
arm64: dts: qcom: msm8916-samsung-a2015: Add rt5033 battery
arm64: dts: qcom: msm8916-samsung-a5u: Add touch key regulator
...
Link: https://lore.kernel.org/r/20210614223712.393096-1-bjorn.andersson@linaro.org
Signed-off-by: Olof Johansson <olof@lixom.net>
- New board support: i.MX8MM Gateworks GW7901 board.
- Add SPBA bus description for i.MX8MN and i.MX8MM.
- A series of update on imx8mq-nitrogen board to add USB OTG/Host and
LT8912 MIPI-DSI to HDMI support.
- Correct enet clock description for i.MX8 Connection Subsystem.
- A couple of patches from Heiko Schocher to add FlexSPI device for
i.MX8MP SoC and enable SPI NOR Flash support on imx8mp-phycore-som.
- Remove the reference to audio IPG clock on i.MX8MP.
- Enable EQOS Ethernet and PMIC device support for imx8mp-evk.
- Disable USB over-current on imx8mm-evk and imx8mn-evk.
- Add dma-ranges description for i.MX8MM and i.MX8MN SoC.
- Add PCIe clock description for i.MX8MQ SoC.
- Enable PCIe support on freeway board.
- Enable OPTEE support on ls1028a-rdb board.
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Merge tag 'imx-dt64-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree chagnes for 5.14:
- New board support: i.MX8MM Gateworks GW7901 board.
- Add SPBA bus description for i.MX8MN and i.MX8MM.
- A series of update on imx8mq-nitrogen board to add USB OTG/Host and
LT8912 MIPI-DSI to HDMI support.
- Correct enet clock description for i.MX8 Connection Subsystem.
- A couple of patches from Heiko Schocher to add FlexSPI device for
i.MX8MP SoC and enable SPI NOR Flash support on imx8mp-phycore-som.
- Remove the reference to audio IPG clock on i.MX8MP.
- Enable EQOS Ethernet and PMIC device support for imx8mp-evk.
- Disable USB over-current on imx8mm-evk and imx8mn-evk.
- Add dma-ranges description for i.MX8MM and i.MX8MN SoC.
- Add PCIe clock description for i.MX8MQ SoC.
- Enable PCIe support on freeway board.
- Enable OPTEE support on ls1028a-rdb board.
* tag 'imx-dt64-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (24 commits)
arm64: dts: imx8mn-evk: disable over current for usb
arm64: dts: imx8mm-evk: disable over current for usb1
arm64: dts: freescale: Separate each group of data in the property 'reg'
arm64: dts: imx8: conn: fix enet clock setting
arm64: dts: imx8mq: assign PCIe clocks
arm64: dts: imx8mn: specify dma-ranges
arm64: dts: imx8mm: specify dma-ranges
arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
arm64: dts: imx8mn-beacon-som: Assign PMIC clock
arm64: dts: ls208xa: remove bus-num from dspi node
arm64: dts: ls1012a: enable PCIe on freeway board
arm64: dts: imx8mp-evk: enable EQOS ethernet
arm64: dts: imx8mp: Remove the reference to audio ipg clock on imx8mp
arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy
arm64: dts: imx8mm: Add spba1 and spba2 buses
arm64: dts: imx8mn: Add spba1 bus
arm64: dts: imx8mq-nitrogen: add lt8912 MIPI-DSI to HDMI
arm64: dts: imx8mq-nitrogen: add USB HOST support
arm64: dts: imx8mq-nitrogen: add USB OTG support
arm64: dts: imx8mp-phycore-som: enable spi nor
...
Link: https://lore.kernel.org/r/20210613082544.16067-5-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
The calculations for the DLL register values are based on the clock rate
of the reference clock. Provide the reference clock in the definition of
the two SDHCI controllers to not rely on the default values.
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Link: https://lore.kernel.org/r/1623309107-27833-1-git-send-email-sbhanu@codeaurora.org
[bjorn: Rewrote commit message]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
8250_omap compatible UART IPs on all SoCs have registers aligned at 4
byte address boundary and constant byte addressability. Thus there is no
need for reg-io-width or reg-shift DT properties. These properties are
not used by 8250_omap driver nor documented as part of binding document.
Therefore drop them.
This is in preparation to move omap-serial.txt to YAML format.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com
ti,pindir-d0-out-d1-in property is expected to be of type boolean.
Therefore, fix the property accordingly.
Fixes: 4fb6c04683 ("arm64: dts: ti: k3-am642-evm: Add support for SPI EEPROM")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210608051414.14873-3-a-govindraju@ti.com
The current device tree CPSW3g node adds non-zero "mac-address" property to
the ports, which prevents random MAC address assignment to network devices
if bootloader failed to update DT. This may cause more then one host to
have the same MAC in the network.
mac-address = [00 00 de ad be ef];
mac-address = [00 01 de ad be ef];
In addition, there is one MAC address available in eFuse registers which
can be used for default port 1.
Hence, fix ports MAC properties by:
- resetting "mac-address" property to 0
- adding ti,syscon-efuse = <&main_conf 0x200> to Port 1
Fixes: 3753b12877 ("arm64: dts: ti: k3-am64-main: Add CPSW DT node")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210608184940.25934-1-grygorii.strashko@ti.com
Drop the hub_5v regulator which controls the HUB Reset line with GPIOH_4 which
is already controlled by a GPIO HOG.
Until we can properly describe how to control USB HUBs reset lines, keeping
the GPIO HOG is an acceptable solution we use on multiple boards.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-8-narmstrong@baylibre.com
Add a node for the XT25F128B SPI-NOR flash to make it accessible
from Linux.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-7-narmstrong@baylibre.com
As described in the HC4 schematics, GPIOH_8 controls the USB 5V and 12V
regulators used to power the SATA drives.
And is set as Open Drain since this GPIO doesn't support Push-Pull.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-6-narmstrong@baylibre.com
As described in the HC4 schematics, only the USB port B is used,
port A is left unconnected. Thus disable PHY0 and remove it from PHYs list.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-5-narmstrong@baylibre.com
As described in the Odroid-C4 & Odroid-HC4 schematics, the 5V regulator is controlled
by GPIOH_8 and in Open Drain since this GPIO doesn't support Push-Pull.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-4-narmstrong@baylibre.com
According to Odroid-C4 & HC4 Schematics, the TF_3V3N_1V8_EN can be in Hi-Z for 3v3,
and since it's the default GPIOAO_6 mode at reset, let switch this GPIO as Open-Source
to drive for 1, and input for 0.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-3-narmstrong@baylibre.com
As described in the schematics of Odroid-C4 and Odroid-HC4, the TF_IO regulator
is enabled by the GPIOE_2 GPIO and gets it's supply from VCC_5V.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210607065435.577334-2-narmstrong@baylibre.com
There are 3 additional patches pending that handle the backward
compatiblity inside the PCI subsystem, but the address ranges
should be fixed anyway.
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Merge tag 'v5.13-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Fix PCIe address ranges that are affected by recent PCI changes.
There are 3 additional patches pending that handle the backward
compatiblity inside the PCI subsystem, but the address ranges
should be fixed anyway.
* tag 'v5.13-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory
Link: https://lore.kernel.org/r/3405741.0S5aU1g85B@diego
Signed-off-by: Olof Johansson <olof@lixom.net>
mainly:
- I2S Support for the V3
- Audio Codec Support for the V3s
- DMA support for the V3s
- PWM support for the V3s
- Support for Bluetooth Audio on the pinephone
- Add A10-like timers to the A64 and R40
- New boards: Forlinx OKA40i-C, Forlinx OKA40i-C, NanoPi R1S H5
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Merge tag 'sunxi-dt-for-5.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual bunch of patches to improve the Allwinner SoCs support,
mainly:
- I2S Support for the V3
- Audio Codec Support for the V3s
- DMA support for the V3s
- PWM support for the V3s
- Support for Bluetooth Audio on the pinephone
- Add A10-like timers to the A64 and R40
- New boards: Forlinx OKA40i-C, Forlinx OKA40i-C, NanoPi R1S H5
* tag 'sunxi-dt-for-5.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (29 commits)
ARM: dts: sun8i: v3s: enable emac for zero Dock
arm64: dts: allwinner: pinephone: Set audio card name
ARM: dts: sun8i: r40: Add timer node
ARM: dts: sun8i: V3: add I2S interface to V3 dts
dt-bindings: sound: sun4i-i2s: add Allwinner V3 I2S compatible
ARM: dts: sun8i: V3: add codec analog frontend to V3 dts
ASoC: dt-bindings: sun8i-a23-codec-analog: add compatible for Allwinner V3
ARM: dts: sun8i: v3s: add analog codec and frontend to v3s dts
ARM: dts: sun8i: v3s: add DMA properties to peripherals supporting DMA
ARM: dts: sun8i: v3s: add DMA controller to v3s dts
ARM: dts: sun8i: v3s: add pwm controller to v3s dts
dt-bindings: pwm: allwinner: add v3s pwm compatible
arm64: dts: allwinner: h5: Add NanoPi R1S H5 support
dt-bindings: arm: Add NanoPi R1S H5
arm64: dts: allwinner: pinephone: Add support for Bluetooth audio
arm64: dts: allwinner: a64: Allow multiple DAI links
arm64: dts: allwinner: a64: Add pinmux nodes for AIF2/AIF3
arm64: dts: allwinner: a64: Allow using multiple codec DAIs
ARM: dts: sun8i-a33: Allow using multiple codec DAIs
ASoC: dt-bindings: sun8i-codec: Increase #sound-dai-cells
...
Link: https://lore.kernel.org/r/96cc77ec-139d-4685-8a66-a60964cf39fd.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
Just a single fix to use standard and generic nodes names for SCMI
power domain controller and clock controller devicetree nodes.
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Merge tag 'juno-fix-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
ARMv8 Juno fix for v5.14
Just a single fix to use standard and generic nodes names for SCMI
power domain controller and clock controller devicetree nodes.
* tag 'juno-fix-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Update SCPI nodes as per the YAML schema
Link: https://lore.kernel.org/r/20210611075805.2813712-1-sudeep.holla@arm.com
Signed-off-by: Olof Johansson <olof@lixom.net>
please pull the following:
- Zhen fixes the Broadcom stingray serial node unit names to fix a DT
binding warning
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Merge tag 'arm-soc/for-5.14/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM64-based SoCs changes for 5.14,
please pull the following:
- Zhen fixes the Broadcom stingray serial node unit names to fix a DT
binding warning
* tag 'arm-soc/for-5.14/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: normalize the node name of the UART devices
Link: https://lore.kernel.org/r/20210610194836.309869-2-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
for 5.14, please pull the following:
- Rafal updates the BCM5301x, HR2, BCM63xx, BCM5301x, NSP and Cygnus DTS
files to resolve a number of DT binding check warnings pertaining to
NAND, pinmux, clocks, SPI
- Stefan provides a fix for an increase in the DWC2 controller's RX FIFO
causing regressions on the Raspberry Pi 4B
- Mateusz adds a BCM2711 specific VEC compatible string to allow keying
off that variant properly
- Stefan adds support for the Raspberry Pi 400 by doing some DTS/DTSI
re-organization work and finally adding the DTS file proper
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Merge tag 'arm-soc/for-5.14/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.14, please pull the following:
- Rafal updates the BCM5301x, HR2, BCM63xx, BCM5301x, NSP and Cygnus DTS
files to resolve a number of DT binding check warnings pertaining to
NAND, pinmux, clocks, SPI
- Stefan provides a fix for an increase in the DWC2 controller's RX FIFO
causing regressions on the Raspberry Pi 4B
- Mateusz adds a BCM2711 specific VEC compatible string to allow keying
off that variant properly
- Stefan adds support for the Raspberry Pi 400 by doing some DTS/DTSI
re-organization work and finally adding the DTS file proper
* tag 'arm-soc/for-5.14/devicetree' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Add reference to RPi 400
ARM: dts: Add Raspberry Pi 400 support
ARM: dts: bcm283x: Fix up GPIO LED node names
dt-bindings: arm: bcm2835: Add Raspberry Pi 400 to DT schema
ARM: dts: Move BCM2711 RPi specific into separate dtsi
ARM: dts: bcm283x: Fix up MMC node names
ARM: boot: dts: bcm2711: Add BCM2711 VEC compatible
Revert "ARM: dts: bcm283x: increase dwc2's RX FIFO size"
ARM: dts: BCM5301X: Fixup SPI binding
dt-bindings: clock: brcm, iproc-clocks: convert to the json-schema
ARM: dts: BCM5301X: Fix pinmux subnodes names
ARM: dts: Hurricane 2: Fix NAND nodes names
ARM: dts: BCM63xx: Fix NAND nodes names
ARM: NSP: dts: fix NAND nodes names
ARM: Cygnus: dts: fix NAND nodes names
ARM: brcmstb: dts: fix NAND nodes names
ARM: dts: BCM5301X: Fix NAND nodes names
Link: https://lore.kernel.org/r/20210610194836.309869-1-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
imx8mn evk board usb port does not support over current detection,
so disable it.
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx8mm evk board usb1 port does not support over current detection,
so disable it.
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Do not write the 'reg' of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar to the following
will be reported by reg.yaml.
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml:
soc: pcie@3400000:reg:0: \
[0, 54525952, 0, 1048576, 64, 0, 0, 8192] is too long
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
enet_clk_ref actually is sourced from internal gpr clocks
which needs a default rate. Also update enet lpcg clock
output names to be more straightforward.
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This fixes multiple issues with the current non-existent PCIe clock setup:
The controller can run at up to 250MHz, so use a parent that provides this
clock.
The PHY needs an exact 100MHz reference clock to function if the PCIe
refclock is not fed in via the refclock pads. While this mode is not
supported (yet) in the driver it doesn't hurt to make sure we are
providing a clock with the right rate.
The AUX clock is specified to have a maximum clock rate of 10MHz. So
the current setup, which drives it straight from the 25MHz oscillator is
actually overclocking the AUX input.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
DMA addressing capabilities on i.MX8MN are limited by the interconnect,
same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
the kernel know about this.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
DMA addressing capabilities on i.MX8MM are limited by the interconnect,
same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
the kernel know about this.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Currently all PCIE windows point to bus address 0x0, which does not match
the values obtained from hardware during EA.
Replace those values with CPU addresses, since in reality we
have a 1:1 mapping between the two.
Signed-off-by: Kornel Duleba <mindal@semihalf.com>
Acked-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The PMIC throws an errors because the clock isn't assigned to it.
Fix this by assigning the clocks info.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On LS2088A-RDB board, if the spi-fsl-dspi driver is built as module
then its probe fails with the following warning:
[ 10.471363] couldn't get idr
[ 10.471381] WARNING: CPU: 4 PID: 488 at drivers/spi/spi.c:2689 spi_register_controller+0x73c/0x8d0
...
[ 10.471651] fsl-dspi 2100000.spi: Problem registering DSPI ctlr
[ 10.471708] fsl-dspi: probe of 2100000.spi failed with error -16
Reason for the failure is that bus-num property is set for dspi node.
However, bus-num property is not set for the qspi node. If probe for
spi-fsl-qspi happens first then id 0 is dynamically allocated to it.
Call to spi_register_controller() from spi-fsl-dspi driver then fails.
Since commit 29d2daf2c3 ("spi: spi-fsl-dspi: Make bus-num property
optional") bus-num property is optional. Remove bus-num property from
dspi node to fix the issue.
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
ls1012a-freeway board contains a M.2 2230 slot. Update the status of
pcei1 node to okay so that the pcie controller can be probed.
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX8MP, there is no audio ipg clock, so remove the wrong reference
to this clock in dts file.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX8MM reference manual shows there are two spba busses.
SPBA1 handles much of the serial interfaces, and SPBA2 covers much
of the audio.
Add both of them.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX8MN has an SPBA bus which covers much of the audio, but
there is a second SPBA bus which covers many of the serial interfaces
like SPI and UARTs currently missing from the device tree. The reference
manual calls the bus handling the audio peripherals SPBA2, and the bus
handling the serial peripherals is called SPBA1.
Rename the existing spba bus to spba2 and add spba1.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support of the lt8912b in the DTB.
This adds the support of the DB_DSIHD daugther board from
Boundary Devices.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the description for the USB host port.
This port is linked to a resettable USB HUB so handle
this reset signal with a GPIO hog.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the description for the USB OTG port.
The OTG port uses a dedicated regulator for vbus.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The PCIe host bridge on RK3399 advertises a single 64-bit memory
address range even though it lies entirely below 4GB.
Previously the OF PCI range parser treated 64-bit ranges more
leniently (i.e., as 32-bit), but since commit 9d57e61bf7 ("of/pci:
Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses")
the code takes a stricter view and treats the ranges as advertised in
the device tree (i.e, as 64-bit).
The change in behaviour causes failure when allocating bus addresses
to devices connected behind a PCI-to-PCI bridge that require
non-prefetchable memory ranges. The allocation failure was observed
for certain Samsung NVMe drives connected to RockPro64 boards.
Update the host bridge window attributes to treat it as 32-bit address
memory. This fixes the allocation failure observed since commit
9d57e61bf7.
Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Link: https://lore.kernel.org/r/20210607112856.3499682-5-punitagrawal@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the device tree node for the dual-SMMU found on Tegra194 and hook up
peripherals such as host1x, BPMP, HDA, SDMMC, EQOS and VIC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
On Tegra186 and later, the memory controller needs to be programmed in
coordination with any of the ARM SMMU instances to configure the stream
ID used for each memory client.
To support this, add a phandle reference to the memory controller to the
SMMU device tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SMMU found on Tegra186 requires interoperation with the memory
controller in order to program stream ID overrides. The generic ARM SMMU
500 compatible is therefore inaccurate. Replace it with a more correct,
SoC-specific compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the DT nodes for the network-on-chip interconnect buses found
on sc7280-based platforms.
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Link: https://lore.kernel.org/r/1619517059-12109-4-git-send-email-okukatla@codeaurora.org
[bjorn: Sorted nodes and dropped include]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The Huawei Ascend G7 supports NFC using the NXP PN547, which is
supported by the nxp-nci-i2c driver in mainline. It seems to detect
NFC tags using "nfctool" just fine, although it seems like there
are not really any useful applications making use of the Linux NFC
subsystem. :(
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The display on the Huawei Ascend G7 is supplied by a TI TPS65132
regulator. The panel needs a driver in mainline first, but the
TPS65132 is already supported in mainline by the tps65132 driver.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The Huawei Ascend G7 has a Synaptics "C199HW-006" touchscreen,
supplied by pm8916_l17 and pm8916_l16. Add it to the device tree
and reduce the maximum allowed voltage for pm8916_l16 to 1.8V since
we really should not use more for an I/O supply.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The Huawei Ascend G7 is a smartphone from Huawei based on MSM8916.
It's fairly similar to the other MSM8916 devices, the only notable
exception are the "cd-gpios" for detecting if a SD card was inserted:
It looks like Huawei forgot to re-route this to gpio38, so the correct
GPIO seems to be gpio56 on this device.
Note: The original firmware from Huawei can only boot 32-bit kernels.
To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware
with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei
forgot to set up (firmware) secure boot for some reason.
Also note that Huawei no longer provides bootloader unlock codes.
This can be bypassed by patching the bootloader from a custom HYP firmware,
making it think the bootloader is unlocked. I use a modified version of
qhypstub [1], that patches a single instruction in the Huawei bootloader.
The device tree contains initial support for the Huawei Ascend G7 with:
- UART (untested, probably available via some test points)
- eMMC/SD card
- Buttons
- Notification LED (combination of 3 GPIO LEDs)
- Vibrator
- WiFi/Bluetooth (WCNSS)
- USB
[1]: https://github.com/msm8916-mainline/qhypstub
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This spi flash part is actually being clocked at 37.5MHz, not 25MHz,
because of the way the clk driver is rounding up the rate that is
requested to the nearest supported frequency. Let's update the frequency
here, and remove the TODO because this is the fastest frequency we're
going to be able to use here.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210519054030.3217704-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This compatible string isn't present upstream. Let's drop the node as it
isn't used.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210601185959.3101132-2-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This compatible string isn't present upstream. Let's drop the node as it
isn't used.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210601185959.3101132-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
We don't use the PON module on Trogdor devices. Instead the reboot
reason is sort of stored in the 'eventlog' and the bootloader figures
out if the boot is abnormal and records that there. Disable the PON node
and then drop the power key disabling because that's a child node that
will no longer be enabled if the PON node is disabled.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210601184417.3020834-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
On coachz it could be observed that SPI_CLK voltage level was only
1.4V during active transfers because the drive strength was too
weak. The line hadn't finished slewing up by the time we started
driving it down again. Using a drive strength of 8 lets us achieve the
correct voltage level of 1.8V.
Though the worst problems were observed on coachz hardware, let's do
this across the board for trogdor devices. Scoping other boards shows
that this makes the clk line look nicer on them too and doesn't
introduce any problems.
Only the clk line is adjusted, not any data lines. Because SPI isn't a
DDR protocol we only sample the data lines on either rising or falling
edges, not both. That means the clk line needs to toggle twice as fast
as data lines so having the higher drive strength is more important
there.
Signed-off-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com>
[dianders: Adjust author real name; adjust commit message]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210510075253.1.Ib4c296d6ff9819f26bcaf91e8a08729cc203fed0@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add initial DTSI for RZ/G2{L,LC} SoC's.
File structure:
r9a07g044.dtsi => RZ/G2L family SoC common parts
r9a07g044l1.dtsi => RZ/G2L R9A07G044L1 SoC specific parts
r9a07g044l2.dtsi => RZ/G2L R9A07G044L2 SoC specific parts
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Although the schematics of Pine A64-LTS and SoPine Baseboard shows both
the RX and TX internal delay are enabled, they're using the same broken
RTL8211E chip batch with Pine A64+, so they should use TXID instead, not
ID.
In addition, by checking the real components soldered on both a SoPine
Baseboard and a Pine A64-LTS, RX delay is not enabled (GR69 soldered and
GR70 NC) despite the schematics says it's enabled. It's a common
situation for Pine64 boards that the NC information on schematics is not
the same with the board.
So the RGMII delay mode should be TXID on these boards.
Fixes: c2b111e59a ("arm64: dts: allwinner: A64 Sopine: phy-mode rgmii-id")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210609083843.463750-1-icenowy@aosc.io
Add a basic GPU node for mt8183, as well as OPP table.
Note that with the current panfrost driver, devfreq is not
actually functional, as the we do not have platform-specific
support for >1 supplies. Also, we are missing code to handle
frequency change, as the GPU frequency needs to be switched
away to a stable 26Mhz clock during the transition.
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Link: https://lore.kernel.org/r/20210521200038.v14.1.I9f45f5c1f975422d58b5904d11546349e9ccdc94@changeid
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add tboard thermal zones.
The tboard thermal sensors are a kind of NTC sensors which are located
on PCB board to correlate the temperature of the case (Tskin).
pull-up voltage: 1800 mv
pull-up resistor: 75K
Vsense = pull-up voltage * Rntc / ( pull-up resistor + Rntc )
AuxIn = Vsense * 4096 / 1500
Signed-off-by: Michael Kao <michael.kao@mediatek.com>
Signed-off-by: Ben Tseng <ben.tseng@mediatek.com>
Tested-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210604093755.13288-1-ben.tseng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add a 'cbas' device node for supporting tablet mode switch in
kukui devices.
Kukui platforms with detacheable base have an additional input
device under cros-ec, which reports SW_TABLET_MODE regarding
its base state (e.g. base flipped or detached).
Signed-off-by: Ikjoon Jang <ikjn@chromium.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210609032554.2443675-1-ikjn@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This adds a reference to the dts of the Raspberry Pi 400,
so we don't need to maintain the content in arm64.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Link: https://lore.kernel.org/r/1622981777-5023-8-git-send-email-stefan.wahren@i2se.com
Signed-off-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
AM642-SK has no PCIe slot. Disable it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603142251.14563-6-kishon@ti.com
AM642 EVM has a x4 lane PCIe connector. Enable PCIe in RC mode here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603142251.14563-4-kishon@ti.com
AM64 has one PCIe instance which can be configured in either
host mode (RC) or device mode (EP). Add PCIe DT node for host
mode and device mode here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603142251.14563-3-kishon@ti.com
AM64 has one SERDES 10G instance. Add SERDES DT node for it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603142251.14563-2-kishon@ti.com
Commit 66db854b1f ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy' as discussed in [1].
Re-name subnodes of serdes in J721E to 'phy'.
[1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus
Fixes: 66db854b1f ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances")
Fixes: 02c35dca2b ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603143427.28735-5-kishon@ti.com
Konstantin Porotchkin