Call uart_write_wakeup() after writing the hardware FIFO and updateing the FIFO
pointers.
This fixes high latency and jitter on PPP over Serial links.
Reported-by: Jun Shih <Jun.Shih@pason.com>
Tested-by: Jun Shih <Jun.Shih@pason.com>
Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Don't activate the TX Space available IRQ on startup, or a simple
$ cat /dev/ttyHSU0
will cause an endless amount of IRQs, as there is always space in
the TX FIFO available if no data is going to be sent.
Also correct comments for IRQ names (RX and TX swapped).
Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add driver for MEN's 16z135 High Speed UART.
The 16z135 is a memory mapped UART Core on an MCB FPGA and has 1024 byte
deep FIFO buffers for the RX and TX path. It also has configurable FIFO
fill level IRQs and data copied to and from the hardware has to be
acknowledged.
Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de>
Reviewed-by: Alan Cox <gnomes@lxorguk.ukuu.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Johannes Thumshirn