Add the "intc-ex" clock to the R8A7796 CPG MSSR driver.
According to information from the hardware team the INTC-EX
parent clock is CP. The next data sheet version will include
this information.
[takeshi.kihara.df: Ported from commit f099aa0757 ("clk: shmobile:
r8a7795: Add INTC-EX clock") to drivers/clk/renesas/r8a7796-cpg-mssr.c]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's
Manual Rev.1.00, MD19=0 is a prohibited setting.
Hence stop looking at MD19, and remove all PLL configurations for
MD19=0.
Fixes: 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
RZ/G1E does not have the SCU-SRC[0789] modules and module clocks.
Fixes: 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
R-Car V2H and E2 do not have the PLL0CR register, but use a fixed
multiplier (depending on mode pins) and divider.
This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on
R-Car V2H and E2 from 1.5 GHz to 1 GHz.
Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G
Clock Pulse Generator support core.
Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Fixes: 0dce5454d5 ("ARM: shmobile: Initial r8a7794 SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28.
Add support for that, but retain the old behavior for R-Car H3 ES1.x and
M3-W ES1.0 using a quirk.
Inspired by a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The same SoC may have different clocks and/or module clock parents,
depending on SoC revision. One option is to use different sets of clock
tables for each SoC revision. However, if the differences are small, it
is much more space-efficient to have a single set of clock tables, and
fix those up at runtime instead.
Hence provide three helpers:
- Two helpers to NULLify core and module clocks that do not exist on
some revisions (NULLified clocks are skipped during the registration
phase),
- One helper to reparent module clocks that have different clock
parents.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and
PLL4 clock frequencies are off by a factor of two.
Inspired by a patch by Dien Pham in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Dien Pham <dien.pham.ry@renesas.com>
Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to make some
core clock configuration decisions.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which
maps to S3D1 on R-Car H3 ES1.x.
All module clocks must be sorted by clock ID.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Add the IMR[0-3] clocks to the R8A7795 CPG/MSSR driver.
Based on the original (and large) patch by Konstantin Kozhevnikov
<Konstantin.Kozhevnikov@cogentembedded.com>.
Signed-off-by: Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.
Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
- Use CLK_IS_CRITICAL to handle critical clocks,
- Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
- Add IIC-DVFS clocks for R-Car H3 and M3-W,
- Minor cleanups.
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Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Use CLK_IS_CRITICAL to handle critical clocks,
- Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
- Add IIC-DVFS clocks for R-Car H3 and M3-W,
- Minor cleanups.
* tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add IIC-DVFS clock
clk: renesas: r8a7795: Add IIC-DVFS clock
clk: renesas: cpg-mssr: Add support for reset control
clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock
clk: renesas: cpg-mssr: Document suitability for RZ/G1
dt-bindings: clock: renesas: cpg-mssr: Document reset control support
clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff
clk: renesas: mstp: Make INTC-SYS a critical clock
clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
Add optional support for the Reset Control feature of the Renesas Clock
Pulse Generator / Module Standby and Software Reset module on R-Car
Gen2, R-Car Gen3, and RZ/G1 SoCs.
This allows to reset SoC devices using the Reset Controller API.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
The spinlock is used to protect Read-Modify-Write register accesses,
which won't be limited to SMSTPCR register accesses.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The Renesas CPG/MSSR driver is already in active use for RZ/G1 since
commits c0b2d75d2a ("clk: renesas: cpg-mssr: Add R8A7743 support")
and 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
As the function header of cpg_mstp_clock_register() is split in an
unusual way, "git diff" gets confused when changes to the body of
the function are made, and attributes them to the wrong function.
Reformat the function header to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
INTC-SYS is the module clock for the GIC. Accessing the GIC while it is
disabled causes:
Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
Currently, the GIC-400 driver cannot enable its module clock for several
reasons:
- It does not use a platform device, so Runtime PM is not an option,
- gic_of_init() runs before any clocks are registered, so it cannot
enable the clock explicitly,
- gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE()
doesn't support deferred probing.
Hence we have to keep on relying on the boot loader for enabling the
module clock.
To prevent the module clock from being disabled when the CCF core thinks
it is unused, and thus causing a system lock-up, add a check to the MSTP
clock driver and enable CLK_IS_CRITICAL. This will make sure the module
clock is never disabled.
This is a hard dependency for describing the INTC-SYS clock in DT on
R-Mobile APE6 and R-Car Gen2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
When the Renesas CPG/MSSR driver was introduced, it was anticipated that
critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag
soon. However, CLK_ENABLE_HAND_OFF never made it upstream.
Instead, commit 32b9b10961 ("clk: Allow clocks to be marked as
CRITICAL") introduced CLK_IS_CRITICAL, a flag with slightly differing
semantics. Still, it can be used to prevent e.g. the GIC module clock
from being turned off, until the GIC-400 driver has full support for
Runtime PM.
Hence migrate the Renesas CPG/MSSR driver from CLK_ENABLE_HAND_OFF to
CLK_IS_CRITICAL.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.
Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module
Standby and Software Reset support code, using the CPG/MSSR driver
core.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
All R-Car Gen3 clock drivers now obtain the values of the mode pins from
the R-Car RST driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Fall back to our own private copy of rcar_gen2_read_mode_pins() for
backward-compatibility with old DTs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RESET/WDT module.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RESET/WDT module.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
The intention was to enable the checks if debugging is enabled, not
disabled.
Fixes: f793d1e517 ("clk: shmobile: Add new CPG/MSSR driver core")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The R-Car Gen3 CPG/MSSR driver uses a mix of clk_readl()/clk_writel()
and readl()/writel() to access the clock registers. Settle on the
generic readl()/writel().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel()
and readl()/writel() to access the clock registers. Settle on the
generic readl()/writel().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Check the MD_CLK pin to determine the current clock mode in order to set
the pll clock parent correctly.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add all clocks needed to use the SDHI interfaces on the Renesas R-Car M3-W
(r8a7796) SoC.
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Merge tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull renesas r8a7796 SDHI clock support from Geert Uytterhoeven:
Add all clocks needed to use the SDHI interfaces on the Renesas R-Car M3-W
(r8a7796) SoC.
* tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add SDIF clocks
clk: renesas: r8a7796: Add GPIO clocks
This patch adds SDIF clocks for R8A7796 SoC.
Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add all clocks related to the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.
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Merge tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Merge r8a7796 watchdog clk support from Geert Uytterhoeven:
Add all clocks related to the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.
* tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add watchdog module clock
clk: renesas: r8a7796: Add watchdog core clocks
According to the datasheet, SDn clocks are from the SDSRC clock. And
the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal
core clock. Otherwise, since the sdhi driver will calculate clock for
a sd card using the wrong parent clock rate, and then performance will
be not good.
Fixes: 90c073e539 ("clk: shmobile: r8a7795: Add SD divider support")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.
Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Extract the code to support parts common to all members of the R-Car
Gen3 SoC family into a separate file, to ease sharing among SoC-specific
drivers.
Note that while the cpg_pll_configs[] arrays and the selection of the
config based on the MODE bits are identical on R-Car H3 and R-Car M3-W,
they are not common, and may be different on other R-Car Gen3 SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
As a pure Clock Domain does not have the concept of powering the domain
itself, the CPG/MSTP driver does not provide power_off() and power_on()
callbacks.
However, the genpd core may still perform a dummy power down, causing
/sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's
status being "off-0".
Use the always-on governor to make sure the domain is never powered
down, and always shows up as "on" in pm_genpd_summary.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
All local setup of the generic_pm_domain structure should have been
completed before calling pm_genpd_init().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
As a pure Clock Domain does not have the concept of powering the domain
itself, the CPG/MSTP driver does not provide power_off() and power_on()
callbacks.
However, the genpd core may still perform a dummy power down, causing
/sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's
status being "off-0".
Use the always-on governor to make sure the domain is never powered
down, and always shows up as "on" in pm_genpd_summary.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
All local setup of the generic_pm_domain structure should have been
completed before calling pm_genpd_init().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
The R-Car SYSC PM Domain driver has to power manage devices in power
areas using clocks. To reuse code and to share knowledge of clocks
suitable for power management, this is ideally done through the existing
cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks.
Hence these callbacks can no longer rely on their "domain" parameter
pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to
the clock domain in a static variable. cpg_mssr_attach_dev() has to
support probe deferral, as the R-Car SYSC PM Domain may be initialized,
and devices may be added to it, before the CPG/MSSR Clock Domain is
initialized.
Dummy callbacks are provided for the case where CPG/MSTP support is not
included, so the rcar-sysc driver won't have to care about this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Currently the decision whether to build the renesas-cpg-mssr and
clk-mstp drivers is handled by Makefile logic. However, the rcar-sysc
driver will need to know whether CPG/MSSR and/or CPG/MSTP support are
available or not.
To avoid having to duplicate this logic, move it to Kconfig. Provide
non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig
symbols, which can be used by both Makefiles and C code.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Make it clear that the "domain" parameter of the cpg_mstp_attach_dev()
and cpg_mstp_detach_dev() functions is not used.
The cpg_mstp_attach_dev() and cpg_mstp_detach_dev() callbacks are not
only used by the CPG/MSTP Clock Domain driver, but also by the R-Mobile
SYSC PM Domain driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
As of commit 71d076ceb2 ("ARM: shmobile: Enable PM and
PM_GENERIC_DOMAINS for SoCs with PM Domains"),
CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with a CPG/MSSR
block.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
As of commit 71d076ceb2 ("ARM: shmobile: Enable PM and
PM_GENERIC_DOMAINS for SoCs with PM Domains"),
CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with MSTP
clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
R can select between two parents. We deal with it like this: During
initialization, check if EXTALR is populated. If so, use it for R. If
not, use R_Internal. clk_mux doesn't help here because we don't want to
switch parents depending on the clock rate. The clock rate (and source)
should stay constant for the watchdog, so I think a setup like this
during initialization makes sense.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gen3 has two clocks (OSC and R) which look like a DIV6 clock but their
divider value is read-only and depends on MD pins at bootup. Add support
for such clocks by reading the value and adding a fixed clock.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
About SD clocks: The clock type is Gen3 specific, the callbacks are all
Gen3 specific; I think the clock definition should also be Gen3 specific
and not in the general header file.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Name the #define guarding compilation of this header
__RENESAS_CLK_DIV6_H__ rather than __SHMOBILE_CLK_DIV6_H__.
This is a follow-up to renaming the directory in which this file lives from
shmobile to renesas which is in turn part of an ongoing process to migrate
from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that
RENESAS seems to be a more appropriate name than SHMOBILE for the majority
of Renesas ARM based SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Along with the above mentioned Kconfig changes it seems appropriate
to also rename files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Along with the above mentioned Kconfig changes it seems appropriate
to also rename directories that only hold drivers for such SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Takeshi Kihara