Most of these relate to endianness problems, and are purely cosmetic.
But a couple of them were legit -- listen interval parsing and some of
the rate selection code would malfunction on BE systems.
There's still one cosmetic warning remaining, in the (admittedly) ugly
code in cw1200_spi.c. It's there because the hardware needs 16-bit SPI
transfers, but many SPI controllers only operate 8 bits at a time.
If there's a cleaner way of handling this, I'm all ears.
Signed-off-by: Solomon Peachy <pizza@shaftnet.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This is only really useful for people who are bringing up new hardware
designs and have access to the proprietary vendor tools that interface
with this mode.
It'll live out of tree until it's rewritten to use a less kludgy interface.
Signed-off-by: Solomon Peachy <pizza@shaftnet.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This avoids problems when building on SPARC targets due to the driver
calling the bus abstraction layer 'sbus'. Not that any SBUS-sporting
SPARC targets are likely to have an SDIO controller, but this is the
correct thing to do.
See http://kisskb.ellerman.id.au/kisskb/buildresult/8846508/
Signed-off-by: Solomon Peachy <pizza@shaftnet.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Remove including <linux/version.h> that don't need it.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Solomon Peachy