2 Commits

Author	SHA1	Message	Date
Geert Uytterhoeven	a4f8a6e60c	clk: renesas: r8a779g0: Add watchdog clock ... Add the module clock used by the RCLK Watchdog Timer on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be	2022-09-18 14:43:51 +02:00
Yoshihiro Shimoda	0ab55cf183	clk: renesas: cpg-mssr: Add support for R-Car V4H ... Initial CPG support for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2022-04-29 12:23:39 +02:00