The "a" version of the MT7620 has single port PCIE bus. The driver is
straightforward without any special magic required. The driver works on
MT7620 and MT7628. There are a few magic values that get written to the
pcie phy and a register of which we only know the name. I marked these
places as vodoo in the comments above the code.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11996/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MT7621 is based on a 1004k core. This patch adds support for the SoC. The
timer and IRQ is just boiler plate as GIC has recently been moved to
generic places in the kernel and just works.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11990/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Some of the newer SoCs use the GIC. This patch splits the INTC out into its
own symbol, allowing us to add the gic code in the following patch.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11989/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
A driver was added in commit 5433acd81e ("MIPS: ralink: add illegal access
driver") without the Kconfig section being added. Fix this by adding the symbol
to the Kconfig file.
Signed-off-by: John Crispin <blogic@openwrt.org>
Reported-by: Paul Bolle <pebolle@tiscali.nl>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9299/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Move the Ralink device-trees to arch/mips/boot/dts/ and update the
Makefiles accordingly. A built-in device-tree is optional, so select
BUILTIN_DTB when it is requested.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: David Daney <david.daney@cavium.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7561/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
USB_ARCH_HAS_EHCI, USB_ARCH_HAS_OHCI, and USB_ARCH_HAS_XHCI were just
removed. Selecting them is a nop. The select statements for these
symbols can be removed too.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In order to avoid keeping an ever growing list of chips which need to
select a specific MIPS_L1_CACHE_SHIFT value introduce multiple internal
and non-exposed Kconfig symbols for the various MIPS_L1_CACHE_SHIFT
values out there and update the relevant Kconfig symbols to select them.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
The Ralink RT3883 SoCs have a built-in PCI Host Controller
device. The patch adds a platform driver and device tree
binding documentation for that.
The patch also enables the HW_HAS_PCI config option. This
is required in order to be able to enable the PCI support.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/5758/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent
of the SoC master clock. If we want to automatic frequency scaling to work we
need to use the systick timer as the clock source.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5669/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add a dtsi file for MT7620A SoC and a sample dts file.
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/5190/
Add a dtsi file for RT3883 SoC and a sample dts file.
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/5189/
Add a dtsi file for RT2880 SoC and a sample dts file.
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/5188/
Add support code for mt7620 SOC.
The code detects the SoC and registers the clk / pinmux settings.
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5177/
Add support code for rt3883 SOC.
The code detects the SoC and registers the clk / pinmux settings.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5185/
Add support code for rt2880 SOC.
The code detects the SoC and registers the clk / pinmux settings.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5176/
Add the Kbuild symbols and Makefiles needed to actually build the ralink code
from this series
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4899/
John Crispin