Sync kernel codes to the same with 590eaf1fec ("Init Repo base on
linux 5.4.32 long term, and add base tlinux kernel interfaces."), which
is from tk4, and it is the base of tk4.
Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
i.MX8MN is a new SoC of i.MX8M series, it also uses speed
grading and market segment fuses for OPP definitions, add
support for this SoC.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This is not currently needed, instead a platform device is always created
from SOC-specific code.
We can use of_machine_is_compatible for per-SOC behavior instead.
Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Early samples without fuses written report "0 0" which means consumer
segment and minimum speed grading. According to datasheet the minimum speed
grade is not supported for consumer parts so all OPPs are disabled
which results in stack dumps later on.
Fix by clamping minimum consumer speed grade to 1 on imx8mm and imx8mq.
Fixes: 4d28ba1d62 ("cpufreq: Add imx-cpufreq-dt driver")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
[ Viresh: s/minumum/minimum/ in patch and log ]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Right now in upstream imx8m cpufreq support just lists a common subset
of OPPs because the higher ones should only be attempted after checking
speed grading in fuses.
Add a small driver which checks speed grading from nvmem cells before
registering cpufreq-dt.
This driver allows unlocking all frequencies for imx8mm and imx8mq and
could be applied to other chips like imx7d
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Jianping Liu