Commit Graph

41 Commits

Author SHA1 Message Date
Wu Hao 724142f8c4 fpga: dfl: fme: add performance reporting support
This patch adds support for performance reporting private feature
for FPGA Management Engine (FME). Now it supports several different
performance counters, including 'basic', 'cache', 'fabric', 'vtd'
and 'vtd_sip'. It allows user to use standard linux tools to access
these performance counters.

e.g. List all events by "perf list"

  perf list | grep fme

  dfl_fme0/cache_read_hit/                     [Kernel PMU event]
  dfl_fme0/cache_read_miss/                    [Kernel PMU event]
  ...

  dfl_fme0/fab_mmio_read/                      [Kernel PMU event]
  dfl_fme0/fab_mmio_write/                     [Kernel PMU event]
  ...

  dfl_fme0/fab_port_mmio_read,portid=?/        [Kernel PMU event]
  dfl_fme0/fab_port_mmio_write,portid=?/       [Kernel PMU event]
  ...

  dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/   [Kernel PMU event]
  dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/   [Kernel PMU event]
  ...

  dfl_fme0/vtd_sip_iotlb_1g_hit/               [Kernel PMU event]
  dfl_fme0/vtd_sip_iotlb_1g_miss/              [Kernel PMU event]
  ...

  dfl_fme0/clock                               [Kernel PMU event]
  ...

e.g. check increased counter value after run one application using
"perf stat" command.

 perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test

 Performance counter stats for './test':

                 1      dfl_fme0/fab_mmio_read/
                 2      dfl_fme0/fab_mmio_write/

       1.009496520 seconds time elapsed

Please note that fabric counters support both fab_* and fab_port_*, but
actually they are sharing one set of performance counters in hardware.
If user wants to monitor overall data events on fab_* then fab_port_*
can't be supported at the same time, see example below:

perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/

 Performance counter stats for 'system wide':

                 0      dfl_fme0/fab_mmio_read/
   <not supported>      dfl_fme0/fab_port_mmio_write,portid=0/

       2.141064085 seconds time elapsed

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Link: https://lore.kernel.org/r/1587949583-12058-3-git-send-email-hao.wu@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28 15:49:28 +02:00
Wu Hao 4284c65a9f fpga: dfl: fme: add thermal management support
This patch adds support to thermal management private feature for DFL
FPGA Management Engine (FME). This private feature driver registers
a hwmon for thermal/temperature monitoring (hwmon temp1_input).
If hardware automatic throttling is supported by this hardware, then
driver also exposes sysfs interfaces under hwmon for thresholds
(temp1_max/ crit/ emergency), threshold alarms (temp1_max_alarm/
temp1_crit_alarm) and throttling policy (temp1_max_policy).

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2019-10-16 19:18:27 -07:00
Greg Kroah-Hartman 526af04054 FPGA Manager changes for 5.4-rc1
Here is the second set of changes for the 5.4 merge window.
 
 This patchset adds support for the v2 revision of Intel (Altera)'s CVP
 parts including the Stratix 10.
 
 All of this patches have been reviewed and been in the last few
 linux-next releases without issues.
 
 Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Merge tag 'fpga-cvp-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next

Moritz writes:

FPGA Manager changes for 5.4-rc1

Here is the second set of changes for the 5.4 merge window.

This patchset adds support for the v2 revision of Intel (Altera)'s CVP
parts including the Stratix 10.

All of this patches have been reviewed and been in the last few
linux-next releases without issues.

Signed-off-by: Moritz Fischer <mdf@kernel.org>

* tag 'fpga-cvp-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
  fpga: altera-cvp: Add Stratix10 (V2) Support
  fpga: altera-cvp: Preparation for V2 parts.
  fpga: altera-cvp: Discover Vendor Specific offset
2019-09-03 21:57:04 +02:00
Thor Thayer e58915179f fpga: altera-cvp: Add Stratix10 (V2) Support
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2019-08-24 11:38:29 -07:00
YueHaibing 3d139703d3 fpga-manager: altera-ps-spi: Fix build error
If BITREVERSE is m and FPGA_MGR_ALTERA_PS_SPI is y,
build fails:

drivers/fpga/altera-ps-spi.o: In function `altera_ps_write':
altera-ps-spi.c:(.text+0x4ec): undefined reference to `byte_rev_table'

Select BITREVERSE to fix this.

Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: fcfe18f885 ("fpga-manager: altera-ps-spi: use bitrev8x4")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Cc: stable <stable@vger.kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20190708071356.50928-1-yuehaibing@huawei.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-07-24 11:29:41 +02:00
Enrico Weigelt 786285f5e0 drivers: fpga: Kconfig: pedantic cleanups
Formatting of Kconfig files doesn't look so pretty, so just
take damp cloth and clean it up.

Signed-off-by: Enrico Weigelt <info@metux.net>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-20 10:41:37 +02:00
Thomas Gleixner ec8f24b7fa treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 10:50:46 +02:00
Nava kishore Manne c09f747112 fpga manager: Adding FPGA Manager support for Xilinx zynqmp
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-15 10:23:18 +02:00
Alan Tull 38cd7ad5bd fpga: altera_freeze_bridge: remove restriction to socfpga
The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA
since it can be used on other platforms such as Stratix10.

Signed-off-by: Alan Tull <atull@kernel.org>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-01-31 16:22:51 +01:00
Alan Tull e7eef1d763 fpga: add intel stratix10 soc fpga manager driver
Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel service layer driver
which does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.

Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Richard Gong <richard.gong@intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-11-26 20:15:07 +01:00
Wu Hao 1a1527cf5d fpga: dfl: add FPGA Accelerated Function Unit driver basic framework
On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
reprogrammed for different functions. It connects to the FPGA
infrastructure (static FPGA region) via a Port. Port CSRs are
implemented separately from the AFU CSRs to provide control and
status of the Port. Once valid PR bitstream is programmed into
the AFU, it allows access to the AFU CSRs in the AFU MMIO space.

This patch only implements basic driver framework for AFU, including
device file operation framework.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-15 13:55:46 +02:00
Wu Hao bb61b9be3e fpga: dfl: add fpga region platform driver for FME
This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-15 13:55:46 +02:00
Wu Hao de892dff17 fpga: dfl: add fpga bridge platform driver for FME
This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set callback for fpga bridge.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-15 13:55:46 +02:00
Wu Hao af275ec616 fpga: dfl: add fpga manager platform driver for FME
This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Kang Luwei <luwei.kang@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-15 13:55:46 +02:00
Kang Luwei 322ddebe54 fpga: dfl: add FPGA Management Engine driver basic framework
The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'. It's a platform device created by
DFL framework.

This patch adds the basic framework of FME platform driver. It defines
sub feature drivers to handle the different sub features, including init,
uinit and ioctl. It also registers the file operations for the device file.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Kang Luwei <luwei.kang@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-15 13:55:45 +02:00
Zhang Yi 72ddd9f340 fpga: add FPGA DFL PCIe device driver
This patch implements the basic framework of the driver for FPGA PCIe
device which implements the Device Feature List (DFL) in its MMIO space.
This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including
both integrated (e.g. Intel Server Platform with In-package FPGA) and
discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-15 13:55:45 +02:00
Wu Hao 543be3d8c9 fpga: add device feature list support
Device Feature List (DFL) defines a feature list structure that creates
a linked list of feature headers within the MMIO space to provide an
extensible way of adding features. This patch introduces a kernel module
to provide basic infrastructure to support FPGA devices which implement
the Device Feature List.

Usually there will be different features and their sub features linked into
the DFL. This code provides common APIs for feature enumeration, it creates
a container device (FPGA base region), walks through the DFLs and creates
platform devices for feature devices (Currently it only supports two
different feature devices, FPGA Management Engine (FME) and Port which
the Accelerator Function Unit (AFU) connected to). In order to enumerate
the DFLs, the common APIs required low level driver to provide necessary
enumeration information (e.g. address for each device feature list for
given device) and fill it to the dfl_fpga_enum_info data structure. Please
refer to below description for APIs added for enumeration.

Functions for enumeration information preparation:
 *dfl_fpga_enum_info_alloc
   allocate enumeration information data structure.

 *dfl_fpga_enum_info_add_dfl
   add a device feature list to dfl_fpga_enum_info data structure.

 *dfl_fpga_enum_info_free
   free dfl_fpga_enum_info data structure and related resources.

Functions for feature device enumeration:
 *dfl_fpga_feature_devs_enumerate
   enumerate feature devices and return container device.

 *dfl_fpga_feature_devs_remove
   remove feature devices under given container device.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-15 13:55:45 +02:00
Paolo Pisati 88fb3a0023 fpga: lattice machxo2: Add Lattice MachXO2 support
This patch adds support to the FPGA manager for programming
MachXO2 device’s internal flash memory, via slave SPI.

Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
[atull@kernel.org: use existing FPGA mgr API]
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-04-23 13:33:01 +02:00
Geert Uytterhoeven 84d84c5b8f fpga: Remove depends on HAS_DMA in case of platform dependency
Remove dependencies on HAS_DMA where a Kconfig symbol depends on another
symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST".
In most cases this other symbol is an architecture or platform specific
symbol, or PCI.

Generic symbols and drivers without platform dependencies keep their
dependencies on HAS_DMA, to prevent compiling subsystems or drivers that
cannot work anyway.

This simplifies the dependencies, and allows to improve compile-testing.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-04-23 13:31:27 +02:00
Alan Tull 84e93f1d4f fpga: clean up fpga Kconfig
The fpga menuconfig has gotten messy.  The bridges and managers are
mixed together.

* Separate the bridges and things dependent on CONFIG_FPGA_BRIDGE
  from the managers.
* Group the managers by vendor in order that they were added
  to the kernel.

The following is what the menuconfig ends up looking like more or less
(platform dependencies are hiding some of these on any given
platform).

    --- FPGA Configuration Framework
    <*>   Altera SOCFPGA FPGA Manager
    <*>   Altera SoCFPGA Arria10
    <*>   Altera Partial Reconfiguration IP Core
    <*>     Platform support of Altera Partial Reconfiguration IP Core
    <*>   Altera FPGA Passive Serial over SPI
    <*>   Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager
    <*>   Xilinx Zynq FPGA
    <*>   Xilinx Configuration over Slave Serial (SPI)
    <*>   Lattice iCE40 SPI
    <*>   Technologic Systems TS-73xx SBC FPGA Manager
    <*>   FPGA Bridge Framework
    <*>     Altera SoCFPGA FPGA Bridges
    <*>     Altera FPGA Freeze Bridge
    <*>     Xilinx LogiCORE PR Decoupler
    <*>     FPGA Region
    <*>       FPGA Region Device Tree Overlay Support

Signed-off-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-28 16:30:38 +01:00
Alan Tull ef3acdd820 fpga: region: move device tree support to of-fpga-region.c
Create of-fpga-region.c and move the following functions without
modification from fpga-region.c.

* of_fpga_region_find
* of_fpga_region_get_mgr
* of_fpga_region_get_bridges
* child_regions_with_firmware
* of_fpga_region_parse_ov
* of_fpga_region_notify_pre_apply
* of_fpga_region_notify_post_remove
* of_fpga_region_notify
* of_fpga_region_probe
* of_fpga_region_remove

Create two new functions with some code from fpga_region_init/exit.

* of_fpga_region_init
* of_fpga_region_exit

Signed-off-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-28 16:30:38 +01:00
Anatolij Gustschin 34d1dc17ce fpga manager: Add Altera CvP driver
Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
and Arria-10 FPGAs via CvP.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-17 17:26:15 +02:00
Joshua Clayton 5692fae074 fpga manager: Add altera-ps-spi driver for Altera FPGAs
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.

This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-17 17:26:14 +02:00
Vincent Legoll 50fa028595 Make FPGA a menuconfig to ease disabling it all
No need to get into the submenu to disable all FPGA-related config entries

Signed-off-by: Vincent Legoll <vincent.legoll@gmail.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-17 17:26:14 +02:00
Moritz Fischer 7e961c12be fpga: Add support for Xilinx LogiCORE PR Decoupler
This adds support for the Xilinx LogiCORE PR Decoupler
soft-ip that does decoupling of PR regions in the FPGA
fabric during partial reconfiguration.

Signed-off-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-08 17:50:36 +02:00
Matthew Gerlach 5b73cb5b01 fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-08 17:45:28 +02:00
Matthew Gerlach d201cc17a8 fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-08 17:45:28 +02:00
Anatolij Gustschin 061c97d13f fpga manager: Add Xilinx slave serial SPI driver
The driver loads FPGA firmware over SPI, using the "slave serial"
configuration interface on Xilinx FPGAs.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-08 17:45:28 +02:00
Joel Holdsworth 21f8ba2ef3 fpga: Add support for Lattice iCE40 FPGAs
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.

Signed-off-by: Joel Holdsworth <joel@airwebreathe.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-03-17 15:10:48 +09:00
Florian Fainelli 4348f7e2ae FPGA: Add TS-7300 FPGA manager
Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.

The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-03-17 15:10:48 +09:00
Jason Gunthorpe a0e1b61858 fpga: Add COMPILE_TEST to all drivers
Like Zynq the Altera drivers compile fine on x86 and others too,
so make it easier to compile test this stuff.

A10 requires REGMAP_MMIO to compile, so be explicit rather than
relying on it via ARCH_SOCFPGA.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Alan Tull <atull@opensource.altera.com>
2016-11-29 15:51:44 -06:00
Alan Tull acbb910ae0 fpga-manager: Add Socfpga Arria10 support
Add low level driver to support reprogramming FPGAs for Altera
SoCFPGA Arria10.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10 17:03:36 +01:00
Alan Tull ca24a648f5 fpga: add altera freeze bridge support
Add a low level driver for Altera Freeze Bridges to the FPGA Bridge
framework.  A freeze bridge is a bridge that exists in the FPGA
fabric to isolate one region of the FPGA from the busses while that
one region is being reprogrammed.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10 17:03:36 +01:00
Alan Tull e5f8efa5c8 ARM: socfpga: fpga bridge driver support
Supports Altera SOCFPGA bridges:
 * fpga2sdram
 * fpga2hps
 * hps2fpga
 * lwhps2fpga

Allows enabling/disabling the bridges through the FPGA
Bridge Framework API functions.

The fpga2sdram driver only supports enabling and disabling
of the ports that been configured early on.  This is due to
a hardware limitation where the read, write, and command
ports on the fpga2sdram bridge can only be reconfigured
while there are no transactions to the sdram, i.e. when
running out of OCRAM before the kernel boots.

Device tree property 'init-val' configures the driver to
enable or disable the bridge during probe.  If the property
does not exist, the driver will leave the bridge in its
current state.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10 17:03:36 +01:00
Alan Tull 0fa20cdfcc fpga: fpga-region: device tree control for FPGA
FPGA Regions support programming FPGA under control of the Device
Tree.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10 17:03:35 +01:00
Alan Tull 21aeda950c fpga: add fpga bridge framework
This framework adds API functions for enabling/
disabling FPGA bridges under kernel control.

This allows the Linux kernel to disable FPGA bridges
during FPGA reprogramming and to enable FPGA bridges
when FPGA reprogramming is done.  This framework is
be manufacturer-agnostic, allowing it to be used in
interfaces that use the FPGA Manager Framework to
reprogram FPGA's.

The functions are:
* of_fpga_bridge_get
* fpga_bridge_put
   Get/put an exclusive reference to a FPGA bridge.

* fpga_bridge_enable
* fpga_bridge_disable
   Enable/Disable traffic through a bridge.

* fpga_bridge_register
* fpga_bridge_unregister
   Register/unregister a device-specific low level FPGA
   Bridge driver.

Get an exclusive reference to a bridge and add it to a list:
* fpga_bridge_get_to_list

To enable/disable/put a set of bridges that are on a list:
* fpga_bridges_enable
* fpga_bridges_disable
* fpga_bridges_put

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10 17:03:35 +01:00
Jean Delvare 54e9b09972 fpga manager: Add hardware dependency to Zynq driver
The Zynq FPGA manager driver serves no purpose on other architectures
so hide it unless build-testing.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-09-08 17:31:44 +02:00
Sudip Mukherjee 1c8cb40949 drivers/fpga/Kconfig: fix build failure
While building m32r allmodconfig the build is failing with the error:

  ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined!

Xilinx Zynq FPGA is using DMA but there was no dependency while
building.

Link: http://lkml.kernel.org/r/1464346526-13913-1-git-send-email-sudipm.mukherjee@gmail.com
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-08-04 08:50:07 -04:00
Moritz Fischer 37784706bf fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000
This commit adds FPGA Manager support for the Xilinx Zynq chip.
The code borrows some from the xdevcfg driver in Xilinx'
vendor tree.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-17 21:57:16 -07:00
Alan Tull fab6266e82 fpga manager: add driver for socfpga fpga manager
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07 18:08:15 +01:00
Alan Tull 6a8c3be7ec add FPGA manager core
API to support programming FPGA's.

The following functions are exported as GPL:
* fpga_mgr_buf_load
   Load fpga from image in buffer

* fpga_mgr_firmware_load
   Request firmware and load it to the FPGA.

* fpga_mgr_register
* fpga_mgr_unregister
   FPGA device drivers can be added by calling
   fpga_mgr_register() to register a set of
   fpga_manager_ops to do device specific stuff.

* of_fpga_mgr_get
* fpga_mgr_put
   Get/put a reference to a fpga manager.

The following sysfs files are created:
* /sys/class/fpga_manager/<fpga>/name
  Name of low level driver.

* /sys/class/fpga_manager/<fpga>/state
  State of fpga manager

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07 18:08:15 +01:00