Commit Graph

22 Commits

Author SHA1 Message Date
Thomas Bogendoerfer 601637e42d MIPS: Remove mach-*/war.h
After conversion of all WAR defines we can now remove all mach-*/war.h
files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:25:27 +02:00
Thomas Bogendoerfer ab5743079b MIPS: Get rid of BCM1250_M3_WAR
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS.
So using this option directly lets and remove define.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:25:03 +02:00
Thomas Bogendoerfer 43df4eb2fc MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
SB1250 uart bug is related to PASS 2 workarounds. Use config
CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:51 +02:00
Thomas Bogendoerfer a7fbed988f MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option
Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:40 +02:00
Thomas Bogendoerfer 256ec489f1 MIPS: Convert R10000_LLSC_WAR info a config option
Use a new config option to enabel R1000_LLSC workaound and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:27 +02:00
Thomas Bogendoerfer 886ee1363a MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option
Use a new config option to enable I-cache refill workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:19 +02:00
Thomas Bogendoerfer 24a1c023f3 MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:09 +02:00
Thomas Bogendoerfer 142439b052 MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:01 +02:00
Thomas Bogendoerfer 44def3426e MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:23:48 +02:00
Thomas Bogendoerfer 5e5b652712 MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:23:38 +02:00
Thomas Bogendoerfer 802b83627f MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
Use a new config option to enable R4600 V1 index I-cacheop workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:23:29 +02:00
Thomas Bogendoerfer c0de00b286
MIPS: SGI-IP22/28: Use PROM for memory detection
EARLY_PRINTK uses ArcWrite (via prom_putchar) on IP22/28, which needs
to not mess up PROMs data structures. ARC PROM gives out a list of
memory chunks, which are used and which are free. This fixes the
problem of not working early printk.

By using XKPHYS spaces more than 256MB memory on Indigo2 R4k machines
is working now, too.

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-10-09 14:55:57 -07:00
Thomas Bogendoerfer 931e1bfea4
MIPS: SGI-IP22: set PHYS_OFFSET to memory start
IP22 started at physical 0x08000000. To avoid wasting memory for
page structs set PHYS_OFFSET.

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-10-09 14:55:55 -07:00
Paul Burton ccd51b9fc3
MIPS: Remove unused R5432_CP0_INTERRUPT_WAR
R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and
so the workaround is never used. Remove the dead code.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-07-23 14:33:44 -07:00
Maciej W. Rozycki 65ae8d2621 MIPS16e2: Provide feature overrides for non-MIPS16 systems
Hardcode the absence of the MIPS16e2 ASE for all the systems that do so
for the MIPS16 ASE already, providing for code to be optimized away.

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16097/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-11 14:13:06 +02:00
Maciej W. Rozycki 18a2c2c6b9 MIPS: Correct `nofpu' non-functionality
The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu'
kernel option will be ignored.  Remove any such overrides and add a
cautionary note.  Hardcoding to 0 is fine for FPU-less platforms.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9694/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-08 01:09:49 +02:00
Ralf Baechle 66b047dc9c MIPS: IP22: This platform may come with either MIPS III or MIPS IV CPUs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-23 15:10:59 +02:00
Ralf Baechle 69f24d1784 MIPS: Optimize current_cpu_type() for better code.
o Move current_cpu_type() to a separate header file
 o #ifdefing on supported CPU types lets modern GCC know that certain
   code in callers may be discarded ideally turning current_cpu_type() into
   a function returning a constant.
 o Use current_cpu_type() rather than direct access to struct cpuinfo_mips.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5833/
2013-09-17 18:50:53 +02:00
Ralf Baechle bdf20507da MIPS: PMC-Sierra Yosemite: Remove support.
Nobody seems to be interested anymore and upstream also never had an
ethernet driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-13 18:15:30 +01:00
Ralf Baechle 475032564e MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.
Most supported systems currently hardwire cpu_has_dsp to 0, so we also
can disable support for cpu_has_dsp2 resulting in a slightly smaller
kernel.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-11 11:10:43 +02:00
Thomas Bogendoerfer 7d81a5e03d MIPS: IP22/28: Switch over to RTC class driver
This patchset removes some dead code and creates a platform device
for the RTC class driver.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-15 12:46:51 +01:00
Ralf Baechle 384740dc49 MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11 16:18:52 +01:00