The current GPL only licensing on the device tree makes it very
impractical for other software components licensed under another
license.
In order to make it easier for them to reuse our device trees,
relicense our device trees under a GPL/X11 dual-license.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Arnaud Ebalard <arno@natisbad.org>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Willy Tarreau <w@1wt.eu>
The DT branch adds a lot of new stuff for additional SoC and board
support. The branch is the largest one and contains 513 out of the
total 972 non-merge arm-soc changesets for 3.19.
Most of the changes are about enabling additional on-chip devices for
existing machines, but there are also an unusual number of new SoC
types being added this time:
* AMLogic Meson8
* ARM Realview in DT mode
* Allwinner A80
* Broadcom BCM47081
* Broadcom Cygnus
* Freescale LS1021A
* Freescale Vybrid 500 series
* Mediatek MT6592, MT8127, MT8135
* STMicroelectronics STiH410
* Samsung Exynos4415
The level of support for the above differs widely, some are just
stubs with nothing more than CPU, memory and a UART, but others
are fairly complete. As usual, these get extended over time.
There are also many new boards getting added, this is the
list of model strings that are showing up in new dts files:
* ARM RealView PB1176
* Altera SOCFPGA Arria 10
* Asus RT-N18U (BCM47081)
* Buffalo WZR-1750DHP (BCM4708)
* Buffalo WZR-600DHP2 (BCM47081)
* Cygnus Enterprise Phone (BCM911360_ENTPHN)
* D-Link DIR-665
* Google Spring
* IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
* IGEPv2 Rev. F (TI OMAP AM/DM37x)
* LS1021A QDS Board
* LS1021A TWR Board
* LeMaker Banana Pi
* MarsBoard RK3066
* MediaTek MT8127 Moose Board
* MediaTek MT8135 evaluation board
* Mele M3
* Merrii A80 Optimus Board
* Netgear R6300 V2 (BCM4708)
* Nomadik STN8815NHK
* NovaTech OrionLXm
* Olimex A20-OLinuXino-LIME2
* Raspberry Pi Model B+
* STiH410 B2120
* Samsung Monk board
* Samsung Rinato board
* Synology DS213j
* Synology DS414
* TBS2910 Matrix ARM mini PC
* TI AM5728 BeagleBoard-X15
* Toradex Colibri VF50 on Colibri Evaluation Board
* Zynq ZYBO Development Board
Other notable changes include:
* exynos: cleanup of existing dts files
* mvebu: improved pinctrl support for Armada 370/XP
* nomadik: restructuring dts files
* omap: added CAN bus support
* shmobile: added clock support for some SoCs
* shmobile: added sound support for some SoCs
* sirf: reset controller support
* sunxi: continuing the relicensing under dual GPL/MIT
* sunxi: lots of new on-chip device support
* sunxi: working simplefb support (long awaited)
* various: provide stdout-path property for earlycon
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Arnd Bergmann:
"The DT branch adds a lot of new stuff for additional SoC and board
support. The branch is the largest one and contains 513 out of the
total 972 non-merge arm-soc changesets for 3.19.
Most of the changes are about enabling additional on-chip devices for
existing machines, but there are also an unusual number of new SoC
types being added this time:
- AMLogic Meson8
- ARM Realview in DT mode
- Allwinner A80
- Broadcom BCM47081
- Broadcom Cygnus
- Freescale LS1021A
- Freescale Vybrid 500 series
- Mediatek MT6592, MT8127, MT8135
- STMicroelectronics STiH410
- Samsung Exynos4415
The level of support for the above differs widely, some are just stubs
with nothing more than CPU, memory and a UART, but others are fairly
complete. As usual, these get extended over time.
There are also many new boards getting added, this is the list of
model strings that are showing up in new dts files:
- ARM RealView PB1176
- Altera SOCFPGA Arria 10
- Asus RT-N18U (BCM47081)
- Buffalo WZR-1750DHP (BCM4708)
- Buffalo WZR-600DHP2 (BCM47081)
- Cygnus Enterprise Phone (BCM911360_ENTPHN)
- D-Link DIR-665
- Google Spring
- IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
- IGEPv2 Rev. F (TI OMAP AM/DM37x)
- LS1021A QDS Board
- LS1021A TWR Board
- LeMaker Banana Pi
- MarsBoard RK3066
- MediaTek MT8127 Moose Board
- MediaTek MT8135 evaluation board
- Mele M3
- Merrii A80 Optimus Board
- Netgear R6300 V2 (BCM4708)
- Nomadik STN8815NHK
- NovaTech OrionLXm
- Olimex A20-OLinuXino-LIME2
- Raspberry Pi Model B+
- STiH410 B2120
- Samsung Monk board
- Samsung Rinato board
- Synology DS213j
- Synology DS414
- TBS2910 Matrix ARM mini PC
- TI AM5728 BeagleBoard-X15
- Toradex Colibri VF50 on Colibri Evaluation Board
- Zynq ZYBO Development Board
Other notable changes include:
- exynos: cleanup of existing dts files
- mvebu: improved pinctrl support for Armada 370/XP
- nomadik: restructuring dts files
- omap: added CAN bus support
- shmobile: added clock support for some SoCs
- shmobile: added sound support for some SoCs
- sirf: reset controller support
- sunxi: continuing the relicensing under dual GPL/MIT
- sunxi: lots of new on-chip device support
- sunxi: working simplefb support (long awaited)
- various: provide stdout-path property for earlycon"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (510 commits)
ARM: dts: rk3288: add arm,cpu-registers-not-fw-configured
Revert "ARM: dts: rockchip: temporarily disable smp on rk3288"
ARM: BCM5301X: Add DT for Buffalo WZR-600DHP2
ARM: BCM5301X: Add DT for Asus RT-N18U
ARM: BCM5301X: Add DT for Buffalo WZR-1750DHP
ARM: BCM5301X: Add DT for Netgear R6300 V2
ARM: BCM5301X: Add buttons for Netgear R6250
ARM: dts: rockchip: Add input voltage supply regulators in pmic for Marsboard
ARM: BCM5301X: Add IRQs to Broadcom's bus-axi in DTS file
arm: dts: zynq: Add Digilent ZYBO board
arm: dts: zynq: Move crystal freq. to board level
doc: dt: vendor-prefixes: Add Digilent Inc
Documentation: devicetree: Fix Xilinx VDMA specification
ARM: dts: rockchip: set FIFO size for SDMMC, SDIO and EMMC on rk3066 and rk3188
ARM: dts: rockchip: add label property for leds on Radxa Rock
ARM: BCM5301X: Add LEDs for Netgear R6250 V1
ARM: BCM5301X: Add Broadcom's bus-axi to the DTS file
ARM: dts: add sysreg phandle to i2c device nodes for exynos
ARM: dts: Remove unused bootargs from exynos3250-rinato
ARM: dts: add board dts file for Exynos3250-based Monk board
...
The suspend/resume sequence on Armada XP needs to modify a number of
registers in the SDRAM controller. Therefore, this commit updates the
Armada XP Device Tree description to include the SDRAM controller
Device Tree node.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-17-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
There are currently 2 differents naming conventions used between the
existing Armada SoC DT files for pinctrl entries (*_pin(s): *-pin(s)
and pmx_*: pmx-*) with a vast majority of files using the former:
$ grep _pin arch/arm/boot/dts/armada-*.dts* | wc -l
155
$ grep pmx arch/arm/boot/dts/armada-*.dts* | wc -l
13
In fact, only some Armada XP files are using the second variant.
This patch normalizes those files (mainly ge0/1 entries) to use
the first variant.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/00114c3169e1d93259ff4150ed46ee36eae16b1e.1416670812.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch defines common Armada XP pinctrl settings in armada-xp.dtsi
for the supported SPI interface (MPP36-39) and use it as default
for Armada XP spi interface. That being done, it removes the now
redundant definitions in armada-xp-axpwifiap.dts.
Note: this patch has the potential to break out-of-tree users w/o
specific pinctrl settings for their spi interfaces if the default
above does not match their config (i.e. if they do not use CS0).
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/d404b7abd80ee5a0fd8e8d3586d33cd37740d589.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch defines common Armada XP pinctrl settings for uart2 and
uart3 interfaces (uart0 and uart1 rx/tx do not rely on MPP):
uart2: MPP42-43 as default
uart3: MPP44-45 as default
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/fd51c080c7139a67ec01df8d797f1e88ce557796.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
What was done by Sebastian in 264a05e19b ("ARM: mvebu: armada-xp:
Add node alias to pinctrl and add base address") and 01c434225e
("ARM: mvebu: armada-xp: Use pinctrl node alias") can also be done for
Armada 370, i.e.
- Rename Armada 370 pinctrl node to pin-ctrl with its address encoded
- Add a node alias to access the pinctrl node easily.
- use the newly available alias in existing Armada 370 .dts files
We can even go a bit further by putting the pinctrl node definition in
armada-370-xp.dtsi, with only its reg property defined. This allows us
to then also use the newly defined node alias in armada-xp.dtsi,
armada-370.dtsi.
Suggested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/b54eb45e5242728aace3ce8aef2eae4251f8dea3.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds uartX labels for Armada SoC serial nodes. This is
a preliminary work to be able to easily reference the serial lines
in Device Tree files. One expected use is when providing stdout-path
property for barebox.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/0683d1a823fe9b75849f3dafcf1cf6ee291cdca6.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
There is a GMII setting for GE0, add it to the common pinctrl node.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-By: Benoit Masson <yahoo@perenite.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Pinctrl settings for GE0 and GE1 are not only usable on RD-AXPWiFiAP.
Moreover, naming the RGMII settings pmx-ge{0,1} is not precise enough
as there is also a GMII setting for GE0.
Move the pinctrl sub-nodes to the common pinctrl node and rename them
to pmx-ge{0,1}-rgmii.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-By: Benoit Masson <yahoo@perenite.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In other MVEBU SoCs, the pin controller node is called pin-ctrl with
its base address added. Also, we have a node alias to access the pinctrl
node easily. Fix this for Armada XP pinctrl nodes to be consistent with
other SoCs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-By: Benoit Masson <yahoo@perenite.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
All current Armada XP SoCs have their pin controller at 0x18000/0x38.
Move the common properties of pinctrl nodes to armada-xp.dtsi to allow
to share pinctrl settings later.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-By: Benoit Masson <yahoo@perenite.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The L2 cache controller on the Armada 370 and Armada XP SoCs is a
unified cache. Moreover, the Aurora cache controller is compatible
with the L2x0 cache controller: the "cache-unified" property is
required by its binding.
This patch fixes the Aurora L2 cache node for the Armada 370 and
Armada XP SoCs by adding this property.
Reported-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1412588276-4514-1-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to support dynamic frequency scaling:
* the cpuclk Device Tree node needs to be updated to describe a
second set of registers describing the PMU DFS registers.
* the clock-latency property of the CPUs must be filled, otherwise
the ondemand and conservative cpufreq governors refuse to work. The
latency is high because the cost of a frequency transition is quite
high on those CPUs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Back when the Armada 370 and Armada XP initial support was introduced,
the only way to pass the clock frequency to the of_serial driver was
through a clock-frequency Device Tree property.
Thanks to 0bbeb3c3e8 ('of serial port
driver - add clk_get_rate() support'), it is possible to use the
standard 'clocks' DT property to reference the clock used for a
particular UART controller. This clock is then used by the of_serial
driver to retrieve the clock rate.
This commit modifies the SoC-level Device Tree files of Armada 370,
Armada XP, Armada 375 and Armada 38x to use this possibility. Since
there is no gatable clock for the UART controllers, we simply
reference the TCLK, which is the main SoC clock for the peripherals.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397806908-7550-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Following the introduction of the new PMSU Device Tree binding, as
well as the separate CPU reset binding, this commit switches the
Armada 370 and Armada XP Device Trees to use them.
The PMSU node is moved from the Armada XP specific armada-xp.dtsi to
the common Armada 370/XP armada-370-xp.dtsi because the PMSU is in
fact available at the same location on both SOCs.
The CPU reset node is then added on both Armada 370 and Armada XP,
with a different compatible string. On Armada 370, the CPU reset
driver is not really needed as Armada 370 is single core and the only
use of the CPU reset driver is to boot secondary processors, but it
still makes sense to have this CPU reset register described in the
Device Tree.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add the DT nodes to enable watchdog support available in Armada 370
and Armada XP SoCs.
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The per-CPU PMSU registers documented in the datasheet start at
0x22100 and the last register for CPU3 is at 0x22428. However, the DT
informations use <0x22100 0x430>, which makes the region end at
0x22530 and not 0x22430.
Moreover, looking at the datasheet, we can see that the registers for
CPU0 start at 0x22100, for CPU1 at 0x22200, for CPU2 at 0x22300 and
for CPU3 at 0x22400. It seems clear that 0x100 bytes of registers have
been used per CPU.
Therefore, this commit reduces the length of the PMSU per-CPU register
area from the incorrect 0x430 bytes to a more logical 0x400 bytes.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
- Always build in board-generic, and add pdata quirks and auxdata
support for it so we have all the pdata related quirks
in the same place.
- Merge of the drivers/pinctrl changes that are needed for PM
to continue working on omap3 and also needed for other omaps
eventually. The three pinctrl related patches have been acked
by Linus Walleij and are pulled into both the pinctrl tree
and this branch.
- Few defconfig related changes for drivers needed.
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Merge tag 'omap-for-v3.13/quirk-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
Changes needed to prepare for making omap3 device tree only:
- Always build in board-generic, and add pdata quirks and auxdata
support for it so we have all the pdata related quirks
in the same place.
- Merge of the drivers/pinctrl changes that are needed for PM
to continue working on omap3 and also needed for other omaps
eventually. The three pinctrl related patches have been acked
by Linus Walleij and are pulled into both the pinctrl tree
and this branch.
- Few defconfig related changes for drivers needed.
* tag 'omap-for-v3.13/quirk-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (523 commits)
ARM: configs: omap2plus_defconfig: enable dwc3 and dependencies
ARM: OMAP2+: Add WLAN modules and of_serial to omap2plus_defconfig
ARM: OMAP2+: Run make savedefconfig on omap2plus_defconfig to shrink it
ARM: OMAP2+: Add minimal 8250 support for GPMC
ARM: OMAP2+: Use pdata quirks for wl12xx for omap3 evm and zoom3
ARM: OMAP: Move DT wake-up event handling over to use pinctrl-single-omap
ARM: OMAP2+: Add support for auxdata
pinctrl: single: Add support for auxdata
pinctrl: single: Add support for wake-up interrupts
pinctrl: single: Prepare for supporting SoC specific features
ARM: OMAP2+: igep0020: use display init from dss-common
ARM: OMAP2+: pdata-quirks: add legacy display init for IGEPv2 board
+Linux 3.12-rc4
Signed-off-by: Kevin Hilman <khilman@linaro.org>
With the addition of the Armada XP reference clock, we can now model
accurately the available clock inputs for the timer: namely, nbclk
and refclk. For each of this clock inputs we assign a name, for the
driver to select as appropriate.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada XP SoC has a reference 25 MHz fixed-clock that is used in
some controllers such as the timer and the watchdog. This commit adds
a DT representation of this clock through a fixed-clock compatible node.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The mv64xxx-i2c embedded in the Armada XP have a new feature to
offload i2c transaction. This new version of the IP come also with
some errata. This lead to the introduction to a another compatible
string.
This commit split the i2c information into armada-370.dtsi and
armada-xp.dtsi. Most of the data remains the same and stay in the
common file Armada-370-xp.dtsi. With this new feature the size of the
registers are bigger for Armada XP and the new compatible string is
used.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The "marvell,armada-370-xp-timer" compatible string, together with
the "marvell,timer-25Mhz" property are deprecated and should be
removed from current DT.
Instead, the timer DT nodes are now required to have an appropriate
compatible string, which should be either "marvell,armada-370-timer"
or "marvell,armada-xp-timer", depending on SoC.
The clock property is now required only for Armada 370 so move it accordingly.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to access the SoC BootROM, we need to declare a mapping
(through a ranges property). The mbus driver will use this property
to allocate a suitable address decoding window.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370/XP SoC family has a completely configurable address
space handled by the MBus controller.
This patch introduces the device tree layout of MBus, making the
'soc' node as mbus-compatible.
Since every peripheral/controller is a child of this 'soc' node,
this makes all of them sit behind the mbus, thus describing the
hardware accurately.
A translation entry has been added for the internal-regs mapping.
This can't be done in the common armada-370-xp.dtsi because A370
and AXP have different addressing width.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
These changes from 30 individual branches for the most part update device
tree files, but there are also a few source code changes that have crept
in this time, usually in order to atomically move over a driver from
using hardcoded data to DT probing.
A number of platforms change their DT files to use the C preprocessor,
which is causing a bit of churn, but that is hopefully only this once.
There are a few conflicts with the other branches unfortunately:
* in exynos5440.dtsi and kirkwood-6281.dtsi, device nodes are added
from multiple branches. Need to be careful to have the right
set of closing braces as git gets this one wrong.
* In kirkwood.dtsi, one 'ranges' line got split into two lines, while
another line got added. Order of the lines does not matter.
* in sama5d3.dtsi, some cleanup was merged the wrong way, causing
a bogus conflict. We want the 'dmas' and 'dma-names' properties
to get added here.
* Two lines got removed independently in arch/arm/mach-mxs/mach-mxs.c
* Contents get added independently in arch/arm/mach-omap2/cclock33xx_data.c
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree changes from Arnd Bergmann:
"These changes from 30 individual branches for the most part update
device tree files, but there are also a few source code changes that
have crept in this time, usually in order to atomically move over a
driver from using hardcoded data to DT probing.
A number of platforms change their DT files to use the C preprocessor,
which is causing a bit of churn, but that is hopefully only this once"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits)
ARM: at91: dt: rm9200ek: add spi support
ARM: at91: dt: rm9200: add spi support
ARM: at91/DT: at91sam9n12: add SPI DMA client infos
ARM: at91/DT: sama5d3: add SPI DMA client infos
ARM: at91/DT: fix SPI compatibility string
ARM: Kirkwood: Fix the internal register ranges translation
ARM: dts: bcm281xx: change comment to C89 style
ARM: mmc: bcm281xx SDHCI driver (dt mods)
ARM: nomadik: add the new clocks to the device tree
clk: nomadik: implement the Nomadik clocks properly
ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
ARM: dts: omap4-panda: Fix DVI EDID reads
ARM: dts: omap4-panda: Add USB Host support
arm: mvebu: enable mini-PCIe connectors on Armada 370 RD
ARM: shmobile: irqpin: add a DT property to enable masking on parent
ARM: dts: AM43x EPOS EVM support
ARM: dts: OMAP5: Add bandgap DT entry
ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
...
- mvebu
- set aliases for ethernet interfaces
- PCIe range for armada-xp-db
- rm unused properties on A370
- kirkwood
- assign sheevaplug pinmuxs to correct devices
- enable second PCIe port for ts219
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Merge tag 'dt-3.11-5' of git://git.infradead.org/users/jcooper/linux into next/dt
From Jason Cooper:
mvebu dt changes for v3.11 (round 5)
- mvebu
- set aliases for ethernet interfaces
- PCIe range for armada-xp-db
- rm unused properties on A370
- kirkwood
- assign sheevaplug pinmuxs to correct devices
- enable second PCIe port for ts219
* tag 'dt-3.11-5' of git://git.infradead.org/users/jcooper/linux:
ARM: Kirkwood: ts219: Enable second PCIe port in DT.
ARM: mvebu: Remove device tree unused properties on A370
arm: mvebu: armada-xp-db: ensure PCIe range is specified
arm: kirkwood: sheevaplug: move pinmux configs to the right devices
ARM: mvebu: set aliases for ethernet controllers
Signed-off-by: Olof Johansson <olof@lixom.net>
These aliases are used when feeding the DT from ATAGS to set the
devices MAC addresses.
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The length of the registers area for the Marvell 370/XP Ethernet
controller was incorrect in the .dtsi: 0x2400 while it should have
been 0x4000. Until now, this problem wasn't noticed because there was
a large static mapping for all I/Os set up by ->map_io(). But since
we're going to get rid of this static mapping, we need to ensure that
the register areas are properly sized.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The mpic alias is already defined in the common armada-370-xp.dtsi, so
there's no need to repeat it at the armada-xp.dtsi and armada-370.dtsi
level.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Introduce a 'internal-regs' subnode, under which all devices are
moved. This is not really needed for now, but will be for the
mvebu-mbus driver. This generates a lot of code movement since it's
indenting by one more tab all the devices. So it was a good
opportunity to fix all the bad indentation.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
reorganize the .dts and .dtsi files so that all devices are under the
soc { } node (currently some devices such as the interrupt controller,
the L2 cache and a few others are outside).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
- Kirkwood
- a couple of small fixes for the Iomega ix2-200 board (ether and led)
- mvebu
- allow GPIO button to work on Mirabox when running SMP
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Merge tag 'tags/mvebu_fixes_for_v3.9_round3' into mvebu/dt
pulling in mvebu branches which changes armada*.dts? files for LPAE changes
mvebu fixes for v3.9 round 3
- Kirkwood
- a couple of small fixes for the Iomega ix2-200 board (ether and led)
- mvebu
- allow GPIO button to work on Mirabox when running SMP
This patch adds support for the thermal controller available in
all Armada XP boards. This controller has two 4-byte registers:
one to read the thermal sensor, the other for sensor initialization.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Setting the reg-io-width to 1 byte represents more accurate
description of the HW.
This will fix an issue where UART driver causes kernel
panic during bootup. Gregory CLEMENT traced the issue to
autoconfig() in 8250.c, where the existence of FIFO is
checked from UART_IIR register. The register is now read as
32-bit value as the reg-io-width is set to 4-bytes. The
retuned value seems to contain bogus data for bits 31:8,
causing the issue.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370 and Armada XP SoC has an Orion EHCI USB controller.
This patch adds support for this controller in Armada 370
and Armada XP SoC common device tree files.
Cc: Lior Amsalem <alior@marvell.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch makes the interrupt controller driver more SMP aware for
the Armada XP SoCs. It adds the support for the per-CPU irq. It also
adds the implementation for the set_affinity hook.
Patch initialy wrote by Yehuda Yitschak and reworked by Gregory
CLEMENT.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We originally thought that the MV78230 variant of the Armada XP had
four Ethernet interfaces, like the other variants MV78260 and
MV78460. In fact, this is not true, and the MV78230 has only three
Ethernet interfaces.
So, the definitions of the Ethernet interfaces is now done as follows:
* armada-370-xp.dtsi: definitions of the first two interfaces, that
are common to Armada 370 and Armada XP
* armada-xp.dtsi: definition of the third interface, common to all
Armada XP variants.
* armada-xp-mv78260.dtsi and armada-xp-mv78460.dtsi: definition of
the fourth interface.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The UART controller used in the Armada 370 and Armada XP SoCs is the
Synopsys DesignWare 8250 (aka Synopsys DesignWare ABP UART). The
improper use of the ns16550 can lead to a kernel oops during boot if
a character is sent to the UART before the initialization of the
driver. The DW APB has an extra interrupt that gets raised when
writing to the LCR when busy. This explains why we need to use
dw-apb-uart driver to handle this.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
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Merge tag 'marvell-armadaxp-smp-for-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
SMP support for Armada XP
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
This patch enhances the IRQ controller driver to add support for
Inter-Processor-Interrupts that are needed to enable SMP support.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 370 and Armada XP SOCs have a power management service unit
which is responsible for powering down and waking up CPUs and other
SOC units. This patch adds support for this unit.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The mvneta driver now understands a standard 'clocks' clock pointer
property in the Device Tree nodes for the Ethernet devices, so we add
the right clock reference for the different Ethernet ports of the
Armada 370/XP SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Gregory CLEMENT