Commit Graph

6 Commits

Author SHA1 Message Date
Shobhit Kumar f1c79f16d7 drm/i915: Parameterize the Clockstop and escape_clk_div
In preparation for Generic driver

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-04-09 21:54:29 +02:00
Shobhit Kumar f6da28429a drm/i915: Parametrize the dphy and other spec specific parameters
The values of these parameters will be different for differnet panel
based on dsi rate, lane count, etc. Remove the hardcodings and make
these as parameters whch will be initialized in panel specific
sub-encoder implementaion.

This will also form groundwork for planned generic panel sub-encoder
implemntation based on VBT design enhancments to support multiple panels

v2: Mask away the port_bits before use

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-11 23:52:20 +01:00
Shobhit Kumar 1dbd7cb256 drm/i915: Reorganize the DSI enable/disable sequence
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable phase. The ULPS entry/exit
sequneces as suggested by HW team is as follows -

During enable time -
set DEVICE_READY --> Clear DEVICE_READY --> set DEVICE_READY

And during disable time to flush all FIFOs -
set ENTER_SLEEP --> EXIT_SLEEP --> ENTER_SLEEP

Also during disbale sequnece sub-encoder disable is moved to the end
after port is disabled.

v2: Based on comments from Ville
    - Detailed epxlaination in the commit messgae
    - Moved parameter changes out into another patch
    - Backlight enabling will be a new patch

v3: Updated as per Jani's comments
    - Removed the I915_WRITE_BITS as it is not needed
    - Moved panel_reset and send_otp_cmds hooks to dsi_pre_enable
    - Moved disable_panel_power hook to dsi_post_disable
    - Replace hardcoding with AFE_LATCHOUT

v4: Make intel_dsi_device_ready and intel_dsi_clear_device_ready static

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-11 23:52:19 +01:00
Shobhit Kumar b9f5e07d02 drm/i915: Add more dev ops for MIPI sub encoder
Some panels require one time programming if they do not contain their
own eeprom for basic register initialization. The sequence is

Panel Reset --> Send OTP --> Enable Pixel Stream --> Enable the panel

v2: Based on review comments from Jani and Ville
    - Updated the commit message with more details
    - Move the new parameters out of this patch

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-11 23:52:16 +01:00
ymohanma be4fc046be drm/i915: add VLV DSI PLL Calculations
v2:
 - Grab dpio_lock mutex in vlv_enable_dsi_pll().
 - Add and call vlv_disable_dsi_pll().

v3: Mostly based on Ville's review comments.
 - Only pipe A has DSI PLL lock bit.
 - Add more of CCK REG bit definitions for DSI PLL.
 - Make tables static.
 - Move clock gating out of the clock calculation functions.
 - DSI PLL LDO power gating.
 - Put alternative MNP from table calc behind #ifdef.

v4: s/CKK/CLK/ in the CCK REG bit definitions (Ville).

Signed-off-by: ymohanma <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-04 17:34:48 +02:00
Jani Nikula f5e11b06eb drm/i915: add structs for MIPI DSI output
The sub-encoder model is copied from DVO.

v2: Add attached_connector to struct intel_dsi.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-04 17:34:46 +02:00