Commit Graph

178 Commits

Author SHA1 Message Date
Arnd Bergmann bccb5d53e2 Memory controller drivers for v5.16, part two
1. Convert LPDDR2 bindings to dtschema and extend them with new
    properties.
 2. Tegra 20 EMC: support matching timings by LPDDR2 configuration from
    devicetree.
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Merge tag 'memory-controller-drv-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.16, part two

1. Convert LPDDR2 bindings to dtschema and extend them with new
   properties.
2. Tegra 20 EMC: support matching timings by LPDDR2 configuration from
   devicetree.

* tag 'memory-controller-drv-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra20-emc: Add runtime dependency on devfreq governor module
  memory: tegra20-emc: Support matching timings by LPDDR2 configuration
  memory: Add LPDDR2-info helpers
  dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node
  dt-bindings: Add vendor prefix for Elpida Memory
  dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F
  dt-bindings: memory: lpddr2: Add revision-id properties
  dt-bindings: memory: lpddr2: Convert to schema
  dt-bindings: Relocate DDR bindings

Link: https://lore.kernel.org/r/20211021093002.118192-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-21 21:34:21 +02:00
Dmitry Osipenko 14b43c20c2 memory: tegra20-emc: Add runtime dependency on devfreq governor module
Tegra20 EMC driver uses simple devfreq governor. Add simple devfreq
governor to the list of the Tegra20 EMC driver module softdeps to allow
userspace initramfs tools like dracut to automatically pull the devfreq
module into ramfs image together with the EMC module.

Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Suggested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20211019231524.888-1-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-21 11:18:08 +02:00
Dmitry Osipenko 131dd9a436 memory: tegra20-emc: Support matching timings by LPDDR2 configuration
ASUS Transformer TF101 doesn't provide RAM code and in this case memory
timings should be selected based on identity information read out from
SDRAM chip. Support matching timings by LPDDR2 configuration.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20211006224659.21434-10-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-15 09:52:47 +02:00
Kai Song 31b88d85f0 memory: tegra210-emc: replace DEFINE_SIMPLE_ATTRIBUTE with
fix debugfs_simple_attr.cocci warning:
drivers/memory/tegra/tegra210-emc-core.c:1665:0-23: WARNING:tegra210_emc_debug_min_rate_fops
should be defined with DEFINE_DEBUGFS_ATTRIBUTE

Commit 6fc5f1adf5 ("memory: tegra210-emc: replace
DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE") fixed the same
warning, but didn't fix all matches in this file at once.

Signed-off-by: Kai Song <songkai01@inspur.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20211005043514.9650-1-songkai01@inspur.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-07 20:37:33 +02:00
Yang Yingliang 982ca19a09 memory: tegra186-emc: Fix error return code in tegra186_emc_probe()
Return the error code when command fails.

Fixes: 13324edbe9 ("memory: tegra186-emc: Handle errors in BPMP response")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://lore.kernel.org/r/20210928021545.3774677-1-yangyingliang@huawei.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-07 20:32:33 +02:00
Cai Huoqing 1d8e0223bb memory: tegra: Make use of the helper function devm_add_action_or_reset()
Use devm_add_action_or_reset() instead of devm_add_action() to simplify
the error handling.

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Link: https://lore.kernel.org/r/20210922130002.586-1-caihuoqing@baidu.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-24 13:18:47 +02:00
Mikko Perttunen 13324edbe9 memory: tegra186-emc: Handle errors in BPMP response
The return value from tegra_bpmp_transfer indicates the success or
failure of the IPC transaction with BPMP. If the transaction
succeeded, we also need to check the actual command's result code.
Add code to do this.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://lore.kernel.org/r/20210915085517.1669675-3-mperttunen@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-20 10:33:28 +02:00
Dmitry Osipenko 77b14c9d05 memory: tegra: Remove interconnect state syncing hack
State syncing works properly now, previously the sync callback was never
invoked. Apparently it was fixed in drivers core, so let's remove the
hack. The state won't be synced until all consumer drivers of devices
that reference memory controller in a device-tree are probed, i.e. keeping
bandwidth at maximum until both display and devfreq drivers are probed.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210912183009.6400-1-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-20 10:32:53 +02:00
Jing Yangyang 6fc5f1adf5 memory: tegra210-emc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
Fix the following coccicheck warning:
  drivers/memory/tegra/tegra210-emc-core.c:1665:0-23:WARNING
    tegra210_emc_debug_min_rate_fops should be defined  with DEFINE_DEBUGFS_ATTRIBUTE

Signed-off-by: Jing Yangyang <jing.yangyang@zte.com.cn>
Link: https://lore.kernel.org/r/20210825063739.70260-1-deng.changcheng@zte.com.cn
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-15 09:33:58 +02:00
jing yangyang e12bc3540a memory: tegra30-emc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
Fix the following coccicheck warning:
  drivers/memory/tegra/tegra30-emc.c:1322:0-23:WARNING:
    tegra_emc_debug_max_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE

Signed-off-by: jing yangyang <jing.yangyang@zte.com.cn>
Link: https://lore.kernel.org/r/20210821035223.28282-1-jing.yangyang@zte.com.cn
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-15 09:33:05 +02:00
Colin Ian King d71b90e363 memory: tegra: make the array list static const, makes object smaller
Don't populate the array list on the stack but instead it
static const. Makes the object code smaller by 110 bytes:

Before:
   text    data     bss     dec     hex filename
  37713   21992      64   59769    e979 .../tegra/tegra210-emc-cc-r21021.o

After:
   text    data     bss     dec     hex filename
  37539   22056      64   59659    e90b .../tegra/tegra210-emc-cc-r21021.o

(gcc version 10.3.0)

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210819133155.10441-1-colin.king@canonical.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-15 09:31:19 +02:00
Arnd Bergmann eaf89f1cd3 memory: tegra: fix unused-function warning
The tegra186_mc_client_sid_override() is only called from
an #ifdef block:

drivers/memory/tegra/tegra186.c:74:13: error: 'tegra186_mc_client_sid_override' defined but not used [-Werror=unused-function]
   74 | static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Add another #ifdef around the called function.

Fixes: 393d66fd2c ("memory: tegra: Implement SID override programming")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20210722090748.1157470-1-arnd@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-07-23 08:25:34 +02:00
Dan Carpenter c7c6570326 memory: tegra: Delete dead debugfs checking code
The debugfs_create_dir() function does not return NULL, it returns error
pointers.  But in normal situations like this where the caller is not
dereferencing "emc->debugfs.root" then we are not supposed to check the
return.  So instead of fixing these checks, we should delete them.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/YMCQDTSyG8UuQoh0@mwanda
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10 09:18:15 +02:00
Thierry Reding 393d66fd2c memory: tegra: Implement SID override programming
Instead of programming all SID overrides during early boot, perform the
operation on-demand after the SMMU translations have been set up for a
device. This reuses data from device tree to match memory clients for a
device and programs the SID specified in device tree, which corresponds
to the SID used for the SMMU context banks for the device.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210603164632.1000458-2-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:50:43 +02:00
Thierry Reding 8fd9f632ba memory: tegra: Split Tegra194 data into separate file
Keep the directory structure consistent by splitting the Tegra194 data
into a separate file.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-13-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding 7191b623a2 memory: tegra: Add memory client IDs to tables
The memory client IDs will subsequently be used to program override SIDs
for the given clients depending on the device tree configuration.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-12-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding 7355c7b9ae memory: tegra: Unify drivers
The Tegra210 (and earlier) driver now supports all the functionality
that the Tegra186 (and later) driver does, so they can be unified.

Note that previously the Tegra186 (and later) driver could be unloaded,
even if that was perhaps not very useful. Older chips don't support that
yet, but once they do this code can be reenabled.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-11-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding 0de93c6985 memory: tegra: Only initialize reset controller if available
The memory controller hot resets are implemented in the BPMP on Tegra186
and later, so there's no need to provide an implementation via the
memory controller driver. Conditionally register the reset controller
only if needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-10-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding e474b3a15d memory: tegra: Make IRQ support opitonal
Make IRQ support optional to help unify the Tegra186 memory controller
driver with this one.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-9-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding 1079a66bc3 memory: tegra: Parameterize interrupt handler
Tegra20 requires a slightly different interrupt handler than Tegra30 and
later, so parameterize the handler, so that each SoC implementation can
provide its own.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-8-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding ddeceab0a9 memory: tegra: Extract setup code into callback
Separate the setup code for Tegra30 and later into a ->setup() callback
and set it for all applicable chips.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-7-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding c64738e949 memory: tegra: Make per-SoC setup more generic
The current per-SoC setup code runs at a fairly arbitrary point during
probe, thereby making it less flexible for other SoC generations. Move
the call around slightly (after only the very basic, common setup that
applies to all SoC generations has been performed), which will allow
it to be used for other implementations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-6-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding 5c9016f0a8 memory: tegra: Push suspend/resume into SoC drivers
Continuing the scheme of unification, push suspend/resume callbacks into
per-SoC driver so that they can be properly parameterized.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-5-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:41 +02:00
Thierry Reding 6cc884c1c7 memory: tegra: Introduce struct tegra_mc_ops
Subsequent patches will introduce further callbacks, so create a new
struct tegra_mc_ops to collect all of them in a single place. Move the
existing ->init() callback into the new structure.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-4-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:40 +02:00
Thierry Reding e899993845 memory: tegra: Unify struct tegra_mc across SoC generations
As another step towards unifying both the Tegra210 (and earlier) and
Tegra186 (and later) memory controller drivers, unify the structures
that are used to represent them.

Note that this comes at a slight space penalty since some fields are
not used on all generations, but the benefits of unifying the driver
outweigh the downsides.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-3-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:40 +02:00
Thierry Reding 4f1ac76e5e memory: tegra: Consolidate register fields
Subsequent patches will add more register fields to the tegra_mc_client
structure, so consolidate all register field definitions into a common
sub-structure for coherency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-2-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:49:40 +02:00
Dmitry Osipenko b4f74b59b9 memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table()
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-03 14:24:03 +02:00
Dmitry Osipenko f8c9670fff memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table()
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.

Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-03 14:24:03 +02:00
Dmitry Osipenko 56ebc9b0d7 memory: tegra: Enable compile testing for all drivers
Enable compile testing for all Tegra memory drivers.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-03 14:24:03 +02:00
Dmitry Osipenko e0740fb869 memory: tegra: Fix compilation warnings on 64bit platforms
Fix compilation warning on 64bit platforms caused by implicit promotion
of 32bit signed integer to a 64bit unsigned value which happens after
enabling compile-testing of the EMC drivers.

Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-01 13:42:53 +02:00
Dmitry Osipenko f012ade8aa memory: tegra: Print out info-level once per driver probe
Probing of EMC drivers may be deferred and in this case we get duplicated
info messages during kernel boot. Use dev_info_once() helper to silence
the duplicated messages.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210330230445.26619-7-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-04-01 19:58:22 +02:00
Dmitry Osipenko 289471984f memory: tegra20: Protect debug code with a lock
Simultaneous accesses to MC_STAT h/w shouldn't be allowed since one
collection process stomps on another. There is no good reason for
polling stats in parallel in practice, nevertheless let's add a
protection lock, just for consistency.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210323210446.24867-2-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-04-01 19:58:22 +02:00
Dmitry Osipenko 7ebb09db5b memory: tegra20: Correct comment to MC_STAT registers writes
The code was changed multiple times and the comment to MC_STAT
registers writes became slightly outdated. The MC_STAT programming
now isn't hardcoded to the "bandwidth" mode, let's clarify this in
the comment.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210323210446.24867-1-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-04-01 19:58:22 +02:00
Dmitry Osipenko fbd31f5aa6 memory: tegra20: Add debug statistics
Add debug statistics collection support. The statistics is available
via debugfs in '/sys/kernel/debug/mc/stats', it shows percent of memory
controller utilization for each memory client. This information is
intended to help with debugging of memory performance issues, it already
was proven to be useful by helping to improve memory bandwidth management
of the display driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210319130933.23261-1-digetx@gmail.com
2021-04-01 19:58:22 +02:00
Yang Li e47faa54c3 memory: tegra: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
Fix the following coccicheck warning:

  drivers/memory/tegra/tegra124-emc.c:1207:0-23: WARNING:
    tegra_emc_debug_min_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1614243958-55847-1-git-send-email-yang.lee@linux.alibaba.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-04-01 19:58:22 +02:00
Arnd Bergmann f464252181 Memory controller drivers for v5.12, part two
Two minor cleanups and one fix for compile testing (when !CONFIG_OF).
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Merge tag 'memory-controller-drv-5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.12, part two

Two minor cleanups and one fix for compile testing (when !CONFIG_OF).

* tag 'memory-controller-drv-5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
  memory: samsung: exynos5422-dmc: Correct function names in kerneldoc
  memory: ti-emif-pm: Drop of_match_ptr from of_device_id table

Link: https://lore.kernel.org/r/20210211081829.7317-1-krzk@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-11 13:48:49 +01:00
Jiapeng Chong 321b36c79c memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE
Fix the following coccicheck warning:

drivers/memory/tegra/tegra186-emc.c:158:0-23: WARNING:
  tegra186_emc_debug_max_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE.

Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Link: https://lore.kernel.org/r/1612684970-125948-1-git-send-email-jiapeng.chong@linux.alibaba.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-02-08 18:15:45 +01:00
Viresh Kumar 25d987706a memory: tegra: Remove calls to dev_pm_opp_set_clkname()
There is no point calling dev_pm_opp_set_clkname() with the "name"
parameter set to NULL, this is already done by the OPP core at setup
time and should work as it is.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/0f22cc1791d8b88c50a9790c2dc19455b34ec7b0.1611742564.git.viresh.kumar@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-29 07:59:01 +01:00
Dmitry Osipenko 6ce84ab649 memory: tegra: Check whether reset is already asserted
Check whether memory client reset is already asserted in order to prevent
DMA-flush error on trying to re-assert an already asserted reset.

This becomes a problem once PMC GENPD is enabled to use memory resets
since GENPD will get a error and fail to toggle power domain. PMC GENPDs
can't be toggled safely without holding memory reset on Tegra and we're
about to fix this.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210119235210.13006-1-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-23 00:10:40 +01:00
Dmitry Osipenko 380def2d4c memory: tegra124: Support interconnect framework
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.

Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201228154920.18846-4-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-05 18:03:22 +01:00
Dmitry Osipenko 9c56679d6f memory: tegra124-emc: Continue probing if timings are missing in device-tree
EMC driver will become mandatory after turning it into interconnect
provider because interconnect users, like display controller driver, will
fail to probe using newer device-trees that have interconnect properties.
Thus make EMC driver to probe even if timings are missing in device-tree.

Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201228154920.18846-3-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-05 18:01:23 +01:00
Dmitry Osipenko 281462e593 memory: tegra124-emc: Make driver modular
Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.

Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete callbacks. similarly to what is
done for the Tegra20/30 EMC drivers.

Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201228154920.18846-2-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-05 18:00:09 +01:00
Dmitry Osipenko d76fa3f2c2 memory: tegra30: Support interconnect framework
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS. MC driver now
supports tuning of memory arbitration latency, which needs to be done
for ISO memory clients, like a Display client for example.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201203192439.16177-4-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-12-05 14:54:36 +01:00
Dmitry Osipenko 7e04ce2a9d memory: tegra20: Support hardware versioning and clean up OPP table initialization
Support hardware versioning, which is now required for Tegra20 EMC OPP.
Clean up OPP table initialization by using a error code returned by OPP
API for judging about the OPP table presence in a device-tree and remove
OPP regulator initialization because we're now going to use power domain
instead of a raw regulator. This puts Tegra20 EMC OPP preparation on par
with the Tegra30/124 EMC drivers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201203192439.16177-3-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-12-05 14:53:59 +01:00
Nathan Chancellor 0e1bcf2c05 memory: tegra30-emc: Remove unnecessary of_node_put in tegra_emc_probe
Clang warns:

  drivers/memory/tegra/tegra30-emc.c:1275:15: warning: variable 'np' is uninitialized when used here [-Wuninitialized]
                of_node_put(np);
                            ^~
  drivers/memory/tegra/tegra30-emc.c:1269:24: note: initialize the variable 'np' to silence this warning

There does not need to be an of_node_put call in this error handling
block after the shuffling of the np assignment. Remove it so there is
no use of uninitialized memory.

Fixes: 5e00fd90183a ("memory: tegra30-emc: Continue probing if timings are missing in device-tree")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201119195244.1517236-1-natechancellor@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26 18:50:37 +01:00
Nicolin Chen 4a91b11c0a memory: tegra: Complete tegra210_swgroups
According to Tegra X1 TRM, there are missing swgroups in the
tegra210_swgroups list. So this patch adds them to the list.

Note that the TEGRA_SWGROUP_GPU (in list) should be actually
TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being
used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add
TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list)
as it is.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201008003746.25659-6-nicoleotsuka@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26 18:50:37 +01:00
Dmitry Osipenko bf25f3fcef memory: tegra30-emc: Continue probing if timings are missing in device-tree
EMC driver will become mandatory after turning it into interconnect
provider because interconnect users, like display controller driver, will
fail to probe using newer device-trees that have interconnect properties.
Thus make EMC driver to probe even if timings are missing in device-tree.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201111011456.7875-9-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26 18:50:36 +01:00
Dmitry Osipenko 0c56eda86f memory: tegra30-emc: Make driver modular
Add modularization support to the Tegra30 EMC driver, which now can be
compiled as a loadable kernel module.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201111011456.7875-8-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26 18:50:36 +01:00
Dmitry Osipenko 1d1564aabc memory: tegra30: Add FIFO sizes to memory clients
The latency allowness is calculated based on buffering capabilities of
memory clients. Add FIFO sizes to the Tegra30 memory clients.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201111011456.7875-7-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26 18:50:36 +01:00
Dmitry Osipenko dedf62d6f1 memory: tegra20-emc: Add devfreq support
Add devfreq support to the Tegra20 EMC driver. Memory utilization
statistics will be periodically polled from the memory controller and
appropriate minimum clock rate will be selected by the devfreq governor.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20201111011456.7875-5-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26 18:50:36 +01:00