Commit Graph

21 Commits

Author SHA1 Message Date
Ravikumar Kattekola d2192ea098 ARM: dts: DRA7x: Fix the bypass clock source for dpll_iva and others
Fixes: ee6c750761 (ARM: dts: dra7 clock data)

On DRA7x, For DPLL_IVA, the ref clock(CLKINP) is connected to sys_clk1 and
the bypass input(CLKINPULOW) is connected to iva_dpll_hs_clk_div clock.
But the bypass input is not directly routed to bypass clkout instead
both CLKINP and CLKINPULOW are connected to bypass clkout via a mux.

This mux is controlled by the bit - CM_CLKSEL_DPLL_IVA[23]:DPLL_BYP_CLKSEL
and it's POR value is zero which selects the CLKINP as bypass clkout.
which means iva_dpll_hs_clk_div is not the bypass clock for dpll_iva_ck

Fix this by adding another mux clock as parent in bypass mode.

This design is common to most of the PLLs and the rest have only one bypass
clock. Below is a list of the DPLLs that need this fix:

DPLL_IVA, DPLL_DDR,
DPLL_DSP, DPLL_EVE,
DPLL_GMAC, DPLL_PER,
DPLL_USB and DPLL_CORE

Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-03-06 08:34:21 -08:00
Tomi Valkeinen e671538d51 ARM: dts: dra7: fix DSS PLL clock mux registers
The clock nodes for DSS VIDEO1/2 and HDMI have wrong register addresses.
This patch fixes the addresses so that they point to
CM_CLKSEL_VIDEO1_PLL_SYS, CM_CLKSEL_VIDEO2_PLL_SYS and
CM_CLKSEL_HDMI_PLL_SYS.

Reported-by: Somnath Mukherjee <somnath@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-14 10:28:33 -08:00
Olof Johansson 730346236a arm: Xilinx Zynq dt patches for v3.17
- Document and use new cadence serial binding
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Merge tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx into next/dt

Merge "Xilinx Zynq changes for v3.17" from Michal Simek:

arm: Xilinx Zynq dt patches for v3.17

- Document and use new cadence serial binding

* tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx:
  ARM: zynq: DT: Migrate UART to Cadence binding
  tty: cadence: Document DT binding
  + Linux 3.16-rc5

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-19 12:16:34 -07:00
Olof Johansson 412a9bbd12 First set of .dts changes for omaps for v3.17 merge
window:
 
 - Enable irqchip crossbar interrupt mapping. These changes
   are based on an immutable irqchip branch set up by Jason
   Cooper to make it easier to merge the related .dts changes.
 
 - Removal of omap2 related static clock data that now comes
   from device tree.
 
 - Enabling of PHY regulators for various omaps
 
 - Enabling of PCIe for dra7
 
 - Add support for am437x starterkit
 
 - Enable audio for for omap5
 
 - Enable display and am335x-evmsk
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Merge tag 'omap-for-v3.17/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Merge "omap dts changes for v3.17 merge window, part1" from Tony Lindgren:

First set of .dts changes for omaps for v3.17 merge window:

- Enable irqchip crossbar interrupt mapping. These changes
  are based on an immutable irqchip branch set up by Jason
  Cooper to make it easier to merge the related .dts changes.

- Removal of omap2 related static clock data that now comes
  from device tree.

- Enabling of PHY regulators for various omaps

- Enabling of PCIe for dra7

- Add support for am437x starterkit

- Enable audio for for omap5

- Enable display and am335x-evmsk

* tag 'omap-for-v3.17/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (43 commits)
  ARM: DTS: omap5-uevm: Enable basic audio (McPDM <-> twl6040)
  ARM: DTS: omap5-uevm: Add node for twl6040 audio codec
  ARM: DTS: omap5-uevm: Enable palmas clk32kgaudio clock
  ARM: dts: dra7: Add dt data for PCIe controller
  ARM: dts: dra7: Add dt data for PCIe PHY
  ARM: dts: dra7: Add dt data for PCIe PHY control module
  ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
  ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
  ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
  ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
  ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock
  ARM: dts: dra7-evm: Add regulator information to USB2 PHYs
  ARM: omap2plus_defconfig: enable TPS65218 configs
  ARM: dts: AM437x: Add TPS65218 device tree nodes
  ARM: dts: AM437x: Fix i2c nodes indentation
  ARM: dts: AM43x: Add TPS65218 device tree nodes
  ARM: dts: Add devicetree for Gumstix Pepper board
  ARM: dts: dra7: add crossbar device binding
  ARM: dts: dra7: add routable-irqs property for gic node
  ARM: OMAP24xx: clock: remove legacy clock data
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-18 22:16:48 -07:00
Kishon Vijay Abraham I 00b0af5b68 ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-15 00:16:12 -07:00
Kishon Vijay Abraham I b700f42c86 ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-15 00:16:11 -07:00
Kishon Vijay Abraham I ba5137b272 ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-15 00:16:11 -07:00
Keerthy 4310e90847 ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.

Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
shows the signal name for the output of post divider (M2) is CLKOUTLDO.

Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as
input to apll mux.

So the actual output of dpll is dpll_pcie_ref_m2ldo_ck which is also the input
of apll.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-15 00:16:10 -07:00
Keerthy 147e541369 ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock
Add divider table to optfclk_pciephy_div clock. The 8th bit of
CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1
based on if the divider value is 0x2 or 0x1.

Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the
block diagram of Clock Generator Subsystem of PCIe PHY module. The divider
value if '1' should be programmed in order to get the correct
PCIE_PHY_DIV_GCLK frequency (2.5GHz).

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-15 00:16:09 -07:00
Tony Lindgren e9360979fe Merge branch 'for-v3.16-rc/clk-dt-fixes' of https://github.com/t-kristo/linux-pm into fixes-rc4 2014-07-07 05:05:42 -07:00
Rajendra Nayak dd94324b98 ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates
Without the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
532000000

With the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
266000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
133000000

The l3 clock derived from core DPLL is actually a divider clock,
with the default divider set to 2. l4 then derived from l3 is a fixed factor
clock, but the fixed divider is 2 and not 1. Which means the l3 clock is
half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch)

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-03 20:59:36 +03:00
Peter Ujfalusi 2ca0945fc1 ARM: DTS: dra7/dra7xx-clocks: ATL related changes
Modify the clock nodes for the ATL clocks to use the ATL clock driver to
handle them.

Add the ATL device node at the same time for DRA7.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-06-16 07:12:10 -07:00
Mike Turquette 3f6eec9969 Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-next 2014-06-10 16:53:25 -07:00
Nishanth Menon 7e14807000 ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies
OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle
Correction(DCC) to operate safely at frequencies >= 1.4GHz.

Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides
this support.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-06-06 20:33:40 +03:00
Peter Ujfalusi 0cccd91900 ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock
To allign the name with the other atl clock names:
atlclkin3_ck -> atl_clkin3_ck

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-28 13:06:50 +03:00
Roger Quadros 032d774575 ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
This clock gate description is missing in the older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.

Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL

Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.

CC: Benoît Cousson <bcousson@baylibre.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-05-14 14:39:34 -07:00
Peter Ujfalusi 8c0b4fd89e ARM: dts: dra7xx-clocks: Correct mcasp2_ahclkx_mux bit-shift
The correct bit is 24 for AHCLKX.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-04-18 15:53:33 -07:00
J Keerthy a0289f9174 ARM: dts: DRA7: Add PCIe related clock nodes
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-17 12:36:31 -08:00
J Keerthy c3be7acdeb ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock
This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-17 12:36:27 -08:00
J Keerthy 7d138d3aaf ARM: dts: clk: Add apll related clocks
The patch adds a mux node to choose the parent of apll_pcie_ck node.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-17 12:36:23 -08:00
Tero Kristo ee6c750761 ARM: dts: dra7 clock data
This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-17 12:36:04 -08:00