Commit Graph

310 Commits

Author SHA1 Message Date
Linus Torvalds c1c76700a0 SPDX changes for 6.0-rc1
Here is the set of SPDX comment updates for 6.0-rc1.
 
 Nothing huge here, just a number of updated SPDX license tags and
 cleanups based on the review of a number of common patterns in GPLv2
 boilerplate text.  Also included in here are a few other minor updates,
 2 USB files, and one Documentation file update to get the SPDX lines
 correct.
 
 All of these have been in the linux-next tree for a very long time.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCYupz3g8cZ3JlZ0Brcm9h
 aC5jb20ACgkQMUfUDdst+ynPUgCgslaf2ssCgW5IeuXbhla+ZBRAzisAnjVgOvLN
 4AKdqbiBNlFbCroQwmeQ
 =v1sg
 -----END PGP SIGNATURE-----

Merge tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx

Pull SPDX updates from Greg KH:
 "Here is the set of SPDX comment updates for 6.0-rc1.

  Nothing huge here, just a number of updated SPDX license tags and
  cleanups based on the review of a number of common patterns in GPLv2
  boilerplate text.

  Also included in here are a few other minor updates, two USB files,
  and one Documentation file update to get the SPDX lines correct.

  All of these have been in the linux-next tree for a very long time"

* tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx: (28 commits)
  Documentation: samsung-s3c24xx: Add blank line after SPDX directive
  x86/crypto: Remove stray comment terminator
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_406.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_398.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_391.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_390.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_385.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_319.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_298.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_292.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_179.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 2)
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 1)
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_160.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_152.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_149.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_147.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_133.RULE
  ...
2022-08-04 12:12:54 -07:00
Moudy Ho e5758850c2 soc: mediatek: mutex: add functions that operate registers by CMDQ
Due to HW limitations, MDP3 is necessary to enable MUTEX in each frame
for SOF triggering and cooperate with CMDQ control to reduce the amount
of interrupts generated(also, reduce frame latency).

In response to the above situation, a new interface
"mtk_mutex_enable_by_cmdq" has been added to achieve the purpose.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Link: https://lore.kernel.org/r/20220610063424.7800-7-moudy.ho@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17 15:51:52 +02:00
Moudy Ho d0804085c5 soc: mediatek: mutex: add common interface for modules setting
In order to allow multiple modules to operate MUTEX hardware through
a common interfrace, two flexible indexes "mtk_mutex_mod_index" and
"mtk_mutex_sof_index" need to be added to replace original component
ID so that like DDP and MDP can add their own MOD table or SOF
settings independently.

In addition, 2 generic interface "mtk_mutex_write_mod" and
"mtk_mutex_write_sof" have been added, which is expected to replace
the "mtk_mutex_add_comp" and "mtk_mutex_remove_comp" pair originally
dedicated to DDP in the future.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Link: https://lore.kernel.org/r/20220610063424.7800-2-moudy.ho@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17 15:51:51 +02:00
Thomas Gleixner 5a729246e5 treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE
Based on the normalized pattern:

    this program is free software you can redistribute it and/or modify it
    under the terms of the gnu general public license version 2 as
    published by the free software foundation  this program is distributed
    as is without any warranty of any kind whether express or implied
    without even the implied warranty of merchantability or fitness for a
    particular purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

has been chosen to replace the boilerplate/reference.

Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10 14:51:36 +02:00
Thomas Gleixner 2aec85b26f treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 2)
Based on the normalized pattern:

    this program is free software you can redistribute it and/or modify it
    under the terms of the gnu general public license as published by the
    free software foundation version 2  this program is distributed as is
    without any warranty of any kind whether express or implied without
    even the implied warranty of merchantability or fitness for a
    particular purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

has been chosen to replace the boilerplate/reference.

Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10 14:51:35 +02:00
Linus Torvalds 96479c0980 ARM: multiplatform changes, part 2
The second part of the multiplatform changes now converts the
 Intel/Marvell PXA platform along with the rest. The patches went through
 several rebases before the merge window as bugs were found, so they
 remained separate.
 
 This has to touch a lot of drivers, in particular the touchscreen,
 pcmcia, sound and clk bits, to detach the driver files from the
 platform and board specific header files.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKZKqsACgkQmmx57+YA
 GNnO/w//dgJBlkmoIIKlG2eJsvoUKwDt7MuLEMCqSqYYUSvMENFwKK66INMDIJ3l
 PmKf94JadlpBm2OB2vzW+D1EtaLGX9eXZkKD+vyB1I1yFkKdzEPcAfitfrRwe58E
 pR4nQd/jVL4UCY+pp442O1q9VvMpMV9P4ILJGPS/PpsD5CT9Gn8m9svIIuNuDRFd
 nwpyZC3l32jVLo9iuLmwZUvxtOWI3hTqZrnxhByBhlvtnGexRsq/VhfubK2uzBi1
 CyWHjqzOSmseGmsUDwv9LFqVV9YRCeisS3IElA5L0VgM0XvHKA+f9qyF7V6zI20g
 y9LtqhdAtiTpE/aUrOW2LDYaM/bc7RilYZrWchoZbCEsHhV4C+ld3QoTyxvGscvG
 tbznhvZKdUNX8LHS0J9NqIj1q1YGN5ei5r/C5R8DBj1q8VcTVnq3dms8xzVTd35o
 xS5BbLFliiI96jc7S6LaQizXheYjAfdPhmXUAxNXvWIVQ6SXnf8/U/RB9Zzjb8hm
 FH2Gu8m/Dh2MHKBBRWSVw8VahV0V7WiEaWeYuwwTbW1wUrsWiizVaPnqrt6Cq9DW
 oJZgBvktWEXUQz73qrnvwo9GjcKqAxaWKWq05hHKHKuLGezsPAyIhIKr51V2xqqw
 cp2OIMCsN5GYENOhHvt6BMRAI5iA4VyFDtWAqw9B6EIwno6N7Z4=
 =cnSb
 -----END PGP SIGNATURE-----

Merge tag 'arm-multiplatform-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull more ARM multiplatform updates from Arnd Bergmann:
 "The second part of the multiplatform changes now converts the
  Intel/Marvell PXA platform along with the rest. The patches went
  through several rebases before the merge window as bugs were found, so
  they remained separate.

  This has to touch a lot of drivers, in particular the touchscreen,
  pcmcia, sound and clk bits, to detach the driver files from the
  platform and board specific header files"

* tag 'arm-multiplatform-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (48 commits)
  ARM: pxa/mmp: remove traces of plat-pxa
  ARM: pxa: convert to multiplatform
  ARM: pxa/sa1100: move I/O space to PCI_IOBASE
  ARM: pxa: remove support for MTD_XIP
  ARM: pxa: move mach/*.h to mach-pxa/
  ARM: PXA: fix multi-cpu build of xsc3
  ARM: pxa: move plat-pxa to drivers/soc/
  ARM: mmp: rename pxa_register_device
  ARM: mmp: remove tavorevb board support
  ARM: pxa: remove unused mach/bitfield.h
  ARM: pxa: move clk register definitions to driver
  ARM: pxa: move smemc register access from clk to platform
  cpufreq: pxa3: move clk register access to clk driver
  ARM: pxa: remove get_clk_frequency_khz()
  ARM: pxa: pcmcia: move smemc configuration back to arch
  ASoC: pxa: i2s: use normal MMIO accessors
  ASoC: pxa: ac97: use normal MMIO accessors
  ASoC: pxa: use pdev resource for FIFO regs
  Input: wm97xx - get rid of irq_enable method in wm97xx_mach_ops
  Input: wm97xx - switch to using threaded IRQ
  ...
2022-06-02 15:23:54 -07:00
Linus Torvalds b00ed48bb0 dmaengine updates for v5.19-rc1
New support:
  - Tegra gpcdma Driver support
  - Qualcomm SM8350, Sm8450 and SC7280 Device support
  - Renesas RZN1 dma and platform support
 
  Updates:
  - stm32 device pause/resume support and updates
  - DMA memset ops Documentation and usage clarification
  - Deprecate '#dma-channels' & '#dma-requests' bindings
  - Driver updates for stm32, ptdma idsx etc
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmKTr5oACgkQfBQHDyUj
 g0ePBw//UP+A+PPvTdQdlq/spO9Hb76lB1UZ7x7nVsObovyO2hxQl61b5Xo9o8eH
 0VIIVB9OU4ysp8eX5Y6m7CUFKa/4MyUSU1HKdspseoap3JKg1EAHEGdhjR++V/dF
 mqPN7VvmTbW8YDQ6b7Xz/mZedxOSJZL+wltCT2AQGLV1PD+BPZyBfkPl9NarpaX6
 OeKatnMiJlZwFjQeVijiqCUx0xZV0G1XfQJDIEzRaBBvYAiHYTjbPUBZVsu5BjoC
 70HtxhDKHJu0JFPa91gm7rqhj8XTKFoIGQU7jZqlpgr1IoYvfnotHoQeURa3yviZ
 lZ6oW0+Y3RKyCcMH5iir2YEGdeaDXEPRb1YS/rz1vcf9b8JNqxXuM9i8Z2EXCVjd
 qVxC9HzVCBh5EHuJGi1DFoHMrw/NXUanbWqW8C0FzqqTcqvp6DceAgzqcd1FJjwl
 lgZM7Y5r0WXMzbbhOeOQP34ps+mY17rsBn210K/H75fZW8kTsdwiCOL4VlaK1p/z
 CCJPYXkxEChbrIYoshXNTqg61bt9F2sEgJ+7FFUbUUOTLlQKFJUZ7fuoU896rDto
 GndspWpxaslgAzdPuWSKBeR+b9IubgLgKF1BKSTYR6coyUt+hRJFiAx1juAOYbHe
 CrJat0luP+hELgt1f2TjyYYZFj9Wc84tnqI+ThzXK0GyEN4Ax1c=
 =ANxH
 -----END PGP SIGNATURE-----

Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine

Pull dmaengine updates from Vinod Koul:
 "Nothing special, this includes a couple of new device support and new
  driver support and bunch of driver updates.

  New support:

   - Tegra gpcdma driver support

   - Qualcomm SM8350, Sm8450 and SC7280 device support

   - Renesas RZN1 dma and platform support

  Updates:

   - stm32 device pause/resume support and updates

   - DMA memset ops Documentation and usage clarification

   - deprecate '#dma-channels' & '#dma-requests' bindings

   - driver updates for stm32, ptdma idsx etc"

* tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (87 commits)
  dmaengine: idxd: make idxd_wq_enable() return 0 if wq is already enabled
  dmaengine: sun6i: Add support for the D1 variant
  dmaengine: sun6i: Add support for 34-bit physical addresses
  dmaengine: sun6i: Do not use virt_to_phys
  dt-bindings: dma: sun50i-a64: Add compatible for D1
  dmaengine: tegra: Remove unused switch case
  dmaengine: tegra: Fix uninitialized variable usage
  dmaengine: stm32-dma: add device_pause/device_resume support
  dmaengine: stm32-dma: rename pm ops before dma pause/resume introduction
  dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done()
  dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage chan->next_sg
  dmaengine: stm32-dmamux: avoid reset of dmamux if used by coprocessor
  dmaengine: qcom: gpi: Add support for sc7280
  dt-bindings: dma: pl330: Add power-domains
  dmaengine: stm32-mdma: use dev_dbg on non-busy channel spurious it
  dmaengine: stm32-mdma: fix chan initialization in stm32_mdma_irq_handler()
  dmaengine: stm32-mdma: remove GISR1 register
  dmaengine: ti: deprecate '#dma-channels'
  dmaengine: mmp: deprecate '#dma-channels'
  dmaengine: pxa: deprecate '#dma-channels' and '#dma-requests'
  ...
2022-05-29 11:38:27 -07:00
Linus Torvalds ecf0aa5317 ARM: ARMv4T/v5 multiplatform support for v5.19, part 1
This series has been 12 years in the making, it mostly finishes the
 work that was started with the founding of Linaro to clean up platform
 support in the kernel.
 
 The largest change here is a cleanup of the omap1 platform, which
 is the final ARM machine type to get converted to the common-clk
 subsystem. All the omap1 specific drivers are now made independent of the
 mach/*.h headers to allow the platform to be part of a generic ARMv4/v5
 multiplatform kernel. The last bit that enables this support is still
 missing here while we wait for some last dependencies to make it into
 the mainline kernel through other subsystems.
 
 The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost
 at the point of allowing multiplatform kernels, this work gets completed
 here along with a few additional cleanup.  At the same time, the s3c24xx
 and s3c64xx are now deprecated and expected to get removed in the future.
 
 The PXA and OMAP1 bits are in a separate branch because of dependencies.
 Once both branches are merged, only the three Intel StrongARM platforms
 (RiscPC, Footbridge/NetWinder and StrongARM1100) need separate kernels,
 and there are no plans to include these.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKOP3sACgkQmmx57+YA
 GNk+DhAAmrPNuS8JDlCRPa76Nd9PC9aitnnEGYytQ6bgwexKd3qdvP7gdUtr7jlV
 8k4KiGnnZZjEGd4i5cAVhSCyBbCt4oPKhato62KneEsO19xLsVmmTpQg1LPK75do
 mHYKpc+6932Lp6WrtI1F75id0phx684tpZp9P4ggXwMwgYkagq9rcO+mGUNZWDc8
 D9SdAmoObtSCoBCYYbq2VhAPA79mSKKVpLGehzd+Gq5cuf/jJQD0u1E00izkdyZc
 r/5acQ7PHQlVXqSONYgCpkvDTqmjg9cvVCKeKLpFspV3f6vBVRgV60UGfwhpdPHY
 N119KUJtPf81xnLSxsqBFA34LMSerrH72YM5cYupKiiYcTDr+Yw6zrtNR6ktkt/B
 F1Tc/QV+A9CGergxljy39G1smEuwKtNiVA//NSlUORCHxgwa5XUB0mQIzNcWARa4
 oMDLhBF7ES211CB7Yto2FR6gBQbh2A9HSpjOh6kxdHrRb4FCgoXjPhzBoMxPoSFu
 XIzJpMb18K4bI+hKRYddEOK5V0kHt9mzT7ViGT/2+n13IHKIGmKrZxwDH7mohAW9
 4GF77gGbQsE9szajkx5EG1t+PWextQeeMyYW05bXO/mbDwA0n7EdjGpBeedvTZw3
 6gUWVahfYp9hZWPdxJ4fbGnlbSovCq0y4tj5fbZHPh6AOAtmvWY=
 =CTtN
 -----END PGP SIGNATURE-----

Merge tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARMv4T/v5 multiplatform support from Arnd Bergmann:
 "This series has been 12 years in the making, it mostly finishes the
  work that was started with the founding of Linaro to clean up platform
  support in the kernel.

  The largest change here is a cleanup of the omap1 platform, which is
  the final ARM machine type to get converted to the common-clk
  subsystem. All the omap1 specific drivers are now made independent of
  the mach/*.h headers to allow the platform to be part of a generic
  ARMv4/v5 multiplatform kernel.

  The last bit that enables this support is still missing here while we
  wait for some last dependencies to make it into the mainline kernel
  through other subsystems.

  The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost
  at the point of allowing multiplatform kernels, this work gets
  completed here along with a few additional cleanup. At the same time,
  the s3c24xx and s3c64xx are now deprecated and expected to get removed
  in the future.

  The PXA and OMAP1 bits are in a separate branch because of
  dependencies. Once both branches are merged, only the three Intel
  StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100)
  need separate kernels, and there are no plans to include these"

* tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits)
  ARM: ixp4xx: Consolidate Kconfig fixing issue
  ARM: versatile: Add missing of_node_put in dcscb_init
  ARM: config: Refresh IXP4xx config after multiplatform
  ARM: omap1: add back omap_set_dma_priority() stub
  ARM: omap: fix missing declaration warnings
  ARM: omap: fix address space warnings from sparse
  ARM: spear: remove include/mach/ subdirectory
  ARM: davinci: remove include/mach/ subdirectory
  ARM: omap2: remove include/mach/ subdirectory
  integrator: remove empty ap_init_early()
  ARM: s3c: fix include path
  MAINTAINERS: omap1: Add Janusz as an additional maintainer
  ARM: omap1: htc_herald: fix typos in comments
  ARM: OMAP1: fix typos in comments
  ARM: OMAP1: clock: Remove noop code
  ARM: OMAP1: clock: Remove unused code
  ARM: OMAP1: clock: Fix UART rate reporting algorithm
  ARM: OMAP1: clock: Fix early UART rate issues
  ARM: OMAP1: Prepare for conversion of OMAP1 clocks to CCF
  ARM: omap1: fix build with no SoC selected
  ...
2022-05-26 10:43:09 -07:00
Linus Torvalds cc3c470ae4 ARM: driver changes for 5.19
There are minor updates to SoC specific drivers for chips by Rockchip,
 Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy
 driver changes include:
 
 - Several conversions of DT bindings to yaml format.
 
 - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
 
 - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
   and support for more chips in the RPMh power domains and the soc-id.
 
 - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
 
 - Apple M1 gains support for the on-chip NVMe controller, making it
   possible to finally use the internal disks. This also includes SoC
   drivers for their RTKit IPC and for the SART DMA address filter.
 
 For other subsystems that merge their drivers through the SoC tree,
 we have
 
 - Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
   SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
   now has a cache for firmware argument structures as an optimization,
   and SCMI now supports the 3.1 version of the specification.
 
 - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers
 
 - Memory controller updates for Tegra, and a few updates for other
   platforms.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKOXOoACgkQmmx57+YA
 GNlpVQ//eQGfL0WktE5G/y0mCVuVHtXT5nSjHMgjTOdb9+QvaATCfxnLXvP7Gq7C
 7YzJd68G+2ZC4rUkkjTxyMICT7eIrJSAIAFn4PWee4EQ5DfbHgG+1tToTjxqb+QQ
 6wGB5MVaYUhjZE30kY2E8a+OKxHtEnkt9wcch6ei0vzsMZquQJF6byfHd5+I4Knd
 CyDmXX8ZGXK3FnhvuBLr3Rgwyhs0X4Ju7UaONLZxBYxdnh8WmymRszmMnv5qEkub
 KDe8fbhFamOT3Z55JdCA5xq7LvUzjsKpTGFxFcS0ptbkTmtAsuyYqqiWvAPx3D5u
 5TxVGSx9QKid6fpIsITZ2ptO6fgljh1W9b/3Y3/eltudXsM1qqSxyN2Hre+M9egf
 WEDADqbNR5Y5+bq1iZWI348jXkNHVPpsLHI9Ihqf4yyrKwFkmRmNLnws53XTAPH2
 FPXZvJjwFDBDHGfewSoLFePXUPNytVLXbr6Mq72ZyTDIBDU8Mxh666Wd8bu4tgbG
 1Y2pMjDIdXDOsljM6Of5D3XjM1kuDwEmFxWGy+cKLgoEbHLeE1xIbTjUir4687+d
 VNHdtsIRFPRZzz2lUSmI8vlA2aewMWrkOF/Ulz8xh6gG8uitMSfOxghg4IWOfRVM
 mlvgFP5eqTInmQcbWRxaRO9JzP+rPp1sAcEpsBmuEHw5Akflbc8=
 =XoLF
 -----END PGP SIGNATURE-----

Merge tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM driver updates from Arnd Bergmann:
 "There are minor updates to SoC specific drivers for chips by Rockchip,
  Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom.

  Noteworthy driver changes include:

   - Several conversions of DT bindings to yaml format.

   - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.

   - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
     and support for more chips in the RPMh power domains and the
     soc-id.

   - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.

   - Apple M1 gains support for the on-chip NVMe controller, making it
     possible to finally use the internal disks. This also includes SoC
     drivers for their RTKit IPC and for the SART DMA address filter.

  For other subsystems that merge their drivers through the SoC tree, we
  have

   - Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
     SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
     now has a cache for firmware argument structures as an
     optimization, and SCMI now supports the 3.1 version of the
     specification.

   - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI
     drivers

   - Memory controller updates for Tegra, and a few updates for other
     platforms"

* tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits)
  memory: tegra: Add MC error logging on Tegra186 onward
  memory: tegra: Add memory controller channels support
  memory: tegra: Add APE memory clients for Tegra234
  memory: tegra: Add Tegra234 support
  nvme-apple: fix sparse endianess warnings
  soc/tegra: pmc: Document core domain fields
  soc: qcom: pdr: use static for servreg_* variables
  soc: imx: fix semicolon.cocci warnings
  soc: renesas: R-Car V3U is R-Car Gen4
  soc: imx: add i.MX8MP HDMI blk-ctrl
  soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
  soc: imx: add i.MX8MP HSIO blk-ctrl
  soc: imx: imx8m-blk-ctrl: set power device name
  soc: qcom: llcc: Add sc8180x and sc8280xp configurations
  dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
  soc/tegra: pmc: Select REGMAP
  dt-bindings: reset: st,sti-powerdown: Convert to yaml
  dt-bindings: reset: st,sti-picophyreset: Convert to yaml
  dt-bindings: reset: socfpga: Convert to yaml
  dt-bindings: reset: snps,axs10x-reset: Convert to yaml
  ...
2022-05-26 10:32:47 -07:00
Linus Torvalds c011dd537f ARM: updates for 32-bit SoCs
These updates are for platform specific code in arch/arm/, mostly fixing
 minor issues. The at91 platform gains support for better power
 management on the lan966 platform and new firmware on the sama5
 platform. The mediatek soc drivers in turn are enabled for the new
 mt8195 SoC.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKORHMACgkQmmx57+YA
 GNnKYA//QhTTZePOMqHZHBVU4dqJuHrjd+rwME5u7a6hqSe3VYaFao6LF+P5fAzR
 IWk8svgCJLIdRx4tnA+kE7LIBsJoPwXYxhGUlgM5CfrxYClQuofnWP58Z+EbIAXx
 VIboLBW1Anw5y7zw+0JkB01DMuGzDDFnUJ4Y+0M3aW3VGC8wJXc+dM+t8BWOn7OW
 DNTcXfJgkRJBtzT++tMU4Z7Kmn//i4xohuT7dwJW4vvIfTL350Bl5Z1EHGnScfMk
 HgbJD5iF7Z12jj7ureuWengr/MN1eAPs18ZdWRcmo4Ie5IDWB50dMoYifjp/tslO
 oXRODrGCuX9yOjcjleGU1mAbb7zqoaThZcbI0yjVOaVwyU0fQR9NFJTqmSEEX97p
 LPZHU1CtAjRns7BW3ons9wPhy4s1xSPopJaHiXDwMMzAlx+kTcoFlFFvWCSlrcOC
 MMo+eN1BQ3SbIxi3Ji3p6MnmSLIiE/wq4nKCEagKAv+AjtqRXYDIsT+28A96Xgeo
 1R5agDamDMp0h6ZrhHMGSIgppWe+qvX14Jp3Hw0Nocgdyf8ABDR9H3/gZasXKbZu
 LrbNLn3vNVKTMn9YpM0T94Uwf0nFPH6MOzFVmjahRute3TU7ioSXxbVPpNuiOkXj
 RFXe1YUoILjLJgHZSUEpdHP+meGUjeScHTQt6jV97WfTeq2ZALg=
 =Eoh1
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull 32-bit ARM SoC updates from Arnd Bergmann:
 "These updates are for platform specific code in arch/arm/, mostly
  fixing minor issues.

  The at91 platform gains support for better power management on the
  lan966 platform and new firmware on the sama5 platform. The mediatek
  soc drivers in turn are enabled for the new mt8195 SoC"

* tag 'arm-soc-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (34 commits)
  ARM: at91: debug: add lan966 support
  ARM: at91: pm: add support for sama5d2 secure suspend
  ARM: at91: add code to handle secure calls
  ARM: at91: Kconfig: implement PIT64B selection
  ARM: at91: pm: add quirks for pm
  ARM: at91: pm: use kernel documentation style
  ARM: at91: pm: introduce macros for pm mode replacement
  ARM: at91: pm: keep documentation inline with structure members
  orion5x: fix typos in comments
  ARM: hisi: Add missing of_node_put after of_find_compatible_node
  ARM: shmobile: rcar-gen2: Drop comma after OF match table sentinel
  ARM: shmobile: Drop commas after dt_compat sentinels
  soc: mediatek: mutex: remove mt8195 MOD0 and SOF0 definition
  MAINTAINERS: Add Broadcom BCMBCA entry
  arm: bcmbca: add arch bcmbca machine entry
  MAINTAINERS: Broadcom internal lists aren't maintainers
  dt-bindings: pwrap: mediatek: Update pwrap document for mt8195
  soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  ...
2022-05-26 10:25:22 -07:00
Miquel Raynal 885525c1e7 clk: renesas: r9a06g032: Export function to set dmamux
The dmamux register is located within the system controller.

Without syscon, we need an extra helper in order to give write access to
this register to a dmamux driver.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220427095653.91804-5-miquel.raynal@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-05-19 22:34:51 +05:30
Arnd Bergmann 3f656f2618 Qualcomm driver updates for v5.19
This converts a wide range of Qualcomm-related DeviceTree bindings to
 YAML, in order to improve our ability to validate the DeviceTree source.
 
 The RPMh power-domain driver gains support for the modem platform SDX65,
 the compute platform SC8280XP and the automotive platform SA8540p. While
 LLCC gains support for SC8180X and SC8280XP and gains a
 MODULE_DEVICE_TABLE() to make it functional as a module.
 
 It adds a driver for configuring the SSC bus, providing Linux access to
 the hardware blocks in the sensor subsystem.
 
 The socinfo driver gets confusion related to MSM8974 Pro sorted out and
 adds new ids for SM8540 and SC7280.
 
 The SCM driver gains support for MSM8974.
 
 Add missing of_node_put() in smp2p and smsm drivers.
 Stop using iterator after list_for_each_entry() and define static
 definitions as such, in the PDR driver.
 -----BEGIN PGP SIGNATURE-----
 
 iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmJ5WsYbHGJqb3JuLmFu
 ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FIo8P+wcc78TQQuG67nqPr2gb
 QFqVK8U2mz07XW0H1rnGZKsTSrZxFs/YWRBaw+dYC5OZVJHx/uoZM04Njsyy/DFh
 UaNQgTgsS4+D5+butveh4lBdmk4ja5sreLHw25/azw5VBzeHb9+4HeAd7QMMQ+BO
 /EvIlykPwsgGIZwabzDHkY8w/xt64CPiajps1qGlFDJedSLsdJ8bKHctvcFD03v3
 3utJku3jAc5SZMBQgDttpPwpn7UnHXjCvWxyz8oSFaWDQBROztH0FbiJsZnjMuFI
 9RfRqblgb2PkvaG23W7jv68aJf3yQ6siY8ezPPs3/1F6T6tMQaAKEhwrY93ZQiWc
 gDDx33TvX3YJiRRdC2Gvg1QpL4xMFUERR8o4ooQ0t+b8bG6TkGP44VVg3/n1wrMK
 Q5xdgDigfrNnVZV1b2flQHc4qke4hNoV23SQ7iFWvtSJO09xklVJhXFGQ6mthEkb
 PnBFurLyxglKw6afs1/2P8tplS52K0l19lgNJu6vtUzC6fMOg50cX0mmWP8+rkFb
 njhXlPqCDataECZazyxnn7KORAn3E7zQceJ/LJeV+XZ9i5DJLXup+JkuBCWem4Nd
 ucEeYtQVRel5FCWZZzkXviPCTlWgTB7ya7pJPCzvZpnNFHeSWSjr9YK6xtWwy9rP
 CBRXYrz2gJLV/MGkB1piAwkm
 =/Dqp
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJ5hB4ACgkQmmx57+YA
 GNksBxAAj09+d2U1sFSJl3HiHTrXyg3MYoG0dA1QK2CRKucdwMf6KBGpEHTQyL6a
 Iqan6URrTqEM3WP4suBsZh8vbv1C8u7KGWwDAMqJ18BkigoGHEV1PyvmHYRvPoT2
 6DSHAkGbYfDglxXZ4JcxNaQk3+t6rZpe5LcRRgQ7JpoKfzlqKxfSJfPFLzYAvhSV
 qThiyd3GvfcgkVHL9noh4BrBrnNRj7wMzUwQnhW5aWebN+DqgG8zlzmmZEQx61uR
 sjMogRZNpGXVAR+4yvPZNoxTGM0plssxlkDQGS4b0XLP1t7ohr22eFPTrWqcsYCi
 h4fa3nXxUIoTDJXQ7nmU04VXp5xVUtQKKe+zXIvQBT98OkM1f6ep5i7rrEh5DZxJ
 TWVdRLuIVpHVsVARqq+qpEnwyDeiF3Hgmope3xPYhEIs1WcIOQzWBjHbNTNeiFdy
 fQMrmAQjirXJBV18ImRSMcAXW+Shc72vnj6fViQcrL5Pzj1HJFMjh/bpPzAhIUYJ
 w9to8mpNgHUpMwnkfMUqQDV6FANVbYPqancK/z4rEPd8mj6bq1z2GEQq2e9+cAfM
 imyD30+g7fm7e4mxp53mv/oxqf4NJExE0eIjXAQY53at0TCk+ngsxJd96Wz3aIpB
 eL9YN5x+y6vXkFC+hsnX2/QdUiVCmfpbrez2QqzoZncSkJ4mjdI=
 =rjVH
 -----END PGP SIGNATURE-----

Merge tag 'qcom-drivers-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.19

This converts a wide range of Qualcomm-related DeviceTree bindings to
YAML, in order to improve our ability to validate the DeviceTree source.

The RPMh power-domain driver gains support for the modem platform SDX65,
the compute platform SC8280XP and the automotive platform SA8540p. While
LLCC gains support for SC8180X and SC8280XP and gains a
MODULE_DEVICE_TABLE() to make it functional as a module.

It adds a driver for configuring the SSC bus, providing Linux access to
the hardware blocks in the sensor subsystem.

The socinfo driver gets confusion related to MSM8974 Pro sorted out and
adds new ids for SM8540 and SC7280.

The SCM driver gains support for MSM8974.

Add missing of_node_put() in smp2p and smsm drivers.
Stop using iterator after list_for_each_entry() and define static
definitions as such, in the PDR driver.

* tag 'qcom-drivers-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (33 commits)
  soc: qcom: pdr: use static for servreg_* variables
  soc: qcom: llcc: Add sc8180x and sc8280xp configurations
  dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
  soc: qcom: rpmhpd: add sc8280xp & sa8540p rpmh power-domains
  soc: qcom: rpmhpd: Don't warn about sparse rpmhpd arrays
  dt-bindings: power: rpmpd: Add sc8280xp RPMh power-domains
  spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema
  soc: qcom: socinfo: Sort out 8974PRO names
  dt-bindings: soc: qcom,smp2p: convert to dtschema
  dt-bindings: qcom: geni-se: Update UART schema reference
  dt-bindings: qcom: geni-se: Update I2C schema reference
  dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema
  bus: add driver for initializing the SSC bus on (some) qcom SoCs
  dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus
  dt-bindings: qcom: qcom,geni-se: refer to dtschema for SPI
  dt-bindings: soc: qcom,smd: convert to dtschema
  firmware: qcom_scm: Add compatible for MSM8976 SoC
  dt-bindings: firmware: qcom-scm: Document msm8976 bindings
  soc: qcom: smem: validate fields of shared structures
  soc: qcom: smem: map only partitions used by local HOST
  ...

Link: https://lore.kernel.org/r/20220509181839.316655-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-09 23:14:06 +02:00
Arnd Bergmann 64dbc4dd7a ARM: pxa: move plat-pxa to drivers/soc/
There are two drivers in arch/arm/plat-pxa: mfp and ssp. Both
of them should ideally not be needed at all, as there are
proper subsystems to replace them.

OTOH, they are self-contained and can simply be normal
SoC drivers, so move them over there to eliminate one more
of the plat-* directories.

Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> (mach-pxa)
Acked-by: Lubomir Rintel <lkundrak@v3.sk> (mach-mmp)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-07 22:56:16 +02:00
Arnd Bergmann fd13f8117f ARM: pxa: move smemc register access from clk to platform
The get_sdram_rows() and get_memclkdiv() helpers need smemc
register that are separate from the clk registers, move
them out of the clk driver, and use an extern declaration
instead.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Link: https://lore.kernel.org/lkml/87pnielzo4.fsf@belgarion.home/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-07 22:55:49 +02:00
Arnd Bergmann 6a946f1bd5 ARM: pxa: pcmcia: move smemc configuration back to arch
Rather than poking at the smemc registers directly from the
pcmcia/pxa2xx_base driver, move those bits into machine file
to have a cleaner interface.

Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Link: https://lore.kernel.org/lkml/87d0egjzxk.fsf@belgarion.home/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-07 22:55:49 +02:00
Bjorn Andersson ec69dfbdc4 soc: qcom: llcc: Add sc8180x and sc8280xp configurations
Add LLCC configuration data for the SC8180X and SC8280XP platforms,
based on the downstream tables.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Link: https://lore.kernel.org/r/20220502215406.612967-3-bjorn.andersson@linaro.org
2022-05-04 11:39:40 -05:00
Sven Peter b170143ae1 soc: apple: Add SART driver
The NVMe co-processor on the Apple M1 uses a DMA address filter called
SART for some DMA transactions. This adds a simple driver used to
configure the memory regions from which DMA transactions are allowed.

Unlike a real IOMMU, SART does not support any pagetables and can't be
implemented inside the IOMMU subsystem using iommu_ops.

It also can't be implemented using dma_map_ops since not all DMA
transactions of the NVMe controller are filtered by SART.
Instead, most buffers have to be registered using the integrated NVMe
IOMMU and we can't have two separate dma_map_ops implementations for a
single device.

Co-developed-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2022-05-02 17:24:45 +02:00
Sven Peter 9bd1d9a0d8 soc: apple: Add RTKit IPC library
Apple SoCs such as the M1 come with multiple embedded co-processors
running proprietary firmware. Communication with those is established
over a simple mailbox using the RTKit IPC protocol.

This cannot be implemented inside the mailbox subsystem since on top
of communication over channels we also need support for starting,
hibernating and resetting these co-processors. We also need to
handle shared memory allocations differently depending on the
co-processor and don't want to split that across multiple drivers.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2022-05-01 16:55:06 +02:00
Matthias Brugger 949cfe1a43 Merge tag 'v5.18-next-vdso0-stable-tag' into v5.18-next/soc 2022-04-22 14:39:59 +02:00
jason-jh.lin 4e8988c634 soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.

But its header need to keep DDP_COMPONENT_DITHER enum
until drm/mediatek also changed it.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220419094143.9561-7-jason-jh.lin@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-22 14:38:53 +02:00
jason-jh.lin b804923b7c soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
1. Add mt8195 mmsys compatible for 2 vdosys.
2. Add io_start into each driver data of mt8195 vdosys.
3. Add get match data function to identify mmsys by io_start.
4. Add mt8195 routing table settings of vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Link: https://lore.kernel.org/r/20220419094143.9561-2-jason-jh.lin@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-22 14:38:52 +02:00
Arnd Bergmann 615dce5bf7 ARM: omap1: fix build with no SoC selected
In a multiplatform randconfig kernel, one can have
CONFIG_ARCH_OMAP1 enabled, but none of the specific SoCs.
This leads to some build issues as the code is not
meant to deal with this configuration at the moment:

arch/arm/mach-omap1/io.c:86:20: error: unused function 'omap1_map_common_io' [-Werror,-Wunused-function]
arch/arm/mach-omap1/pm.h:113:2: error: "Power management for this processor not implemented yet" [-Werror,-W#warnings]

Use the same trick as on OMAP2 and guard the actual compilation
of platform code with another Makefile ifdef check based
on an option that depends on having at least one SoC enabled.

The io.c file still needs to get compiled to allow building
device drivers with a dependency on CONFIG_ARCH_OMAP1.

Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-22 11:08:55 +02:00
Arnd Bergmann 1e9ca7c811 ARM: omap1: move some headers to include/linux/soc
There are three remaining header files that are used by omap1
specific device drivers:

- mach/soc.h provides cpu_is_omapXXX abstractions
- mach/hardware.h provides omap_read/omap_write functions
  and physical addresses
- mach/mux.h provides an omap specific pinctrl abstraction

This is generally not how we do platform abstractions today,
and it would be good to completely get rid of these in favor
of passing information through platform devices and the pinctrl
subsystem.

However, given that nobody is working on that, just move it
one step forward by splitting out the header files that are
used by drivers today from the machine headers that are only
used internally.

Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-21 15:01:02 +02:00
Arnd Bergmann e8e77e9750 ARM: omap1: move mach/usb.h to include/linux/soc
The register definitions in this header are used in at least four
different places, with little hope of completely cleaning that up.

Split up the file into a portion that becomes a linux-wide header
under include/linux/soc/ti/, and the parts that are actually only
needed by board files.

Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-21 15:00:59 +02:00
Chun-Kuang Hu 5252c1c5a0 soc: mediatek: cmdq: Use mailbox rx_callback instead of cmdq_task_cb
rx_callback is a standard mailbox callback mechanism and could cover the
function of proprietary cmdq_task_cb, so use the standard one instead of
the proprietary one. Client has changed to use the standard callback
machanism and sync dma buffer in client driver, so remove the proprietary
callback in cmdq helper.

Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Tested-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Link: https://lore.kernel.org/r/1650102868-26219-1-git-send-email-chunkuang.hu@kernel.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-20 14:14:59 +02:00
Arnd Bergmann 08d3df8c81 ARM: pxa: split up mach/hardware.h
The mach/hardware.h is included in lots of places, and it provides
three different things on pxa:

- the cpu_is_pxa* macros
- an indirect inclusion of mach/addr-map.h
- the __REG() and io_pv2() helper macros

Split it up into separate <linux/soc/pxa/cpu.h> and mach/pxa-regs.h
headers, then change all the files that use mach/hardware.h to
include the exact set of those three headers that they actually
need, allowing for further more targeted cleanup.

linux/soc/pxa/cpu.h can remain permanently exported and is now in
a global location along with similar headers. pxa-regs.h and
addr-map.h are only used in a very small number of drivers now
and can be moved to arch/arm/mach-pxa/ directly when those drivers
are to pass the necessary data as resources.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Jacek Anaszewski <jacek.anaszewski@gmail.com>
Cc: Pavel Machek <pavel@ucw.cz>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mark Brown <broonie@kernel.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-input@vger.kernel.org
Cc: linux-leds@vger.kernel.org
Cc: linux-mmc@vger.kernel.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-rtc@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-fbdev@vger.kernel.org
Cc: linux-watchdog@vger.kernel.org
Cc: alsa-devel@alsa-project.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-19 16:27:05 +02:00
Felix Fietkau 804775dfc2 net: ethernet: mtk_eth_soc: add support for Wireless Ethernet Dispatch (WED)
The Wireless Ethernet Dispatch subsystem on the MT7622 SoC can be
configured to intercept and handle access to the DMA queues and
PCIe interrupts for a MT7615/MT7915 wireless card.
It can manage the internal WDMA (Wireless DMA) controller, which allows
ethernet packets to be passed from the packet switch engine (PSE) to the
wireless card, bypassing the CPU entirely.
This can be used to implement hardware flow offloading from ethernet to
WLAN.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-04-06 14:08:49 +01:00
Linus Torvalds 9512433987 There's one large change in the core clk framework here. We change how
clk_set_rate_range() works so that the frequency is re-evaulated each time the
 rate is changed. Previously we wouldn't let clk providers see a rate that was
 different if it was still within the range, which could be bad for power if the
 clk could run slower when a range expands. Now the clk provider can decide to
 do something differently when the constraints change. This broke Nvidia's clk
 driver so we had to wait for the fix for that to bake a little more in -next.
 
 The rate range patch series also introduced a kunit suite for the clk framework
 that we're going to extend in the next release. It already made it easy to find
 corner cases in the rate range patches so I'm excited to see it cover more clk
 code and increase our confidence in core framework patches in the future. I
 also added a kunit test for the basic clk gate code and that work will continue
 to cover more basic clk types: muxes, dividers, etc.
 
 Beyond the core code we have the usual set of clk driver updates and additions.
 Qualcomm again dominates the diffstat here with lots more SoCs being supported
 and i.MX follows afer that with a similar number of SoCs gaining clk drivers.
 Beyond those large additions there's drivers being modernized to use
 clk_parent_data so we can move away from global string names for all the clks
 in an SoC. Finally there's lots of little fixes all over the clk drivers for
 typos, warnings, and missing clks that aren't critical and get batched up
 waiting for the next merge window to open. Nothing super big stands out in the
 driver pile. Full details are below.
 
 Core:
  - Make clk_set_rate_range() re-evaluate the limits each time
  - Introduce various clk_set_rate_range() tests
  - Add clk_drop_range() to drop a previously set range
 
 New Drivers:
  - i.MXRT1050 clock driver and bindings
  - i.MX8DXL clock driver and bindings
  - i.MX93 clock driver and bindings
  - NCO blocks on Apple SoCs
  - Audio clks on StarFive JH7100 RISC-V SoC
  - Add support for the new Renesas RZ/V2L SoC
  - Qualcomm SDX65 A7 PLL
  - Qualcomm SM6350 GPU clks
  - Qualcomm SM6125, SM6350, QCS2290 display clks
  - Qualcomm MSM8226 multimedia clks
 
 Updates:
  - Kunit tests for clk-gate implementation
  - Terminate arrays with sentinels and make that clearer
  - Cleanup SPDX tags
  - Fix typos in comments
  - Mark mux table as const in clk-mux
  - Make the all_lists array const
  - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add
    support for dynamic mode
  - Clock configuration on Microchip PolarFire SoCs
  - Free allocations on probe error in Mediatek clk driver
  - Modernize Mediatek clk driver by consolidating code
  - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on
    Renesas R-Car S4-8
  - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates)
  - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568
  - Reintroduce the expected fractional-divider behaviour that disappeared
    with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
  - Remove SYS PLL 1/2 clock gates for i.MX8M*
  - Remove AUDIO MCLK ROOT from i.MX7D
  - Add fracn gppll clock type used by i.MX93
  - Add new composite clock for i.MX93
  - Add missing media mipi phy ref clock for i.MX8MP
  - Fix off by one in imx_lpcg_parse_clks_from_dt()
  - Rework for the imx pll14xx
  - sama7g5: One low priority fix for GCLK of PDMC
  - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
  - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
  - Add CAN-FD clocks on Renesas R-Car V3U
  - Qualcomm SC8280XP RPMCC
  - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
  - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML
  - Convert various Qualcomm drivers to use clk_parent_data
  - Remove test clocks from various Qualcomm drivers
  - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
  - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
  - Better pixel clk frequency support on Qualcomm RCG2 clks
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmJDd+gRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSVB4A//QWPv7tssTuHvVDOPz2q9rJFbjG6/fsuY
 d8i30y4uTSCWO2eErVUNKxRmrR5/DFJZ20cqv5aTXbiUk5BrmCiD0hyb8RZIU4jD
 Kw+1pEvnbBWR6s5TK0spMS9Nz9Uq8DBwoeczHAVQrRZu0I8AkOvWlVH7GncejYOP
 KJJSiuByXHRLxudrLWTwwkz3xoDTZBeBcqNbBnatgXnPgSzBh0Uz+0q8r9V9Hugw
 +TwXoTVt+XDrX2ihPzZlfm9xoOTOP6GoP+FYCo8gCfW4N0VjUDr3+D95rJoI2gp/
 O9UyAx1+tMLlkVxuHcX1npHDPX6Nrqan68DBV4LQRdhSO3dfVD95AE16GzMrD+2t
 nuIzT+rst42UUzipCK/8pHLd/YCcPmIsH4C25ZnaF/I59kI/seF3zbekMTY7hS8D
 q9sTZYj1X32aHGTtN6QK6QJIscGHYfnSG3M8VLOnhmWDKmW+6AWJ2MVZdcCqDgnS
 AXnx1p7gwd/lHV8P+e1YoiUyh5a3tJ2CFFdQCu0tPwL0xLehHyfjKqtjYZjL2+hl
 6pF8KxEy6BiMEZWqXmIUJK6xWFO9VpQ2uPxtV8pCTIAXmOOPenWhH7lkeTtIDRc0
 hzJURj9HEcpEDakC4/16yfr+YnEn/vjhhZ8a4Vymsnl2IsI71C17vDmRer875Bp/
 KPMBn6I1naQ=
 =fP8L
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "There's one large change in the core clk framework here. We change how
  clk_set_rate_range() works so that the frequency is re-evaulated each
  time the rate is changed. Previously we wouldn't let clk providers see
  a rate that was different if it was still within the range, which
  could be bad for power if the clk could run slower when a range
  expands. Now the clk provider can decide to do something differently
  when the constraints change. This broke Nvidia's clk driver so we had
  to wait for the fix for that to bake a little more in -next.

  The rate range patch series also introduced a kunit suite for the clk
  framework that we're going to extend in the next release. It already
  made it easy to find corner cases in the rate range patches so I'm
  excited to see it cover more clk code and increase our confidence in
  core framework patches in the future. I also added a kunit test for
  the basic clk gate code and that work will continue to cover more
  basic clk types: muxes, dividers, etc.

  Beyond the core code we have the usual set of clk driver updates and
  additions. Qualcomm again dominates the diffstat here with lots more
  SoCs being supported and i.MX follows afer that with a similar number
  of SoCs gaining clk drivers. Beyond those large additions there's
  drivers being modernized to use clk_parent_data so we can move away
  from global string names for all the clks in an SoC. Finally there's
  lots of little fixes all over the clk drivers for typos, warnings, and
  missing clks that aren't critical and get batched up waiting for the
  next merge window to open. Nothing super big stands out in the driver
  pile. Full details are below.

  Core:
   - Make clk_set_rate_range() re-evaluate the limits each time
   - Introduce various clk_set_rate_range() tests
   - Add clk_drop_range() to drop a previously set range

  New Drivers:
   - i.MXRT1050 clock driver and bindings
   - i.MX8DXL clock driver and bindings
   - i.MX93 clock driver and bindings
   - NCO blocks on Apple SoCs
   - Audio clks on StarFive JH7100 RISC-V SoC
   - Add support for the new Renesas RZ/V2L SoC
   - Qualcomm SDX65 A7 PLL
   - Qualcomm SM6350 GPU clks
   - Qualcomm SM6125, SM6350, QCS2290 display clks
   - Qualcomm MSM8226 multimedia clks

  Updates:
   - Kunit tests for clk-gate implementation
   - Terminate arrays with sentinels and make that clearer
   - Cleanup SPDX tags
   - Fix typos in comments
   - Mark mux table as const in clk-mux
   - Make the all_lists array const
   - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding
     and add support for dynamic mode
   - Clock configuration on Microchip PolarFire SoCs
   - Free allocations on probe error in Mediatek clk driver
   - Modernize Mediatek clk driver by consolidating code
   - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks
     on Renesas R-Car S4-8
   - Improve the clocks for the Rockchip rk3568 display outputs
     (parenting, pll-rates)
   - Use of_device_get_match_data() instead of open-coding on Rockchip
     rk3568
   - Reintroduce the expected fractional-divider behaviour that
     disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
   - Remove SYS PLL 1/2 clock gates for i.MX8M*
   - Remove AUDIO MCLK ROOT from i.MX7D
   - Add fracn gppll clock type used by i.MX93
   - Add new composite clock for i.MX93
   - Add missing media mipi phy ref clock for i.MX8MP
   - Fix off by one in imx_lpcg_parse_clks_from_dt()
   - Rework for the imx pll14xx
   - sama7g5: One low priority fix for GCLK of PDMC
   - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
   - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
   - Add CAN-FD clocks on Renesas R-Car V3U
   - Qualcomm SC8280XP RPMCC
   - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
   - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to
     YAML
   - Convert various Qualcomm drivers to use clk_parent_data
   - Remove test clocks from various Qualcomm drivers
   - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
   - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
   - Better pixel clk frequency support on Qualcomm RCG2 clks"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
  clk: zynq: Update the parameters to zynq_clk_register_periph_clk
  clk: zynq: trivial warning fix
  clk: Drop the rate range on clk_put()
  clk: test: Test clk_set_rate_range on orphan mux
  clk: Initialize orphan req_rate
  dt-bindings: clock: drop useless consumer example
  dt-bindings: clock: renesas: Make example 'clocks' parsable
  clk: qcom: gcc-msm8994: Fix gpll4 width
  dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml
  clk: rs9: Add Renesas 9-series PCIe clock generator driver
  clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
  clk: visconti: prevent array overflow in visconti_clk_register_gates()
  dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
  clk: sifive: Move all stuff into SoCs header files from C files
  clk: sifive: Add SoCs prefix in each SoCs-dependent data
  riscv: dts: Change the macro name of prci in each device node
  dt-bindings: change the macro name of prci in header files and example
  clk: sifive: duplicate the macro definitions for the time being
  clk: qcom: sm6125-gcc: fix typos in comments
  clk: ti: clkctrl: fix typos in comments
  ...
2022-03-30 10:11:04 -07:00
Linus Torvalds 50d602d81f - qcom: add support for MSM8976
- mtk: enable mt8186
 		add ADSP controller driver
 - ti: use poll mode during suspend
 - tegra: fix tx channel flush
 - imx: add i.MX8 SECO MU support
 		prepare for, and add iMX93 support
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE6EwehDt/SOnwFyTyf9lkf8eYP5UFAmItTzIACgkQf9lkf8eY
 P5WZdw/9HsyFdS3n478i0Iut8TgRgke88/ZrhiWekSNJfSrGmKiMbSn1QdDLpqMV
 A113m4rnduz4n4upe+SxWzBA76BbKePUpjW+Fsvu3OtxZ/6LwNmkKsa7z91+CF7n
 RQh+JXmmiO0rLwl10zIsYSXr3zjSz85mKNJUZFtdNFqaj0RZhJPWSVm2OUz36ONk
 WviDiDeWJuqJBtfRXIbqkqGv1YbWHa4CwsxYBA8R91OQOrb9Wd9A7roeUJjR2yvH
 PISGcGycMnDrfowNU3IU1rTVzNq/ojeNX3EfhR489MiKoLVvv5+O8Thr5UODf7TW
 ZtbdVANCywGO0KVpgbQb60TCJi1mzjmyw0UietDw/zz7d8TNKc3CbyR5I3CRMqSU
 epxpjpywAppdd3AZAKe/x44ctlefiSnzzCFqq3eNk2HnQr+p/mKnFW+JwnN8qEVK
 hTAq7L7kkBqQbWRdwPAkE4nAjT2PhdLL0CegOjygP2WBAVU43QdeDoutZMJFeBNZ
 AJUMGLSzbxDNM4Nxaq2xUbn6Sm7MoPRFPrUDIkuW+NFH7XqAYetTIgiNvhv/qGMS
 Qpwn0ZVEZAxEj+wQKBUID84zj2FTCgcCMqkm8PADahjDzjCDEPKOMmTYxiqjSwXa
 VM7Np5+cCSYIVyz6/uYQ3AYcBgfxt0M+rB4qGGEgBFGLT/SEFcQ=
 =mmKG
 -----END PGP SIGNATURE-----

Merge tag 'mailbox-v5.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar:
 "qcom:
   - add support for MSM8976

  mtk:
   - enable mt8186
   - add ADSP controller driver

  ti:
   - use poll mode during suspend

  tegra:
   - fix tx channel flush

  imx:
   - add i.MX8 SECO MU support
   - prepare for, and add iMX93 support"

* tag 'mailbox-v5.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  dt-bindings: mailbox: add definition for mt8186
  mailbox: ti-msgmgr: Operate mailbox in polled mode during system suspend
  mailbox: ti-msgmgr: Refactor message read during interrupt handler
  mailbox: imx: support i.MX93 S401 MU
  mailbox: imx: support dual interrupts
  mailbox: imx: extend irq to an array
  dt-bindings: mailbox: imx-mu: add i.MX93 S4 MU support
  dt-bindings: mailbox: imx-mu: add i.MX93 MU
  mailbox: imx: add i.MX8 SECO MU support
  mailbox: imx: introduce rxdb callback
  dt-bindings: mailbox: imx-mu: add i.MX8 SECO MU support
  mailbox: imx: enlarge timeout while reading/writing messages to SCFW
  mailbox: imx: fix crash in resume on i.mx8ulp
  mailbox: imx: fix wakeup failure from freeze mode
  mailbox: mediatek: add support for adsp mailbox controller
  dt-bindings: mailbox: mtk,adsp-mbox: add mtk adsp-mbox document
  mailbox: qcom-apcs-ipc: Add compatible for MSM8976 SoC
  dt-bindings: mailbox: Add compatible for the MSM8976
  mailbox: tegra-hsp: Flush whole channel
2022-03-27 14:21:57 -07:00
Linus Torvalds b4bc93bd76 ARM driver updates for 5.18
There are a few separately maintained driver subsystems that we merge through
 the SoC tree, notable changes are:
 
  - Memory controller updates, mainly for Tegra and Mediatek SoCs,
    and clarifications for the memory controller DT bindings
 
  - SCMI firmware interface updates, in particular a new transport based
    on OPTEE and support for atomic operations.
 
  - Cleanups to the TEE subsystem, refactoring its memory management
 
 For SoC specific drivers without a separate subsystem, changes include
 
  - Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
    Layerscape SoCs.
 
  - Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
    and Qualcomm SM8450.
 
  - Better power management on Mediatek MT81xx, NXP i.MX8MQ
    and older NVIDIA Tegra chips
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmI4nOUACgkQmmx57+YA
 GNlNNhAApPQw+FKQ6yVj2EZYcaAgik8PJAJoNQWYED52iQfm5uXgjt3aQewvrPNW
 nkKx5Mx+fPUfaKx5mkVOFMhME5Bw9tYbXHm2/RpRp+n8jOdUlQpAhzIPOyWPHOJS
 QX6qu4t+agrQzjbOCGouAJXgyxhTJFUMviM2EgVHbQHXPtdF8i2kyanfCP7Rw8cx
 sVtLwpvhbLm849+deYRXuv2Xw9I3M1Np7018s5QciimI2eLLEb+lJ/C5XWz5pMYn
 M1nZ7uwCLKPCewpMETTuhKOv0ioOXyY9C1ghyiGZFhHQfoCYTu94Hrx9t8x5gQmL
 qWDinXWXVk8LBegyrs8Bp4wcjtmvMMLnfWtsGSfT5uq24JOGg22OmtUNhNJbS9+p
 VjEvBgkXYD7UEl5npI9v9/KQWr3/UDir0zvkuV40gJyeBWNEZ/PB8olXAxgL7wZv
 cXRYSaUYYt3DKQf1k5I4GUyQtkP/4RaBy6AqvH5Sx0lCwuY6G6ISK+kCPaaSRKnX
 WR+nFw84dKCu7miehmW9qSzMQ4kiSCKIDqk7ilHcwv0J2oXDrlqVPKGGGTzZjUc8
 +feqM/eSoYvDDEDemuXNSnl3hc1Zlvm7Apd5AN6kdTaNgoACDYdyvGuJ3CvzcA+K
 1gBHUBvGS/ODA25KnYabr7wCMgxYqf7dXfkyKIBwFHwxOnRHtgs=
 =Cfbk
 -----END PGP SIGNATURE-----

Merge tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM driver updates from Arnd Bergmann:
 "There are a few separately maintained driver subsystems that we merge
  through the SoC tree, notable changes are:

   - Memory controller updates, mainly for Tegra and Mediatek SoCs, and
     clarifications for the memory controller DT bindings

   - SCMI firmware interface updates, in particular a new transport
     based on OPTEE and support for atomic operations.

   - Cleanups to the TEE subsystem, refactoring its memory management

  For SoC specific drivers without a separate subsystem, changes include

   - Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
     Layerscape SoCs.

   - Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
     and Qualcomm SM8450.

   - Better power management on Mediatek MT81xx, NXP i.MX8MQ and older
     NVIDIA Tegra chips"

* tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits)
  ARM: spear: fix typos in comments
  soc/microchip: fix invalid free in mpfs_sys_controller_delete
  soc: s4: Add support for power domains controller
  dt-bindings: power: add Amlogic s4 power domains bindings
  ARM: at91: add support in soc driver for new SAMA5D29
  soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
  dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
  memory: emif: check the pointer temp in get_device_details()
  memory: emif: Add check for setup_interrupts
  dt-bindings: arm: mediatek: mmsys: add support for MT8186
  dt-bindings: mediatek: add compatible for MT8186 pwrap
  soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
  soc: mediatek: mmsys: add mmsys reset control for MT8186
  soc: mediatek: mtk-infracfg: Disable ACP on MT8192
  soc: ti: k3-socinfo: Add AM62x JTAG ID
  soc: mediatek: add MTK mutex support for MT8186
  soc: mediatek: mmsys: add mt8186 mmsys routing table
  soc: mediatek: pm-domains: Add support for mt8186
  dt-bindings: power: Add MT8186 power domains
  soc: mediatek: pm-domains: Add support for mt8195
  ...
2022-03-23 18:23:13 -07:00
Dave Gerlach df227dc8a6 mailbox: ti-msgmgr: Operate mailbox in polled mode during system suspend
During the system suspend path we must set all queues to operate in
polled mode as it is possible for any protocol built using this mailbox,
such as TISCI, to require communication during the no irq phase of suspend,
and we cannot rely on interrupts there.

Polled mode is implemented by allowing the mailbox user to define an
RX channel as part of the message that is sent which is what gets polled
for a response. If polled mode is enabled, this will immediately be
polled for a response at the end of the mailbox send_data op before
returning success for the data send or timing out if no response is
received.

Finally, to ensure polled mode is always enabled during system suspend,
iterate through all queues to set RX queues to polled mode during system
suspend and disable polled mode for all in the resume handler.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-12 19:33:30 -06:00
Konrad Dybcio f804360bb3 clk: qcom: smd: Add missing RPM clocks for msm8992/4
XO and MSS_CFG were omitted when first adding the clocks for these SoCs.
Add them, and while at it, move the XO clock to the top of the definition
list, as ideally everyone should start using it sooner or later..

Fixes: b429784499 ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226214126.21209-2-konrad.dybcio@somainline.org
2022-03-09 08:53:14 -06:00
Arnd Bergmann 4d558d4d88 Qualcomm driver updates for v5.18
This refactors the Qualcomm mdt file loader, to partially decouple it
 from the SCM peripheral-authentication-service. This is needed as newer
 platforms, such as the Qualcomm SM8450, require the metadata to remain
 accessible to TrustZone during a longer time. This is followed by the
 introduction of remoteproc drivers for SM8450 (Snapdragon 8 Gen 1).
 
 It changes the way hardware version differences are handled in the LLCC
 driver and introduces support for Qualcomm SM8450. While updating the dt
 binding for LLCC it also introduces the missing SM8350 compatible.
 
 The ocmem and aoss drivers gains missing put_device() calls and rpmpd
 gains a missing check for kcalloc() failure.
 
 The SPM driver is updated to avoid instantiating the SPM cpuidle devices
 if the CPUs aren't controlled by SPM, such as when Snapdragon 8916
 operates in 32-bit mode without PSCI.
 
 The RPM power-domain driver gains MSM8226 support.
 
 Lastly the socinfo driver gains knowledge about a few new SoCs and
 PMICs.
 -----BEGIN PGP SIGNATURE-----
 
 iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmIdnvAbHGJqb3JuLmFu
 ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FFMIQAL8yVzMuonz7yiuxZaC6
 nvCGWVIbsfjloLWjpE79orSoEx77DlhYaUDHdYqHMEV9ytdryaSaU5A5LGfzVugC
 D6TSvJh1SDV6hJ79xRZIDO72fJn/Xo62JCtTC4u+iBgoehhMrOQHm7HlBhLXJ2lq
 RiHDjzCHMaRTrPf1GCY8a1VK0nIa8KfaAbk+GzZ5Y+0I4oh7ea43DwUSYAIvZAKi
 N5CRXRFeoGpEnY9FzYYfkTPXu28hvj3NtGaEX8SIyzmgLBxCqLpFfxVj3xUsDGbX
 TFqr5YWO31/5oQN4Ex0IrD4NOyOtVyPCtd6iSmlW3t+LxcQsgfW4cCfzT9vQp8dV
 LLkhvKQCAMyIIzZtoHQRN2J0L4tQ8kW1lxW01XMbEjm0lOoALGisE8KouSPlAFn8
 zgX6bPWUmsuictfG8gmqgqKsloV6E5IU37Htcm+sdw89ZVks6UJG40D3DiOcpAXX
 eEKRMW8UHhR/u2AQRlaBcSTQVI/zfXWFk408zHxfD6fphrfnSPRBl+CEZmqrySWi
 eqsL1PJblZg1Uhg5Q8XRokAzB59RYVbs6jSiLKGTUvwTrBMUy+SK1UOG9V3pXsOv
 TSW92RXKZFS8smNcKm/2k1bhopW+2h2BB0z1OYBynl+VUOtCadf7DHciGmAn/Hxd
 eyL2HBVqS4LtdLHSL2TAj3oM
 =okza
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIeZNUACgkQmmx57+YA
 GNmKBBAAwpweTveDkEmeT6nTckDaRYBo0LthJr6TmgndjKq5QChknEOFSMvs6JzP
 Ftheb+J7NcrQ20vN+wv8ic2k6hP8UCRrxyt7IJSJ3iDsqjODxW0K/qoetpFL1BoY
 zCdo0+C7R9iK4QbEA7HjbG5SCVMe8eOLGJLWXkbAO/DInU/WZfSmbbieDSNIjHIp
 nBoX5iBPKHMxj8Cbi12ezK+NHgwXkPdc+H0YNnwbBX6cr470bq5AarJCuWS4W0XP
 xUTC86mR9NUDMu4MkIjbtTZUgKOSXuQoioH4uJKNTDObD+i1GDUNWTm1nvxrQMe1
 DZctGN2ISHKjzcS2okcYwZ4CX8SEB3QK07YydyBknsNINxvwm1fB23VtCikP4k2r
 Zqo6ewT1Y1imrb2MmjWyTesXO1u+JDz5d0A3O9O93Yvfn6Zz/wiGQV6HSmbU6RpQ
 JyJWUOokCydqKXMLlb79Ln2Sx8q84aoZGekEQGfTqvIObntuYx0VWdMJuisP0z4+
 CqZTnIc60IaG8WkB/xx/vzzKa8XmKTfalSxZV5ThTruVmiHAqd1rW8N/mR4ZE2bM
 YQ0AxQcaZHyUawPuaqOY/u9lADE0ROW/3loC5CWU8LLTSR3OM610YgQOKNC8yi2n
 FlEYdhupJEGcx4fLY+SPWGgYFhIZgqxlL7WNtzg7uEFiBpayLxA=
 =vkG6
 -----END PGP SIGNATURE-----

Merge tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.18

This refactors the Qualcomm mdt file loader, to partially decouple it
from the SCM peripheral-authentication-service. This is needed as newer
platforms, such as the Qualcomm SM8450, require the metadata to remain
accessible to TrustZone during a longer time. This is followed by the
introduction of remoteproc drivers for SM8450 (Snapdragon 8 Gen 1).

It changes the way hardware version differences are handled in the LLCC
driver and introduces support for Qualcomm SM8450. While updating the dt
binding for LLCC it also introduces the missing SM8350 compatible.

The ocmem and aoss drivers gains missing put_device() calls and rpmpd
gains a missing check for kcalloc() failure.

The SPM driver is updated to avoid instantiating the SPM cpuidle devices
if the CPUs aren't controlled by SPM, such as when Snapdragon 8916
operates in 32-bit mode without PSCI.

The RPM power-domain driver gains MSM8226 support.

Lastly the socinfo driver gains knowledge about a few new SoCs and
PMICs.

* tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (37 commits)
  soc: qcom: rpmpd: Add MSM8226 support
  dt-bindings: power: rpmpd: Add MSM8226 to rpmpd binding
  soc: qcom: mdt_loader: Fix split-firmware condition
  dt-bindings: arm: msm: Add LLCC compatible for SM8450
  dt-bindings: arm: msm: Add LLCC compatible for SM8350
  soc: qcom: llcc: Add configuration data for SM8450 SoC
  soc: qcom: llcc: Update register offsets for newer LLCC HW
  soc: qcom: llcc: Add missing llcc configuration data
  soc: qcom: llcc: Add write-cache cacheable support
  soc: qcom: llcc: Update the logic for version info extraction
  soc: qcom: llcc: Add support for 16 ways of allocation
  soc: qcom: socinfo: Add some more PMICs and SoCs
  firmware: qcom: scm: Add support for MC boot address API
  firmware: qcom: scm: Drop cpumask parameter from set_boot_addr()
  firmware: qcom: scm: Simplify set_cold/warm_boot_addr()
  cpuidle: qcom-spm: Check if any CPU is managed by SPM
  remoteproc: qcom: pas: Add SM8450 remoteproc support
  dt-bindings: remoteproc: qcom: pas: Add SM8450 PAS compatibles
  remoteproc: qcom: pas: Carry PAS metadata context
  soc: qcom: mdt_loader: Extract PAS operations
  ...

Link: https://lore.kernel.org/r/20220301042055.1804859-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-01 19:24:21 +01:00
Arnd Bergmann 16e769e2ae - add power domains support for mt8195
- disable ACP on mt8192
 
 mt8186:
 - add support for power domains
 - add mmsys and mutex support needed for DRM
 - add reset control based on mmsys subsystem
 - add pmic wrapper
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmId5EgXHG1hdHRoaWFz
 LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH4gEg/+LL7XjcWZlD8GwTfJEeZjgk3c
 06rne1kKh0mm9+VEIHOp0RsMf4IdbHwCbAt3xMMcdOqAxh4oaKchCE0fPS2d+mdA
 2qZaysEBxG6RTs/wY9fS1/diGge3OroW3CuS0cv6mKh7acY9tLW5/VRvvgcOzSrT
 eJYGQqpXg4VfUJ41e7otIhj32Npltby9lBlo8Z5kF3Vy7yYAUEZvNrGrp0pmwkvM
 UJRlCZFoSGAfoijJfpH38vixi+qWYOiAhulweT01VhtIVYHjh+BmoQc4jZ8A7fhW
 ttzlrbYPELRD0eu6/zfdokXWVwZjkqB5HoumN7IaYW+ZUEY6iYhy9J+Ir9qpG82D
 Z4cbk4JMc6uEAjTdu6njdzlBukw80oXOo6nCyPa+xvniNWPoYTHN5JZaNWig4taC
 5i9diVBuwkOdYARKSFqxk1FuvvSDh+8QP9hNiomXZrPUjZgilXDQ2CncKFr70CNM
 iCQqCiHNpzaVEMxBkve2aU9kKc5qVixrLAqh/VOwpUln66aE1Ug51zzdAAkalyQv
 di6iZMRFy+pL3oNPFWAKv0Z0yowBj/QDFBZiOc/SqXrrNpHNDfMVPcSdZVtjSBXD
 DqPxPFRHaqV/+eFHc9xyvgKMMbg2xYsZXVrleyQWiXck0x2mshw3hIcghGpkPGDB
 w+b5BPpeewE49tamKJs=
 =KUFa
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmId8OYACgkQmmx57+YA
 GNlaoA//cdGz81n8HG8zy1DpprypmbUCJv6SruIF1XE2ewOgZ486IiA0H1yYdSD5
 kDmok9SDjFM+WmqxoGUQl5hcNH67ThD/5rxgKgrIpi4kpfhgjbhYLJ9PGjZSAc4v
 9zW+l48WDYxHmq7xhsCgsC6BoimM3MHwJTA3crMzXqtG3PecrLtnMS6EAaX/Uoub
 Vw7HW8v7PAeO9xx4tBV+c65jYDmmcBm21iv9EptEUOgK06OhjyH6KoQjFwGpg/tb
 uEDehYDK5pULc9U2322sfRJ0b0LpD/+yJMREITe9XYuHX+4akqVEscEVvnwh/j+1
 PXwwtGOnVMk/5TLaLUQy181x4soXG+8uBVbitHpZVCfmRvel6fAbnfgAxyf7sYy/
 Kdbp1apVnQ7nDeW/rhR7glNrJSUN+R2uBbfmXPyU+MOoPG+1Ckz6YR4VrjKx0M/N
 K7qkqwJxp7TkuFJXzqWi58apyHqBdM9LzsyroRjk8FqeDC60T6RQDhJXuXDpDp58
 na4WDaS5expzgWpGiJwrm2MfT0rbI9X7pyGRcCPY6kVwtnLX84npVal6ZbS8jCwp
 KRO13i/ZzZj9ZNlOhANgYodedW4dO/tyW39xMIzYrQ+5QjQ8IvD+DFnv50F1DzON
 5IbTBTDS1B07dIikIb9FFLrGZL/bqEtafg9kGsYfypmXfVPf3FY=
 =G//M
 -----END PGP SIGNATURE-----

Merge tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

- add power domains support for mt8195
- disable ACP on mt8192

mt8186:
- add support for power domains
- add mmsys and mutex support needed for DRM
- add reset control based on mmsys subsystem
- add pmic wrapper

* tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  dt-bindings: arm: mediatek: mmsys: add support for MT8186
  dt-bindings: mediatek: add compatible for MT8186 pwrap
  soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
  soc: mediatek: mmsys: add mmsys reset control for MT8186
  soc: mediatek: mtk-infracfg: Disable ACP on MT8192
  soc: mediatek: add MTK mutex support for MT8186
  soc: mediatek: mmsys: add mt8186 mmsys routing table
  soc: mediatek: pm-domains: Add support for mt8186
  dt-bindings: power: Add MT8186 power domains
  soc: mediatek: pm-domains: Add support for mt8195
  soc: mediatek: pm-domains: Move power status offset to power domain data
  soc: mediatek: pm-domains: Remove unused macro
  soc: mediatek: pm-domains: Add wakeup capacity support in power domain
  dt-bindings: power: Add MT8195 power domains

Link: https://lore.kernel.org/r/16a53482-5a8c-e95e-8cd4-b8304f110987@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-01 11:09:42 +01:00
Alyssa Rosenzweig dcfd519256 soc: mediatek: mtk-infracfg: Disable ACP on MT8192
MT8192 contains an experimental Accelerator Coherency Port
implementation, which does not work correctly but was unintentionally
enabled by default. For correct operation of the GPU, we must set a
chicken bit disabling ACP on MT8192.

Adapted from the following downstream change to the out-of-tree, legacy
Mali GPU driver:

https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5

Note this change is required for both Panfrost and the legacy kernel
driver.

Co-developed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Nick Fan <Nick.Fan@mediatek.com>
Cc: Nicolas Boichat <drinkcat@chromium.org>
Cc: Chen-Yu Tsai <wenst@chromium.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220215184651.12168-1-alyssa.rosenzweig@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-01 08:21:28 +01:00
Chun-Jie Chen 88590cbc17 soc: mediatek: pm-domains: Add support for mt8186
Add power domain control data in mt8186.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220215104917.5726-3-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:11 +01:00
Chun-Jie Chen 342479c86d soc: mediatek: pm-domains: Add support for mt8195
Add domain control data including bus protection data size
change due to more protection steps in mt8195.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28 12:02:04 +01:00
Linus Walleij 3059dfa52c ARM: ixp4xx: Remove feature bit accessors
We switched users of the accessors over to using syscon to inspect
the bits, or removed the need for checking them. Delete these
accessors.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220211223238.648934-11-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-12 18:20:04 +01:00
Linus Walleij 8754a7e61c soc: ixp4xx-npe: Access syscon regs using regmap
If we access the syscon (expansion bus config registers) using the
syscon regmap instead of relying on direct accessor functions,
we do not need to call this static code in the machine
(arch/arm/mach-ixp4xx/common.c) which makes things less dependent
on custom machine-dependent code.

Look up the syscon regmap and handle the error: this will make
deferred probe work with relation to the syscon.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220211223238.648934-8-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-12 18:20:03 +01:00
Linus Walleij b50113cbdd soc: ixp4xx: Add features from regmap helper
If we want to read the CFG2 register on the expansion bus and
apply the inversion and check for some hardcoded versions this
helper comes in handy.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220211223238.648934-7-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-12 18:20:03 +01:00
Sai Prakash Ranjan a6e9d7ef25 soc: qcom: llcc: Add configuration data for SM8450 SoC
Add LLCC configuration data for SM8450 SoC.

Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/fec944cb8f2a4a70785903c6bfec629c6f31b6a4.1643355594.git.quic_saipraka@quicinc.com
2022-02-10 18:29:33 -06:00
Sai Prakash Ranjan 8008e7902f soc: qcom: llcc: Update the logic for version info extraction
LLCC HW version info is made up of major, branch, minor and echo
version bits each of which are 8bits. Several features in newer
LLCC HW are based on the full version rather than just major or
minor versions such as write-subcache enable which is applicable
for versions v2.0.0.0 and later, also upcoming write-subcache
cacheable for SM8450 SoC which is only present in versions v2.1.0.0
and later, so it makes it easier and cleaner to just directly
compare with the full version than adding additional major/branch/
minor/echo version checks. So remove the earlier major version check
and add full version check for those features.

Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/a82d7c32348c51fcc2b63e220d91b318bf706c83.1643355594.git.quic_saipraka@quicinc.com
2022-02-10 18:29:33 -06:00
Bjorn Andersson f4e526ff7e soc: qcom: mdt_loader: Extract PAS operations
Rather than passing a boolean to indicate if the PAS operations should
be performed from within __mdt_load(), extract them to their own helper
function.

This will allow clients to invoke this directly, with some
qcom_scm_pas_metadata context that they later needs to release, without
further having to complicate the prototype of qcom_mdt_load().

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220128025513.97188-9-bjorn.andersson@linaro.org
2022-02-03 21:54:48 -06:00
Bjorn Andersson 8bd42e2341 soc: qcom: mdt_loader: Allow hash segment to be split out
It's been observed that some firmware found in a Qualcomm SM8450 device
has the hash table in a separate .bNN file. Use the newly extracted
helper function to load this segment from the separate file, if it's
determined that the hashes are not part of the already loaded firmware.

In order to do this, the function needs access to the firmware basename
and to provide more useful error messages a struct device to associate
the errors with.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220128025513.97188-4-bjorn.andersson@linaro.org
2022-02-03 15:32:30 -06:00
Christophe JAILLET 043cfff99a firmware: ti_sci: Fix compilation failure when CONFIG_TI_SCI_PROTOCOL is not defined
Remove an extra ";" which breaks compilation.

Fixes: 53bf2b0e4e ("firmware: ti_sci: Add support for getting resource with subtype")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/e6c3cb793e1a6a2a0ae2528d5a5650dfe6a4b6ff.1640276505.git.christophe.jaillet@wanadoo.fr
2022-02-02 13:12:37 -06:00
Linus Torvalds feb7a43de5 Rework of the MSI interrupt infrastructure:
Treewide cleanup and consolidation of MSI interrupt handling in
   preparation for further changes in this area which are necessary to:
 
   - address existing shortcomings in the VFIO area
 
   - support the upcoming Interrupt Message Store functionality which
     decouples the message store from the PCI config/MMIO space
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmHf+SETHHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYobzGD/wNEFl5qQo5mNZ9thP6JSJFOItm7zMc
 2QgzCYOqNwAv4jL6Dqo+EHtbShYqDyWzKdKccgqNjmdIqgW8q7/fubN1OPzRsClV
 CZG997AsXDGXYlQcE3tXZjkeCWnWEE2AGLnygSkFV1K/r9ALAtFfTBJAWB+UD+Zc
 1P8Kxo0q0Jg+DQAMAA5bWfSSjo/Pmpr/1AFjY7+GA8BBeJJgWOyW7H1S+GYEWVOE
 RaQP81Sbd6x1JkopxkNqSJ/lbNJfnPJxi2higB56Y0OYn5CuSarYbZUM7oQ2V61t
 jN7pcEEvTpjLd6SJ93ry8WOcJVMTbccCklVfD0AfEwwGUGw2VM6fSyNrZfnrosUN
 tGBEO8eflBJzGTAwSkz1EhiGKna4o1NBDWpr0sH2iUiZC5G6V2hUDbM+0PQJhDa8
 bICwguZElcUUPOprwjS0HXhymnxghTmNHyoEP1yxGoKLTrwIqkH/9KGustWkcBmM
 hNtOCwQNqxcOHg/r3MN0KxttTASgoXgNnmFliAWA7XwseRpLWc95XPQFa5sptRhc
 EzwumEz17EW1iI5/NyZQcY+jcZ9BdgCqgZ9ECjZkyN4U+9G6iACUkxVaHUUs77jl
 a0ISSEHEvJisFOsOMYyFfeWkpIKGIKP/bpLOJEJ6kAdrUWFvlRGF3qlav3JldXQl
 ypFjPapDeB5guw==
 =vKzd
 -----END PGP SIGNATURE-----

Merge tag 'irq-msi-2022-01-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull MSI irq updates from Thomas Gleixner:
 "Rework of the MSI interrupt infrastructure.

  This is a treewide cleanup and consolidation of MSI interrupt handling
  in preparation for further changes in this area which are necessary
  to:

   - address existing shortcomings in the VFIO area

   - support the upcoming Interrupt Message Store functionality which
     decouples the message store from the PCI config/MMIO space"

* tag 'irq-msi-2022-01-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (94 commits)
  genirq/msi: Populate sysfs entry only once
  PCI/MSI: Unbreak pci_irq_get_affinity()
  genirq/msi: Convert storage to xarray
  genirq/msi: Simplify sysfs handling
  genirq/msi: Add abuse prevention comment to msi header
  genirq/msi: Mop up old interfaces
  genirq/msi: Convert to new functions
  genirq/msi: Make interrupt allocation less convoluted
  platform-msi: Simplify platform device MSI code
  platform-msi: Let core code handle MSI descriptors
  bus: fsl-mc-msi: Simplify MSI descriptor handling
  soc: ti: ti_sci_inta_msi: Remove ti_sci_inta_msi_domain_free_irqs()
  soc: ti: ti_sci_inta_msi: Rework MSI descriptor allocation
  NTB/msi: Convert to msi_on_each_desc()
  PCI: hv: Rework MSI handling
  powerpc/mpic_u3msi: Use msi_for_each-desc()
  powerpc/fsl_msi: Use msi_for_each_desc()
  powerpc/pasemi/msi: Convert to msi_on_each_dec()
  powerpc/cell/axon_msi: Convert to msi_on_each_desc()
  powerpc/4xx/hsta: Rework MSI handling
  ...
2022-01-13 09:05:29 -08:00
Arnd Bergmann 13ee75c7b5 Qualcomm driver updates for v5.17
This introduces RPM power-domain support for the SM8450, SM6125 and
 QCM2290 platforms. It them clean up the platform-based naming of the
 resources definitions throughout the RPMh PD driver.
 
 The last-level cache controller driver gains SM8350 support.
 
 The RPM sleep stats driver gains support for several older systems that
 had a slightly different memory layout for this information.
 
 The socinfo gains SM8450, SM6350 and SM7227 definitions.
 
 In addition to the DeviceTree binding updates related to these changes
 new compatibles was added to describe the SM8450 and the Kryo 780 CPU.
 
 Lastly a few typo and style fixes are introduced.
 -----BEGIN PGP SIGNATURE-----
 
 iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmHBUg4bHGJqb3JuLmFu
 ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FObUQAOCTBSbL/US0wCCUEHPq
 MScjFtPDAV88bJi9uRzi5lalwPd/3yPZu+XLcCV/CjRj6nlGAbua2EcogvMsM1Lj
 rgHZopKnnDOHEFII2ZZ3lyJN4EntvSGHtnm/i2Jd7n3nB52zBkuRpgn3mi32QWoL
 QmGECClAPFBlQi9P33yHDZ/XC8ZK1y982G+Pb8SD6guxmtGxXCm4SaZ4qwVya53s
 euBl+nT/snARPEwaqRoGIsvs+fH2BcoJbug19MLQ+3Q4K9ycxQkWalzcMsLM/EjT
 H1JGjoaHbTpNhyMmKDqN2jS0CkvoLiYOIvhAbqw6l2HluRkn8QhcDOJJ9RHl2oB/
 EqYkK457F7smA0Z9vViuaEZJWfyPNt0z2c7zcpf73Iuk8cBM+48MUQ1UOwyvQh3c
 8AeyyAkgyYBWv58h5rLDS2fqD+tWx4hz6tqxyYojsxYjQkyWRDU6540tGSDeVAt+
 SUQ9qFXWyG7R5Z3GBVHi7ztXnkl6vYZUF05fhZrkpw9YrGlmu3wK/3Rcg9ZIECOg
 Q0UA/GQsqQtCqmzkRQsur/ljEbCrmtiB6JvG+7cnQIWPwcN/4Ho3wyfXvtzNvNki
 dMIpd+7NKkTaj1HUaH5qEnyO4szUpMoFfOrtqzlucH5dGG6fppY3svVWzuxLcbDy
 8+b+/aDuWa7HUXpBbPaK7H7U
 =ovup
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHBy8wACgkQmmx57+YA
 GNmS3xAAhIPIdMWF76Gb7eQu0UWrbuACSl0Nkt5SRbRyjX0BHectf+ssXUzR6r2/
 l8Uf2fkBYP5UWVUbWXlKPlmwmdQo/lAGYeHvi/lx3W4ORvIe6CRTeIS0q0DLPwSV
 H7iH8lnoFozIITt+6N+LhN9VME/Zpo8E/t2Wt47mkSkV/2hP6Adrgh5f4pz4KMcl
 hHQcAhi0/3DTEoGjczBDcTXMIt8nUPSwTnd1ktOaD0avRgKgiiLslvzjTxLMXRuw
 aDInx8uIMBswbEE0ZtG1aFrYZ54Y3DAm65n4aZfOPo3OlLjiosOqT1pvKWkpF/u1
 OYcQzVEdUnEwZKB9BYzkTFVtK3ptE/5nNFg4HkclZATrqvEfQ6I3EbM9tvtY6GV+
 BUUjxOthWq0Rnazd3BkOJvsepSndB1dOfxAunBk6m/r44shWWjLKGRI3jd+0QgW2
 UVd0hy5pC28OZelGgSAU0PVQyHYl/82pRu7UCpHVaOg9mvuwgURChr7ddGi9XWVG
 cMChFAumH/hvnQrRavONPUqaTjP62hRkOqjA/bvc3jFuAgFWqvSrc+z1AvqKw4Uz
 0ks+tjoHrQ839EZB0g/LDk7K8MDe8llvOk16gzqNxplQJe2WYaRZ9S0GD+3MC1Wz
 sSIyMsFLhfZJ2Z7TNOqLTPPW3jfoU3ntNzHUY8gCpTSh8DVkbtQ=
 =NlpZ
 -----END PGP SIGNATURE-----

Merge tag 'qcom-drivers-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.17

This introduces RPM power-domain support for the SM8450, SM6125 and
QCM2290 platforms. It them clean up the platform-based naming of the
resources definitions throughout the RPMh PD driver.

The last-level cache controller driver gains SM8350 support.

The RPM sleep stats driver gains support for several older systems that
had a slightly different memory layout for this information.

The socinfo gains SM8450, SM6350 and SM7227 definitions.

In addition to the DeviceTree binding updates related to these changes
new compatibles was added to describe the SM8450 and the Kryo 780 CPU.

Lastly a few typo and style fixes are introduced.

* tag 'qcom-drivers-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits)
  soc: qcom: rpmh-rsc: Fix typo in a comment
  soc: qcom: socinfo: Add SM6350 and SM7225
  dt-bindings: arm: msm: Don't mark LLCC interrupt as required
  dt-bindings: firmware: scm: Add SM6350 compatible
  dt-bindings: arm: msm: Add LLCC for SM6350
  soc: qcom: rpmhpd: Sort power-domain definitions and lists
  soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280
  soc: qcom: rpmhpd: Rename rpmhpd struct names
  soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao
  soc: qcom: socinfo: add SM8450 ID
  soc: qcom: rpmhpd: Add SM8450 power domains
  dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding
  soc: qcom: smem: Update max processor count
  dt-bindings: arm: qcom: Document SM8450 SoC and boards
  dt-bindings: firmware: scm: Add SM8450 compatible
  dt-bindings: arm: cpus: Add kryo780 compatible
  soc: qcom: rpmpd: Add support for sm6125
  dt-bindings: qcom-rpmpd: Add sm6125 power domains
  soc: qcom: aoss: constify static struct thermal_cooling_device_ops
  PM: AVS: qcom-cpr: Use div64_ul instead of do_div
  ...

Link: https://lore.kernel.org/r/20211221040452.3620633-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-21 13:42:52 +01:00
Konrad Dybcio 6fc61c39ee soc: qcom: llcc: Add configuration data for SM8350
Add LLCC configuration data for SM8350 SoC.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211121002050.36977-2-konrad.dybcio@somainline.org
2021-12-20 19:10:09 -06:00
Thomas Gleixner 7ad321a5ea soc: ti: ti_sci_inta_msi: Remove ti_sci_inta_msi_domain_free_irqs()
The function has no users and is pointless now that the core frees the MSI
descriptors, which means potential users can just use msi_domain_free_irqs().

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20211206210748.793119155@linutronix.de
2021-12-16 22:22:19 +01:00
Thomas Gleixner 89e0032ec2 soc: ti: ti_sci_inta_msi: Get rid of ti_sci_inta_msi_get_virq()
Just use the core function msi_get_virq().

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20211210221815.269468319@linutronix.de
2021-12-16 22:16:41 +01:00