Commit Graph

111442 Commits

Author SHA1 Message Date
Akinobu Mita 1e51714c81 MIPS: use for_each_sg()
This replaces the plain loop over the sglist array with for_each_sg()
macro which consists of sg_next() function calls.  Since MIPS doesn't
select ARCH_HAS_SG_CHAIN, it is not necessary to use for_each_sg() in
order to loop over each sg element.  But this can help find problems
with drivers that do not properly initialize their sg tables when
CONFIG_DEBUG_SG is enabled.

Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: akpm@linux-foundation.org
Cc: linux-mips@linux-mips.org
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9930/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:34 +02:00
Rafał Miłecki 78fc774479 MIPS: BCM47xx: Don't select BCMA_HOST_PCI
SoC may have non-Broadcom PCI device attached or one may want to use
totally different PCI driver.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/10537/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:33 +02:00
Rafał Miłecki 94a0535baf MIPS: BCM47xx: Add helper variable for storing NVRAM length
This simplifies code just a bit (also maybe makes it a bit more
intuitive?) and will allow us to stop storing header. Right now we copy
whole NVRAM including its header to the internal buffer. It is not
needed to store a header as we don't access all these details like CRC,
flags, etc. The next improvement that should follow is copying only the
real contents.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: Arend van Spriel <arend@broadcom.com>
Cc: Hante Meuleman <meuleman@broadcom.com>
Patchwork: https://patchwork.linux-mips.org/patch/10535/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:32 +02:00
Ralf Baechle cb2224d7c4 MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
allocate_irqno, free_irqno and alloc_legacy_irqno are a simple allocator
for interrupt numbers from the days when the numer of interrupts was still
fixed to NR_IRQS.  This was necessary for the SGI IP27 architecture which
with its flexible architecture and possibly large number of interrupts
doesn't easily fit into the old pattern.  These days there are better
alternatives.

Move the allocation code from the arch generic code to the only platform
using it, the SGI IP27 aka Origin 200/2000, Onyx 2.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:31 +02:00
Leonid Yegoshin 6f6ed48265 MIPS: Replace smp_mb with release barrier function in unlocks.
Repleace smp_mb() in arch_write_unlock() and __clear_bit_unlock() to
smp_mb__before_llsc() call which does "release" barrier functionality.

It seems like it was missed in commit f252ffd50c
during introduction of "acquire" and "release" semantics.

[ralf@linux-mips: The original patch submission was labelled a fix but
actually it replaces a barrier with another less restrictive type of
barrier so it doesn't fix any ill behaviour but rather squeezes out a
tad better performance.  Further improvments will be possible once
smp_release() has been merged.]

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: benh@kernel.crashing.org
Cc: will.deacon@arm.com
Cc: linux-kernel@vger.kernel.org
Cc: markos.chandras@imgtec.com
Cc: macro@linux-mips.org
Cc: Steven.Hill@imgtec.com
Cc: alexander.h.duyck@redhat.com
Cc: davem@davemloft.net
Patchwork: https://patchwork.linux-mips.org/patch/10507/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:30 +02:00
Paul Burton 5f93ef5cfb MIPS: i8259: DT support
Support probing the i8259 programmable interrupt controller, as found on
the Malta board, and using its interrupts via device tree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/10114/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:29 +02:00
Paul Burton e8823d26b4 MIPS: Malta: Basic DT plumbing
Build a DT for the Malta platform into the kernel, load it & probe
devices from it. The DT is essentially empty at this point, devices
will be added in further patches.

[ralf@linux-mips.org: Fixed conflicts.]

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/10119/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:29 +02:00
Paul Burton 56d4c99b84 MIPS: include errno.h for ENODEV in mips-cm.h
A later patch in this series will include mips-cm.h but does not require
errno.h. This leads to a build failure with ENODEV undeclared. Include
errno.h from mips-cm.h to pull in the appropriate definition and avoid
the build failure.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/10113/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:28 +02:00
Paul Burton 921d55e32d MIPS: Define GCR_GIC_STATUS register fields
Add definitions for the GICEX field in the GCR_GIC_STATUS register to
mips-cm.h for use in a later patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/10112/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:26 +02:00
Markos Chandras 266a88e220 MIPS: BPF: Introduce BPF ASM helpers
This commit introduces BPF ASM helpers for MIPS and MIPS64 kernels.
The purpose of this patch is to twofold:

1) We are now able to handle negative offsets instead of either
falling back to the interpreter or to simply not do anything and
bail out.

2) Optimize reads from the packet header instead of calling the C
helpers

Because of this patch, we are now able to get rid of quite a bit of
code in the JIT generation process by using MIPS optimized assembly
code. The new assembly code makes the test_bpf testsuite happy with
all 60 test passing successfully compared to the previous
implementation where 2 tests were failing.
Doing some basic analysis in the results between the old
implementation and the new one we can obtain the following
summary running current mainline on an ER8 board (+/- 30us delta is
ignored to prevent noise from kernel scheduling or IRQ latencies):

Summary: 22 tests are faster, 7 are slower and 47 saw no improvement

with the most notable improvement being the tcpdump tests. The 7 tests
that seem to be a bit slower is because they all follow the slow path
(bpf_internal_load_pointer_neg_helper) which is meant to be slow so
that's not a problem.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: netdev@vger.kernel.org
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Daniel Borkmann <dborkman@redhat.com>
Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: netdev@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/10530/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:25 +02:00
Markos Chandras beaf70b8b7 MIPS: BPF: Use BPF register names to describe the ABI
Use the BPF register names instead of the arch register names to
document how the ABI is structured.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: netdev@vger.kernel.org
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Daniel Borkmann <dborkman@redhat.com>
Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/10529/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:24 +02:00
Markos Chandras 79a8855c4a MIPS: BPF: Move register definition to the BPF header
The registers will be used by a subsequent patch introducing
ASM helpers so move them to a common header.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: netdev@vger.kernel.org
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Daniel Borkmann <dborkman@redhat.com>
Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/10528/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:24 +02:00
Markos Chandras 5e0c5610ea MIPS: net: BPF: Replace RSIZE with SZREG
The RSZIE was used to determine the register width but MIPS
already defines SZREG so use that instead.

Cc: netdev@vger.kernel.org
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Daniel Borkmann <dborkman@redhat.com>
Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: netdev@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/10526/
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:23 +02:00
Markos Chandras ad152bd698 MIPS: BPF: Free up some callee-saved registers
Move the two scratch registers from s0 and s1 to t4 and t5 in order
to free up some callee-saved registers. We will use these callee-saved
registers to store some permanent data on them in a subsequent patch.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: netdev@vger.kernel.org
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Daniel Borkmann <dborkman@redhat.com>
Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/10525/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:22 +02:00
Joshua Kinard de5792a4ec MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers
This is the first patch of two to clean up/update the Xtalk detection
code used by IP27 with some of the code used in the IP30 port.

This specific patch adds Xtalk widget manufacturer and widget device
numbers to arch/mips/include/asm/xtalk/widget.h

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/10174/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:21 +02:00
Paul Burton 12060666f5 MIPS: Optimise non-EVA kernel user memory accesses
Commits ac1d8590d3 (MIPS: asm: uaccess: Use EVA instructions
wrappers), 05c6516005 (MIPS: asm: uaccess: Add EVA support to
copy_{in, to,from}_user) & e3a9b07a9c (MIPS: asm: uaccess: Add EVA
support for str*_user operations) added checks to various user memory
access functions & macros in order to determine whether to perform
standard memory accesses or their EVA userspace equivalents. In kernels
built without support for EVA these checks are entirely redundant. Avoid
emitting them & allow the compiler to optimise out the EVA userspace
code in such kernels by checking config_enabled(CONFIG_EVA).

This reduces the size of a malta_defconfig kernel built using GCC 4.9.2
by approximately 33KB (from 5995072 to 5962304 bytes).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/10165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:20 +02:00
Ben Hutchings df115f3ee9 MIPS: Octeon: Set OHCI and EHCI MMIO byte order to match CPU
The Octeon OHCI is now supported by the ohci-platform driver, and
USB_OCTEON_OHCI is marked as deprecated.  However, it is currently
still necessary to enable it in order to select
USB_OHCI_BIG_ENDIAN_MMIO.  Make CPU_CAVIUM_OCTEON select that as well,
so that USB_OCTEON_OHCI is really obsolete.

The old ohci-octeon and ehci-octeon drivers also only enabled big-endian
MMIO in case the CPU was big-endian.  Make the selections of
USB_EHCI_BIG_ENDIAN_MMIO and USB_OHCI_BIG_ENDIAN_MMIO conditional, to
match this.

Fixes: 2193dda5ee ("USB: host: Remove ehci-octeon and ohci-octeon drivers")
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: linux-mips@linux-mips.org
Cc: David Daney <david.daney@cavium.com>
Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
Cc: Paul Martin <paul.martin@codethink.co.uk>
Patchwork: https://patchwork.linux-mips.org/patch/10178/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:19 +02:00
Jonas Gorski ca668a2da4 MIPS: BMIPS: Accept UHI interface for passing a dtb
Detect and use passed dtb address using the UHI interface. This allows for
booting with a vmlinux.bin appended dtb instead of using a built-in one.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: James Hartley <James.Hartley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9742/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:17 +02:00
Jonas Gorski 0e12f4a3ab MIPS: BMIPS: Build all dtbs if no builtin dtb
Build all available dtbs to allow them to be appended to the resulting
kernel in case there is no builtin dtb.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: James Hartley <James.Hartley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9740/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:16 +02:00
Jonas Gorski c0b4e10144 MIPS: Add support for vmlinuz.bin appended dtb
Add support for detecting a vmlinuz.bin appended dtb and overriding
the boot arguments to match the UHI interface.

To ensure _edata / __apendend_dtb points to the actual end of the
binary, align the data section to 16 bytes instead of the address
cursor.

Due to ld.script not going through the preprocessor, we can't check
for MIPS_ZBOOT_APPENDED_DTB being enabled, so always reserve space
for it. It should have no consequences for booting without it enabled
except 1 MiB more ram usage during the uncompressing stage.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: James Hartley <James.Hartley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9741/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:15 +02:00
Jonas Gorski 1da8f1798e MIPS: Add support for vmlinux.bin appended dtb
Add support for detecting a vmlinux.bin appended dtb and overriding
the boot arguments to match the UHI interface.

Due to the PERCPU section being empty for !SMP, but still modifying
the current address by aligning it to the page size, do not define
it for !SMP builds to allow __appended_dtb to still point to
the actual end of the data.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: James Hartley <James.Hartley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9739/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:14 +02:00
Rob Herring 01306aeadd MIPS: prepare for user enabling of CONFIG_OF
In preparation to allow users to enable DeviceTree without arch or
machine selecting it, we need to fix build errors on MIPS. When
CONFIG_OF is enabled, device_tree_init cannot be resolved. This is
trivially fixed by using CONFIG_USE_OF instead of CONFIG_OF for prom.h.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:14 +02:00
Joshua Kinard 8d5ded16ee MIPS: R12000: Enable branch prediction global history
The R12000 added a new feature to enhance branch prediction called
"global history".  Per the Vr10000 Series User Manual (U10278EJ4V0UM),
Coprocessor 0, Diagnostic Register (22):

"""
If bit 26 is set, branch prediction uses all eight bits of the global
history register.  If bit 26 is not set, then bits 25:23 specify a count
of the number of bits of global history to be used. Thus if bits 26:23
are all zero, global history is disabled.

The global history contains a record of the taken/not-taken status of
recently executed branches, and when used is XOR'ed with the PC of a
branch being predicted to produce a hashed value for indexing the BPT.
Some programs with small "working set of conditional branches" benefit
significantly from the use of such hashing, some see slight performance
degradation.
"""

This patch enables global history on R12000 CPUs and up by setting bit
26 in the branch prediction diagnostic register (CP0 $22) to '1'.  Bits
25:23 are left alone so that all eight bits of the global history
register are available for branch prediction.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:13 +02:00
Joshua Kinard 0ebb2f4159 MIPS: IP27: Update/restructure CPU overrides
Inspired by Maciej's recent patch to update DEC cpu-feature-overrides.h,
I updated IP27's as well to disable features known to not apply to the
IP27 platform or the R10K-series of CPUs.

Before:
   text    data     bss     dec     hex filename
8616648  463200  472240 9552088  91c0d8 vmlinux

After:
   text    data     bss     dec     hex filename
8592256  471392  472240 9535888  918190 vmlinux

I believe the increase in the size of the data section is for the same
reasons as in the DEC patch.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:13 +02:00
Paul Gortmaker 85cc028817 mips: make loongsoon serial driver explicitly modular
The file looks as if it is non-modular, but it piggy-backs
off CONFIG_SERIAL_8250 which is tristate.  If set to "=m"
we will get this after the init/module header cleanup:

arch/mips/loongson/common/serial.c:76:1: error: data definition has no type or storage class [-Werror]
arch/mips/loongson/common/serial.c:76:1: error: type defaults to 'int' in declaration of 'device_initcall' [-Werror=implicit-int]
arch/mips/loongson/common/serial.c:76:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/loongson/common/serial.c:58:19: error: 'serial_init' defined but not used [-Werror=unused-function]
cc1: all warnings being treated as errors
make[3]: *** [arch/mips/loongson/common/serial.o] Error 1

Make it clearly modular, and add a module_exit function,
so that we avoid the above breakage.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:12 +02:00
Sergei Shtylyov 52ea7bff5d MIPS: Get rid of 'kgdb_early_setup' cruft.
Commit 854700115ecf ([MIPS] kgdb: add arch support for the kernel's kgdb core)
added the 'kgdb_early_setup' flag to avoid  calling trap_init() and init_IRQ()
the second time, however the code that called these functions earlier,  from
kgdb_arch_init(), had been already removed by that  time,  so the flag never
served any useful purpose. Remove the related code along with ugly #ifdef'ery
at last.

[ralf@linux-mips.org: Folded in Guenter Roeck's fix.]

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Patchwork: https://patchwork.linux-mips.org/patch/10501/
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Patchwork: https://patchwork.linux-mips.org/patch/10533/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:10 +02:00
Alban Bedel a5fcc6522f MIPS: Add basic support for the TL-WR1043ND version 1
Add a DTS for TL-WR1043ND version 1 and allow to have it built in the
kernel to circumvent the broken u-boot found on these boards.
Currently only the UART, LEDs and buttons are supported.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:10 +02:00
Alban Bedel 2ddf3a7922 MIPS: ath79: Add OF support to the GPIO driver
Replace the simple GPIO chip registration by a platform driver
and make ath79_gpio_init() just register the device.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:09 +02:00
Alban Bedel 6451af0220 MIPS: ath79: Add OF support to the clocks
Allow using the SoC clocks in the device tree.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:06 +02:00
Alban Bedel b29e8b87d5 MIPS: ath79: Add OF support to the IRQ controllers
Add OF support for the CPU and MISC interrupt controllers of most
supported ATH79 devices.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:03 +02:00
Alban Bedel 03c8c407a8 MIPS: ath79: Add basic device tree support
Add the bare minimum to load a device tree.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:01 +02:00
Hante Meuleman 55cab93bcf mips: bcm47xx: allow retrieval of complete nvram contents
Host platforms such as routers supported by OpenWrt can
support NVRAM reading directly from internal NVRAM store.
The brcmfmac for one requires the complete nvram contents
to select what needs to be sent to wireless device.

Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Hante Meuleman <meuleman@broadcom.com>
Reviewed-by: Arend Van Spriel <arend@broadcom.com>
Reviewed-by: Franky (Zhenhui) Lin <frankyl@broadcom.com>
Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: Daniel (Deognyoun) Kim <dekim@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10093/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:54:00 +02:00
Huacai Chen 30ad29bb48 MIPS: Loongson: Naming style cleanup and rework
Currently, code of Loongson-2/3 is under loongson directory and code of
Loongson-1 is under loongson1 directory. Besides, there are Kconfig
options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is
very ugly and confusing. Since Loongson-2/3 are both 64-bit general-
purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names
and Kconfig symbols from loongson/loongson1 to loongson64/loongson32.

[ralf@linux-mips.org: Resolve a number of simple conflicts.]

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9790/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:59 +02:00
James Hogan abcc82b19f MIPS: Malta: Select 32bit DMA zone for 64-bit kernels
Enable the 32-bit DMA zone for 64-bit Malta kernels so that devices with
32-bit coherent DMA masks aren't constrained to the low 16MB DMA zone,
which can easily be exhausted when there is lots of static kernel data
due to lock and RCU debugging.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9890/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:57 +02:00
James Hogan 8fe4908b83 MIPS: tlbex: Avoid unnecessary _PAGE_PRESENT shifts
Commit c5b367835c ("MIPS: Add support for XPA.") added generation of a
shift by _PAGE_PRESENT_SHIFT in build_pte_present() and
build_pte_writable(), however except for the XPA case this is always
zero making it unnecessary.

Make the shift conditional upon _PAGE_PRESENT_SHIFT being non-zero to
save an instruction in those cases.

Fixes: c5b367835c ("MIPS: Add support for XPA.")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9889/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:55 +02:00
James Hogan a3ae565a13 MIPS: tlbex: Fix broken offsets on r2 without XPA
Commit c5b367835c ("MIPS: Add support for XPA.") changed
build_pte_present() and build_pte_writable() to assume a constant offset
of _PAGE_READ and _PAGE_WRITE relative to _PAGE_PRESENT, however this is
no longer true for some MIPS32R2 builds since commit be0c37c985
("MIPS: Rearrange PTE bits into fixed positions.") which moved the
_PAGE_READ PTE bit away from the _PAGE_PRESENT bit, with the _PAGE_WRITE
bit falling into its place.

Make use of the _PAGE_READ and _PAGE_WRITE definitions to calculate the
correct mask to apply instead of hard coding 3 (for _PAGE_PRESENT |
_PAGE_READ) or 5 (for _PAGE_PRESENT | _PAGE_WRITE).

Fixes: c5b367835c ("MIPS: Add support for XPA.")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9888/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:55 +02:00
James Hogan 8e748c8d09 MIPS: Fix KVM guest fixmap address
KVM guest kernels for trap & emulate run in user mode, with a modified
set of kernel memory segments. However the fixmap address is still in
the normal KSeg3 region at 0xfffe0000 regardless, causing problems when
cache alias handling makes use of them when handling copy on write.

Therefore define FIXADDR_TOP as 0x7ffe0000 in the guest kernel mapped
region when CONFIG_KVM_GUEST is defined.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/9887/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:54 +02:00
Dan Haab 24f2970fd3 MIPS: BCM47XX: Support Luxul XWR-1750 board
Signed-off-by: Dan Haab <dhaab@luxul.com>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Dan Haab <dhaab@luxul.com>
Patchwork: https://patchwork.linux-mips.org/patch/9831/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:53 +02:00
Alban Bedel 411520af8e MIPS: ath79: Use the common clk API
Make the code simpler and open the way for device tree clocks.

[ralf@linux-mips.org: Resolved conflict with 2a552da6 (MIPS/IRQCHIP: Move
irq_chip from arch/mips to drivers/irqchip.)]

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9774/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:51 +02:00
Alban Bedel 24b0e3e84f MIPS: ath79: Improve the DDR controller interface
The DDR controller need to be used by the IRQ controller to flush
the write buffer of some devices before running the IRQ handler.
It is also used by the PCI controller to setup the PCI memory windows.

The current interface used to access the DDR controller doesn't
provides any useful abstraction and simply rely on a shared global
pointer.

Replace this by a simple API to setup the PCI memory windows and use
the write buffer flush independently of the SoC type. That remove the
need for the shared global pointer, simplify the IRQ handler code.

[ralf@linux-mips.org: Folded in Alban Bedel's follup fix.]

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9773/
Patchwork: http://patchwork.linux-mips.org/patch/10543/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:51 +02:00
Alban Bedel 626a0695a6 MIPS: ath79: Correctly name the defines for the PLL_FB register
This register is named PLL_FB and is not a divider but a multiplier.
To make things less confusing rename the ARxxxx_PLL_DIV_SHIFT and
ARxxxx_PLL_DIV_MASK macros to ARxxxx_PLL_FB_SHIFT and
ARxxxx_PLL_FB_MASK.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9772/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:49 +02:00
Alban Bedel da628e8b8b MIPS: ath79: Enable ZBOOT support
ZBOOT is working fine, so allow using it.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9770/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:48 +02:00
Jiang Liu 25aae56137 MIPS, IRQ: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
already have a pointer to corresponding irq_desc.

Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Acked-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Christoph Lameter <cl@linux.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-acpi@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10086/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:47 +02:00
Krzysztof Kozlowski 2e93f68408 MIPS: Alchemy: Remove unneeded cast removing const
Parent names in clock init data is now array of const pointers to const
strings so the cast is not needed.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Barry Song <baohua@kernel.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Inki Dae <inki.dae@samsung.com>
Patchwork: https://patchwork.linux-mips.org/patch/9903
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:46 +02:00
Paul Gortmaker a2d25e63ee MIPS: tlbex.c: Remove new instance of __cpuinitdata that crept back in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a new instance was added in commit c5b367835c
("MIPS: Add support for XPA.")

Since we want to clobber the stubs soon, get this removed now.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9894/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:45 +02:00
Paul Gortmaker 9a8f4ea034 MIPS: c-r4k: Remove legacy __cpuinit section that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a new instance was added in commit 4caa906ee9
("MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functions")

Since we want to clobber the stubs soon, get this removed now.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9893/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:44 +02:00
Paul Gortmaker b1f7e11290 MIPS: BCM77xx: Remove legacy __cpuinit{,data} sections that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a few more crept in as of commit 6ee1d93455
("MIPS: BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)")

Since we want to clobber the stubs soon, get this removed now.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9892/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:42 +02:00
Paul Gortmaker 361d0f78ac MIPS: ATH25: Remove legacy __cpuinit section that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However this one crept back in as of commit 43cc739fd9
("MIPS: ath25: add common parts")

Since we want to clobber the stubs soon, get this removed now.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9891/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:42 +02:00
Andrew Bresticker 644238ae81 MIPS: Pistachio: Enable USB PHY driver in defconfig
Update pistachio_defconfig to enable Pistachio's USB PHY driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9729/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:39 +02:00
Ezequiel Garcia 018f62ee20 MIPS: Pistachio: Support 8250-based early printk
Pistachio SoCs are capable of early printk with generic 8250 support,
so let's select the options to enable it.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9913/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:36 +02:00
Jaedon Shin 8bac078c5d MIPS: BMIPS: dts: Add uart device nodes to bcm7xxx platforms
Add two uart device nodes known as the uart1 and uart2 for the bcm7xxx
platforms.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9991/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:35 +02:00
Florian Fainelli 380e4270f5 MIPS: BMIPS: Add support for Broadcom BCM97435SVMB
Add a DTS file and Kconfig entry for the BCM97435SVMB evaluation board
using bcm7435.dtsi as an example.

The current code needs some tweaking to allow us to use the
dual-threaded dual BMIPS5200 CPUs, so for now we limit ourselves to
allowing just a single CPU to be booted.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: cernekee@chromium.org
Cc: Steven.Hill@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/9972/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:34 +02:00
Florian Fainelli e4c7d00965 MIPS: BMIPS: Add BCM7435 dtsi
Add the bare minimum required to boot a BCM7435-based system:

- BMIPS5200 CPU nodes
- Level 1 and 2 interrupt controllers
- UARTs
- EHCI/OHCI controllers

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: cernekee@chromium.org
Cc: Steven.Hill@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/9971/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:32 +02:00
Florian Fainelli 3fbbb2ee36 MIPS: BCM63xx: Utilize asm/bmips-spaces.h
Since BCM63xx runs on BMIPS3300 which requires the use of a FIXADDR_TOP
to avoid collisions with the SBR, utilize asm/bmips-spaces.h which
defines FIXADDR_TOP for us now.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: cernekee@chromium.org
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/9969/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:32 +02:00
Florian Fainelli 09a50cc727 MIPS: BMIPS: Define BMIPS_FIXADDR_TOP in asm/bmips-spaces.h
The FIXADDR_TOP value used by mach-bmips is in fact required whenever we
run on BMIPS3300 BMIPS CPUs, and is not machine, but CPU-specific, move
this constant to asm/bmips-spaces.h and use it in mach-bmips/spaces.h.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: cernekee@chromium.org
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/9968/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:30 +02:00
Paul Burton 0752f92934 MIPS: ingenic: Initial MIPS Creator CI20 support
Add an initial device tree for the Ingenic JZ4780 based MIPS Creator
CI20 board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10162/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:28 +02:00
Paul Burton 5b9cdd2449 MIPS: ingenic: Initial JZ4780 support
Support the Ingenic JZ4780 SoC using the existing code under
arch/mips/jz4740 now that it has been generalised sufficiently.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10164/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:26 +02:00
Paul Burton 8838245d76 MIPS: JZ4740: use Ingenic SoC UART driver
Remove the serial support from arch/mips/jz4740 & make use of the new
Ingenic SoC UART driver. This is done for both regular & early console
output.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Apelete Seketeli <apelete@seketeli.net>
Cc: Alexandre Courbot <gnurou@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10160/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:26 +02:00
Paul Burton 6ec127fb3c MIPS: JZ4740: only detect RAM size if not specified in DT
Allow a devicetree to specify the memory present in the system rather
than probing it from the memory controller. This both saves the probing
for systems where the amount of memory is fixed, and will simplify the
bringup of later Ingenic SoCs where the memory controller register
layout differs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10163/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:22 +02:00
Paul Burton 1237496af3 MIPS: JZ4740: remove clock.h
The only thing remaining in arch/mips/jz4740/clock.h is declarations of
the jz4740_clock_{suspend,resume} functions. Move these to
arch/mips/include/asm/mach-jz4740/clock.h for consistency with similar
functions, and remove the redundant arch/mips/jz4740/clock.h header.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10156/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:21 +02:00
Paul Burton 50d893ff72 MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu
The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move the jz4740_clock_{suspend,resume} functions there for
such consistency. The arch/mips/jz4740/clock.c file now contains nothing
more of use & so is removed.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10158/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:19 +02:00
Paul Burton ed286ca5d6 MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu
The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions
there for such consistency.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10154/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:18 +02:00
Paul Burton 41dd641e9a MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move jz4740_clock_set_wait_mode for such consistency.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10153/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:17 +02:00
Paul Burton ff1930c6bd MIPS,clk: migrate JZ4740 to common clock framework
Migrate the JZ4740 & the qi_lb60 board to use common clock framework
via the new Ingenic SoC CGU driver. Note that the JZ4740-specific
debugfs code is removed since common clock framework provides its own
debug capabilities.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Co-authored-by: Paul Cercueil <paul@crapouillou.net>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Fabian Frederick <fabf@skynet.be>
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10151/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:15 +02:00
Paul Burton e06b86a33a MIPS: JZ4740: replace use of jz4740_clock_bdata
Replace uses of the jz4740_clock_bdata struct with calls to clk_get_rate
for the appropriate clock. This is in preparation for migrating the
clocks towards common clock framework & devicetree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: Apelete Seketeli <apelete@seketeli.net>
Patchwork: https://patchwork.linux-mips.org/patch/10149/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:12 +02:00
Paul Burton 1f4b840983 MIPS: JZ4740: Call jz4740_clock_init earlier
Call jz4740_clock_init before any uses of jz4740_clock_bdata occur. This
is in preparation for replacing uses of that struct with calls to
clk_get_rate, which will allow the clocks to be migrated towards common
clock framework & devicetree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10148/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:11 +02:00
Paul Burton 44e08e7099 MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip
Move the driver for Ingenic SoC interrupt controllers into
drivers/irqchip where it belongs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10147/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:10 +02:00
Paul Burton 24ccfa06b7 MIPS: JZ4740: support newer SoC interrupt controllers
Allow the interrupt controllers of the JZ4770, JZ4775 & JZ4780 SoCs to
be probed via devicetree, supporting the 64 interrupts they provide.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10155/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:07 +02:00
Paul Burton 2da018849f MIPS: JZ4740: Avoid JZ4740-specific naming
Rename the functions including jz4740 in their names to be more generic
in preparation for supporting further SoCs, and for moving this
interrupt controller code to drivers/irqchip.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Patchwork: https://patchwork.linux-mips.org/patch/10146/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:06 +02:00
Paul Burton 3aa94590e7 MIPS: JZ4740: read intc base address from DT
Read the base address of the SoC interrupt controller from the device
tree rather than relying upon the JZ4740_INTC_BASE_ADDR macro, in order
to remove the dependency on the asm/mach-jz4740/base.h header.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10145/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:05 +02:00
Paul Burton ad68f8d3c2 MIPS: JZ4740: define IRQ numbers based on number of intc IRQs
For interrupts numbered after those of the interrupt controller, define
their numbers based upon the number of interrupts provided by the SoC
interrupt controller. This is in preparation for supporting newer
Ingenic SoCs which provide more interrupts.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:04 +02:00
Paul Burton 943d69c6c2 MIPS: JZ4740: support >32 interrupts
On newer Ingenic SoCs the interrupt controller supports more than 32
interrupts, which it does by duplicating the registers at intervals
of 0x20 bytes within its address space. Add support for an arbitrary
number of interrupts using multiple generic chips, and provide the
number of chips to register from the interrupt controller probe
function.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10141/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:03 +02:00
Paul Burton fe778ece8e MIPS: JZ4740: Remove jz_intc_base global
Avoid the need for the global variable jz_intc_base by introducing a
struct ingenic_intc_data and passing it around as the IRQ handler data.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10144/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:02 +02:00
Paul Burton 2aabd281d6 MIPS: JZ4740: drop intc debugfs code
The debugfs code becomes a nuisance when attempting to avoid globals,
since the interrupt controller probe function run too early for it to be
safe to create the debugfs files. Drop it.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10139/
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:02 +02:00
Paul Burton 638c885185 MIPS: JZ4740: register an irq_domain for the interrupt controller
When probing the interrupt controller, register an IRQ domain such
that the interrupts can be translated by devicetree code & thus used
from devicetree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10140/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:53:00 +02:00
Paul Burton 69ce4b2288 MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
Rather than hardcoding the IRQ number used to cascade interrupts from
the SoC interrupt controller to the CPU interrupt controller, read that
IRQ number from the DT describing the system.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10137/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:59 +02:00
Paul Burton adbdce77cc MIPS: JZ4740: probe interrupt controller via DT
Declare the JZ4740 interrupt controller for probe via DT using the
standard irqchip_init function, and make use of that function to probe
the controller by adding the appropriate node to the JZ4740 dtsi.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10135/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:58 +02:00
Paul Burton 0e81db8f5b MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c
In preparation for moving the JZ4740 interrupt controller driver to
drivers/irqchip, move arch_init_irq into setup.c such that everything
remaining in irq.c is related to said JZ4740 interrupt controller.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10136/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:56 +02:00
Paul Burton 2974a35657 MIPS: JZ4740: use generic plat_irq_dispatch
Make use of the generic plat_irq_dispatch function introduced by commit
85f7cdacbb "MIPS: Provide a generic plat_irq_dispatch", in order to
reduce unnecessary code duplication.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10138/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:55 +02:00
Paul Burton 8e8261eb6a MIPS: JZ4740: probe CPU interrupt controller via DT
Use the generic irqchip_init function to probe irqchip drivers using DT,
and add the appropriate node to the JZ4740 devicetree in place of the
call to mips_cpu_irq_init.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Patchwork: https://patchwork.linux-mips.org/patch/10166/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:54 +02:00
Ralf Baechle 67e38cf293 MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.
While at it, rename it because in drivers/irqchip no longer every CPU is
a MIPS.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:50 +02:00
Paul Burton ffb1843d05 MIPS: JZ4740: require & include DT
Require a DT for JZ4740 based systems, and add a stub one for the
qi_lb60 (Ben NanoNote) board. Devices will be migrated to being probed
via this DT over time.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10132/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:49 +02:00
Paul Burton 252617a4ab MIPS: ingenic: Add newer vendor IDs
Ingenic have actually varied the vendor/company ID of the XBurst cores
across their range of SoCs, whilst keeping the product ID & revision
constant... Add definitions for vendor IDs known to be used in some of
Ingenic's newer SoCs, and handle them in the same way as the existing
Ingenic vendor ID from the JZ4740.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Co-authored-by: Paul Cercueil <paul@crapouillou.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-kernel@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/10128/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:48 +02:00
Paul Burton de361e8bb9 MIPS: JZ4740: introduce CONFIG_MACH_INGENIC
In preparation for supporting Ingenic SoCs other than the JZ4740,
introduce MACH_INGENIC to Kconfig & move MACH_JZ4740 to a separate
entry selected by the board when appropriate. This allows MACH_INGENIC
to be used to enable things generic across Ingenic SoCs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Patchwork: https://patchwork.linux-mips.org/patch/10130/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:47 +02:00
Maciej W. Rozycki bc4f12e639 MIPS: DEC: Update CPU overrides
Update CPU overrides for the DEC port with the recent additions, shaving
off some effectively dead code:

   text    data      bss      dec     hex filename
5586952  233132  5990368 11810452  b43694 vmlinux.32-old
5581248  233140  5990368 11804756  b42054 vmlinux.32-new

   text    data      bss      dec     hex filename
6036936  356648 10756544 17150128 105b0b0 vmlinux.64-old
6029896  360752 10756544 17147192 105a538 vmlinux.64-new

The data size increase is due to the special alignment requirement of
`init_thread_union' aka `.data..init_task' moving it up to the nearest
page boundary and making the amount of padding at its front rely on how
far within a page text ends.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10197/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:44 +02:00
Brian Norris cc23cafe2b MIPS: netlogic: remove unnecessary MTD partition probe specification
The cmdlinepart parser is already supported in the default probe.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mtd@lists.infradead.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10071/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:43 +02:00
Maciej W. Rozycki 9a20b09285 MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation
Replace an explicit barrier with a useful processor instruction in TLB
invalidation, following several other such cases elsewhere in
`tlb-r3k.c'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10196/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:41 +02:00
Maciej W. Rozycki 3bcb03f3a7 MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'
Move the initialisation of the CP0.Wired register implemented by Toshiba
TX3922 and TX3927 processors from `tx39_cache_init' to `tlb_init' where
it belongs, correcting code structure and making sure initialisation
does not rely on `tx39_cache_init' being called before `tlb_init' to
work correctly.

Make `r3k_have_wired_reg' static as it's no longer externally referred
to; remove a stale declaration too.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10195/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:41 +02:00
Maciej W. Rozycki dbfbf60f4a MIPS: tlb-r3k: Also invalidate wired TLB entries on boot
Most R3k processor implementations have their 8 first TLB entries fixed
as wired, so we always skip them in TLB invalidation.  That however
means any leftover entries present there at boot will stay throughout
the life of the kernel, unless replaced with new ones.

So rename `local_flush_tlb_all' to `local_flush_tlb_from' and make it
accept the TLB entry to start from.  Then use 0 initially at bootstrap,
and the first regular entry later on, bypassing any wired entries.
Wrap the latter arrangement into a new `local_flush_tlb_all' entry
point.

There is no need to disable interrupts in the call made from `tlb_init'
because it's made before the interrupt subsystem has been initialised;
this is also true for secondary processors, should we ever support R3k
SMP.  So move this piece of code to new `local_flush_tlb_all'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10194/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:39 +02:00
James Hogan 24ca1d9896 MIPS: dump_tlb: Take XPA into account
XPA extends the physical addresses on MIPS32, including the EntryLo
registers. Update dump_tlb() to concatenate the PFNX field from the high
end of the EntryLo registers (as read by mfhc0).

The width of physical and virtual addresses are also separated to show
only 8 nibbles of virtual but 11 nibbles of physical with XPA.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10077/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:39 +02:00
James Hogan c2bc435e4f MIPS: dump_tlb: Take RI/XI bits into account
The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:

Index: 253 pgmask=16kb va=77b18000 asid=75
        [pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]

The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.

Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:

Index: 226 pgmask=16kb va=77be0000 asid=79
        [ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]

Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10080/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:38 +02:00
James Hogan decebccd76 MIPS: dump_tlb: Take EHINV bit into account
The EHINV bit in EntryHi allows a TLB entry to be properly marked
invalid so that EntryHi doesn't have to be set to a unique value to
avoid machine check exceptions due to multiple matching entries.

Unfortunately dump_tlb() doesn't take this into account so it will print
all the uninteresting invalid TLB entries if the current ASID happens to
be 00. Therefore add a condition to skip entries which are marked
invalid with the EHINV bit.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10076/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:36 +02:00
James Hogan 48269c78fb MIPS: dump_tlb: Take global bit into account
The TLB only matches the ASID when the global bit isn't set, so
dump_tlb() shouldn't really be skipping global entries just because the
ASID doesn't match. Fix the condition to read the TLB entry's global bit
from EntryLo0. Note that after a TLB read the global bits in both
EntryLo registers reflect the same global bit in the TLB entry.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10079/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:35 +02:00
James Hogan d7f5499dc2 MIPS: dump_tlb: Make use of EntryLo bit definitions
Make use of recently added EntryLo bit definitions in mipsregs.h when
dumping TLB contents.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10075/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:34 +02:00
James Hogan d1ce483e45 MIPS: dump_tlb: Refactor TLB matching
Refactor the TLB matching code in dump_tlb() slightly so that the
conditions which can cause a TLB entry to be skipped can be more easily
extended. This should prevent the match condition getting unwieldy once
it is updated to take further conditions into account.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10081/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:33 +02:00
James Hogan 137877e432 MIPS: dump_tlb: Use tlbr hazard macros
Use the new tlb read hazard macros from <asm/hazards.h> rather than the
local BARRIER() macro which uses 7 ops regardless of the kernel
configuration.

We use mtc0_tlbr_hazard for the hazard between mtc0 to the index
register and the tlbr, and tlb_read_hazard for the hazard between the
tlbr and the mfc0 of the TLB registers written by tlbr.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10074/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:32 +02:00
James Hogan 8ab6abcb6a MIPS: mipsregs.h: Add EntryLo bit definitions
Add definitions for EntryLo register bits in mipsregs.h. The R4000
compatible ones are prefixed MIPS_ENTRYLO_ and the R3000 compatible ones
are prefixed R3K_ENTRYLO_.

These will be used in later patches.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/10073/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:31 +02:00
James Hogan e50f0e3135 MIPS: hazards: Add hazard macros for tlb read
Add hazard macros to <asm/hazards.h> for the following hazards around
tlbr (TLB read) instructions, which are used in TLB dumping code and
some KVM TLB management code:

- mtc0_tlbr_hazard
  Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
  all cases on the assumption that tlbr always has similar data user
  timings to tlbw.

- tlb_read_hazard
  Between tlbr and mfc0 (various TLB registers). This is copied from
  tlbw_use_hazard in all cases on the assumption that tlbr has similar
  data writer characteristics to tlbw, and mfc0 has similar data user
  characteristics to loads and stores.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10078/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:28 +02:00
James Hogan d1e9a4f547 MIPS: Add SysRq operation to dump TLBs on all CPUs
Add a MIPS specific SysRq operation to dump the TLB entries on all CPUs,
using the 'x' trigger key.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10072/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:27 +02:00
Petri Gynther 37dd3818d1 MIPS: traps: print Exception Code in __show_regs()
Print Exception Code when printing the Cause register.

Signed-off-by: Petri Gynther <pgynther@google.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9998/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:26 +02:00
Rafał Miłecki 2623899459 MIPS: BCM47xx: Read board info for all bcma buses
Extra bcma buses may be totally different models, see following dump:
boardtype=0x0646
pci/1/1/boardtype=0x0545
pci/2/1/boardtype=0x62b
We need to detect them properly to allow drivers apply some board
specific hacks.

[ralf@linux-mips.org: folded in Rafal's fix.]

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/10028/
Patchwork: https://patchwork.linux-mips.org/patch/10048/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:25 +02:00
Rafał Miłecki 6e122ac005 MIPS: BCM47xx: Extract info about et2 interface
New devices may have more than 1 Ethernet core (device). We should
extract info about them to make it available to Ethernet drivers.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Hante Meuleman <meuleman@broadcom.com>
Cc: Ian Kent <raven@themaw.net>
Patchwork: https://patchwork.linux-mips.org/patch/10027/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:24 +02:00
Rafał Miłecki 1387fe7d29 MIPS: BCM47xx: Extract all boardflags to new u32 fields
For years we planned to get rid of old u16 fields, let's start doing it
with MIPS code. This process will take some time, it requires doing the
same in ssb/bcma and then switching all drivers to new fields. This will
be handled in separated patches submitted to appropriate trees.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/10026/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:23 +02:00
Rafał Miłecki 5bfad4eee9 MIPS: BCM47XX: Simplify function looking for NVRAM entry
First of all it shouldn't modify copied NVRAM just to make sure it can
loop over all entries. It's enough to just compare current position
pointer with the end of buffer address.
Secondly buffer is guaranteed to be \0 ended, so we don't need strnchr.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Hante Meuleman <meuleman@broadcom.com>
Cc: Ian Kent <raven@themaw.net>
Patchwork: https://patchwork.linux-mips.org/patch/10032/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:21 +02:00
Rafał Miłecki d28c9a55c2 MIPS: BCM47XX: Make sure NVRAM buffer ends with \0
This will simplify reading its contents.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Hante Meuleman <meuleman@broadcom.com>
Cc: Ian Kent <raven@themaw.net>
Patchwork: https://patchwork.linux-mips.org/patch/10031/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:20 +02:00
Ralf Baechle 2fb7ac5ba6 MIPS: Malta: Make maltasmvp_defconfig useful again.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:19 +02:00
Ralf Baechle fb59e394c3 MIPS: ftrace: Enable support for syscall tracepoints.
All the necessary support code is already there so all that's left is
to enable the feature in kconfig.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:18 +02:00
Thomas Gleixner cb17b2a674 x86/hpet: Use proper hpet device number for MSI allocation
hpet_assign_irq() is called with hpet_device->num as "hardware
interrupt number", but hpet_device->num is initialized after the
interrupt has been assigned, so it's always 0. As a consequence only
the first MSI allocation succeeds, the following ones fail because the
"hardware interrupt number" already exists.

Move the initialization of dev->num and other fields before the call
to hpet_assign_irq(), which is the ordering before the offending
commit which introduced that regression.

Fixes: "3cb96f0c9733 x86/hpet: Enhance HPET IRQ to support hierarchical irqdomains"
Reported-by: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/alpine.DEB.2.11.1506211635010.4107@nanos
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Borislav Petkov <bp@alien8.de>
2015-06-21 16:38:40 +02:00
Michael Turquette 85e88fab13 Merge branch 'clk-exynos-cpu-clk' into clk-next
Folded into this merge commit is a build error fix: s/clk/core in
clk_change_rate due to the new struct clk_core
2015-06-20 13:26:40 -07:00
Thomas Abraham 131323cd16 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210
The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos4210 to using generic cpufreq driver.

Changes by Bartlomiej:
- removed non-Exynos4210 support for now

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-20 12:17:43 -07:00
Jiang Liu bafac298fb x86/hpet: Check for irq==0 when allocating hpet MSI interrupts
irq == 0 is not a valid irq for a irqdomain MSI allocation, but hpet
code checks only for negative return values.

Reported-by: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Link: http://lkml.kernel.org/r/558447AF.30703@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-20 12:00:58 +02:00
Vladimir Murzin 86dca36e6b arm64: use private ratelimit state along with show_unhandled_signals
printk_ratelimit() shares the ratelimiting state with other callers what
may lead to scenarios where at the time we want to print out debug
information we already limited, so nothing appears in the dmesg - this
makes exception-trace quite poor helper in debugging.

Additionally, we have imbalance with some messages limited with global
ratelimit state and other messages limited with their private state
defined via pr_*_ratelimited().

To address this inconsistency show_unhandled_signals_ratelimited()
macro is introduced and caller sites are converted to use it.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-19 16:26:15 +01:00
Vladimir Murzin 9e793ab84e arm64: show unhandled SP/PC alignment faults
Report unhandled SP/PC alignment faults if the show_unhandled_signals
variable is set (via /proc/sys/debug/exception-trace).

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-19 16:20:10 +01:00
Wei Huang e5af058aac KVM: x86/vPMU: reorder PMU functions
Keep called functions closer to their callers, and init/destroy
functions next to each other.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:30 +02:00
Wei Huang e84cfe4ce0 KVM: x86/vPMU: whitespace and stylistic adjustments in PMU code
Signed-off-by: Wei Huang <wei@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:30 +02:00
Wei Huang 212dba1267 KVM: x86/vPMU: use the new macros to go between PMC, PMU and VCPU
Signed-off-by: Wei Huang <wei@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:30 +02:00
Wei Huang 474a5bb944 KVM: x86/vPMU: introduce pmu.h header
This will be used for private function used by AMD- and Intel-specific
PMU implementations.

Signed-off-by: Wei Huang <wei@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:29 +02:00
Wei Huang c6702c9dcf KVM: x86/vPMU: rename a few PMU functions
Before introducing a pmu.h header for them, make the naming more
consistent.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:29 +02:00
Xiao Guangrong 6a39bbc5da KVM: MTRR: do not map huge page for non-consistent range
Based on Intel's SDM, mapping huge page which do not have consistent
memory cache for each 4k page will cause undefined behavior

In order to avoiding this kind of undefined behavior, we force to use
4k pages under this case

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:29 +02:00
Xiao Guangrong fa61213746 KVM: MTRR: simplify kvm_mtrr_get_guest_memory_type
mtrr_for_each_mem_type() is ready now, use it to simplify
kvm_mtrr_get_guest_memory_type()

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:29 +02:00
Xiao Guangrong f571c0973e KVM: MTRR: introduce mtrr_for_each_mem_type
It walks all MTRRs and gets all the memory cache type setting for the
specified range also it checks if the range is fully covered by MTRRs

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
[Adjust for range_size->range_shift change. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:29 +02:00
Xiao Guangrong f7bfb57b3e KVM: MTRR: introduce fixed_mtrr_addr_* functions
Two functions are introduced:
- fixed_mtrr_addr_to_seg() translates the address to the fixed
  MTRR segment

- fixed_mtrr_addr_seg_to_range_index() translates the address to
  the index of kvm_mtrr.fixed_ranges[]

They will be used in the later patch

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
[Adjust for range_size->range_shift change. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:28 +02:00
Xiao Guangrong 19efffa244 KVM: MTRR: sort variable MTRRs
Sort all valid variable MTRRs based on its base address, it will help us to
check a range to see if it's fully contained in variable MTRRs

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
[Fix list insertion sort, simplify var_mtrr_range_is_valid to just
 test the V bit. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:28 +02:00
Xiao Guangrong a13842dc66 KVM: MTRR: introduce var_mtrr_range
It gets the range for the specified variable MTRR

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
[Simplify boolean operations. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:28 +02:00
Xiao Guangrong de9aef5e1a KVM: MTRR: introduce fixed_mtrr_segment table
This table summarizes the information of fixed MTRRs and introduce some APIs
to abstract its operation which helps us to clean up the code and will be
used in later patches

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
[Change range_size to range_shift, in order to avoid udivdi3 errors.
 - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:28 +02:00
Xiao Guangrong 3f3f78b614 KVM: MTRR: improve kvm_mtrr_get_guest_memory_type
- kvm_mtrr_get_guest_memory_type() only checks one page in MTRRs so
   that it's unnecessary to check to see if the range is partially
   covered in MTRR

 - optimize the check of overlap memory type and add some comments
   to explain the precedence

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:28 +02:00
Xiao Guangrong 86fd52701c KVM: MTRR: do not split 64 bits MSR content
Variable MTRR MSRs are 64 bits which are directly accessed with full length,
no reason to split them to two 32 bits

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:27 +02:00
Xiao Guangrong 10fac2dc2b KVM: MTRR: clean up mtrr default type
Drop kvm_mtrr->enable, omit the decode/code workload and get rid of
all the hard code

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:27 +02:00
Xiao Guangrong 910a6aae4e KVM: MTRR: exactly define the size of variable MTRRs
Only KVM_NR_VAR_MTRR variable MTRRs are available in KVM guest

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:27 +02:00
Xiao Guangrong 70109e7d9d KVM: MTRR: remove mtrr_state.have_fixed
vMTRR does not depend on any host MTRR feature and fixed MTRRs have always
been implemented, so drop this field

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:27 +02:00
Xiao Guangrong eb839917a7 KVM: MTRR: handle MSR_MTRRcap in kvm_mtrr_get_msr
MSR_MTRRcap is a MTRR msr so move the handler to the common place, also
add some comments to make the hard code more readable

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:27 +02:00
Xiao Guangrong ff53604b40 KVM: x86: move MTRR related code to a separate file
MTRR code locates in x86.c and mmu.c so that move them to a separate file to
make the organization more clearer and it will be the place where we fully
implement vMTRR

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:26 +02:00
Xiao Guangrong b18d5431ac KVM: x86: fix CR0.CD virtualization
Currently, CR0.CD is not checked when we virtualize memory cache type for
noncoherent_dma guests, this patch fixes it by :

- setting UC for all memory if CR0.CD = 1
- zapping all the last sptes in MMU if CR0.CD is changed

Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:26 +02:00
Bandan Das f104765b4f KVM: nSVM: Check for NRIPS support before updating control field
If hardware doesn't support DecodeAssist - a feature that provides
more information about the intercept in the VMCB, KVM decodes the
instruction and then updates the next_rip vmcb control field.
However, NRIP support itself depends on cpuid Fn8000_000A_EDX[NRIPS].
Since skip_emulated_instruction() doesn't verify nrip support
before accepting control.next_rip as valid, avoid writing this
field if support isn't present.

Signed-off-by: Bandan Das <bsd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-19 17:16:26 +02:00
Paolo Bonzini 05fe125fa3 KVM/ARM changes for v4.2:
- Proper guest time accounting
 - FP access fix for 32bit
 - The usual pile of GIC fixes
 - PSCI fixes
 - Random cleanups
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Merge tag 'kvm-arm-for-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/ARM changes for v4.2:

- Proper guest time accounting
- FP access fix for 32bit
- The usual pile of GIC fixes
- PSCI fixes
- Random cleanups
2015-06-19 17:15:24 +02:00
Herbert Xu c0b59fafe3 Merge branch 'mvebu/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Merge the mvebu/drivers branch of the arm-soc tree which contains
just a single patch bfa1ce5f38 ("bus:
mvebu-mbus: add mv_mbus_dram_info_nooverlap()") that happens to be
a prerequisite of the new marvell/cesa crypto driver.
2015-06-19 22:07:07 +08:00
Borislav Petkov 04c17341b4 x86/boot: Fix overflow warning with 32-bit binutils
When building the kernel with 32-bit binutils built with support
only for the i386 target, we get the following warning:

  arch/x86/kernel/head_32.S:66: Warning: shift count out of range (32 is not between 0 and 31)

The problem is that in that case, binutils' internal type
representation is 32-bit wide and the shift range overflows.

In order to fix this, manipulate the shift expression which
creates the 4GiB constant to not overflow the shift count.

Suggested-by: Michael Matz <matz@suse.de>
Reported-and-tested-by: Enrico Mioso <mrkiko.rs@gmail.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-06-19 16:03:26 +02:00
Will Deacon 6f1a6ae87c arm64: vdso: work-around broken ELF toolchains in Makefile
When building the kernel with a bare-metal (ELF) toolchain, the -shared
option may not be passed down to collect2, resulting in silent corruption
of the vDSO image (in particular, the DYNAMIC section is omitted).

The effect of this corruption is that the dynamic linker fails to find
the vDSO symbols and libc is instead used for the syscalls that we
intended to optimise (e.g. gettimeofday). Functionally, there is no
issue as the sigreturn trampoline is still intact and located by the
kernel.

This patch fixes the problem by explicitly passing -shared to the linker
when building the vDSO.

Cc: <stable@vger.kernel.org>
Reported-by: Szabolcs Nagy <Szabolcs.Nagy@arm.com>
Reported-by: James Greenlaigh <james.greenhalgh@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-19 14:54:10 +01:00
Sudeep Holla af391b15f7 arm64: kernel: rename __cpu_suspend to keep it aligned with arm
This patch renames __cpu_suspend to cpu_suspend so that it's aligned
with ARM32. It also removes the redundant wrapper created.

This is in preparation to implement generic PSCI system suspend using
the cpu_{suspend,resume} which now has the same interface on both ARM
and ARM64.

Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Ashwin Chaugule <ashwin.chaugule@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-19 14:46:39 +01:00
Vineet Gupta 5793e273a1 ARC: intc: split into ARCompact ISA specific, common bits
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:40 +05:30
Vineet Gupta 6ffb9c8c5f ARC: Make way for pt_regs != user_regs_struct
These have been register compatible so far. However ARCv2 mandates
different pt_regs layout (due to h/w auto save). To keep pt_regs same
for both, we start by removing the assumption - used mainly for block
copies between the 2 structs in signal handling and ptrace

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:40 +05:30
Vineet Gupta 5a343b9fe2 ARC: entry.S: [arcompact] simplify SWITCH_TO_KERNEL_STK
Previously this macro was overloaded with stack switching, saving SP at right
slot in pt_regs, saving/setup of r25 and setting SP baseline to where
pt_regs->sp is saved (vs. bottom of pt_regs)

Now it only does SP switch, and leaves SP pointing to bottom of pt_regs.

r25 saving is no longer done here to allow for future reordering of
regfile in pt_regs w/o touching this macro

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:40 +05:30
Vineet Gupta c80417b612 ARC: entry.S: use single EXCEPTION_PROLOGUE
Returning from pure kernel mode and exception mode use the same code
anyways. Remove one the duplicate blocks

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:39 +05:30
Vineet Gupta 62fb64034d ARC: entry.S: micro-optimize Trap handler
Elide the need to re-read ECR in Trap handler by ensuring that
EXCEPTION_PROLOGUE does that at the very end just before returning
to Trap handler

ARCv2 EXCEPTION_PROLOGUE already did that, so same for ARcompact and the
common trap handler adjusted to use cached ECR

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:39 +05:30
Vineet Gupta c7e6d79204 ARC: entry.S: move some code around for cache locality in return path
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:38 +05:30
Vineet Gupta 6d1a20b1d2 ARC: entry.S: split into ARCompact ISA specific, common bits
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:38 +05:30
Vineet Gupta c10d6969b0 ARC: entry.S: Ensure that restore_regs is local to compilation unit
This fixes the possible link/relo errors, since restore_regs will be
provided by ISA code, but called from ARC common code.
The .L prefix reassures binutils that it will be in same compilation
unit.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:37 +05:30
Vineet Gupta 4bf4564b27 ARC: entry.S: comments cleanup
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:37 +05:30
Vineet Gupta a8717d2808 ARC: entry.S: Trap handler to use r10 for syscall vs. brkpt decision
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:36 +05:30
Vineet Gupta 9b8c7d1e71 ARC: entry.S: FAKE_RET_FROM_EXCPN can always use r9
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:36 +05:30
Vineet Gupta a615b47dbf ARC: entry.S: confine EXCEPTION_* macros to one file
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:35 +05:30
Vineet Gupta f033737e77 ARC: entry.S: canonical'ize EXCEPTION_{PROLOGUE,EPILOGUE}
-EXCEPTION_EPILOGUE introduced
-EXCEPTION_PROLOGUE now also includes reg file saving

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:35 +05:30
Vineet Gupta 09f3b37e4e ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}
-common'ize macros for level 1 and level 2 interrupts

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:34 +05:30
Vineet Gupta fbfa26ae3b ARC: entry.S: common'ize scrtach reg freeup in intr + exceptions
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:34 +05:30
Vineet Gupta 11e14896ea ARC: untangle cache flush loop
- Remove the ifdef'ery and write distinct versions for each mmu ver even
  if there is some code duplication

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:33 +05:30
Vineet Gupta 6c31068137 ARC: cacheflush: No need to retain DC_CTRL from __before_dc_op()
That is because __after_dc_op() already reads it for status check, so it
is better anyways to use that "newer" value.

Also reduces the clutter in callers for passing from/to these routines.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:33 +05:30
Vineet Gupta 8ea2ddff41 ARC: cacheflush: move some code around, delete old comments
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:33 +05:30
Vineet Gupta 8362c389a4 ARC: mm/cache_arc700.c -> mm/cache.c
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:32 +05:30
Vineet Gupta db7e985526 ARC: [axs101] Add missing __init annotations
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:32 +05:30
Alexey Brodkin 7cacc5bf60 ARC: [axs101] STAR 9000799830: Fix SD cards support
As DW Mobile Storage databook says it's required to use "Hold Register"
if card is enumerated in SDR12 or SDR25 modes.
It means we need to act in the same way as in Altera's Socfpga
implementation - set "use hold reg" bit in commad.

Note that for upstream proper solution would be to remove
dw_mci_pltfm_prepare_command() at all and set the bit right in
dw_mci_prepare_command() for all platforms.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:31 +05:30
Vineet Gupta 749aa0e11a ARC: [axs101] Tweak DDR port aperture mappings for performance
Route all MB originated traffic to DDR Port 1 and keep Port 0 for CPU
traffic only

Basic system parameters
--------------------------------------------------------------------------------------
        Host                 OS Description 				Mhz  tlb   cache  mem   scal
                                                			    pages  line   par   load
                                                      				   bytes
----------------- ------------- --------------------------------------- ---- ----- ----- ------ ----
axs101-sd-2-new-f Linux 3.13.0+ axs101-sd-2-new-fw-old-img-rerun    	739  	8    32 1.1100    1
axs101-sd-3-arc-3 Linux 3.13.9+ axs101-sd-3-arc-3.13-tip-regression 	735  	8    32 1.1000    1
axs101-sd-9-diffe Linux 3.13.11 axs101-sd-9-different-tweak         	740  	8    32 1.0000    1

Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host                 OS  Mhz null null      open slct sig  sig  fork exec sh
                             call  I/O stat clos TCP  inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
axs101-sd Linux 3.13.0+  739 0.50 0.88 5.38 14.6 34.1 0.92 5.18 2135 6555 12.K
axs101-sd Linux 3.13.9+  735 0.50 0.90 5.89 19.2 81.4 0.94 4.08 2560 8559 15.K
axs101-sd Linux 3.13.11  740 0.50 0.88 4.45 17.8 34.4 0.94 3.25 2052 6493 12.K
                                                 ^^^^                     ^^^^

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:31 +05:30
Vineet Gupta 8d0d56ba24 ARC: [axs101] support early 8250 uart
Earlycon calculates UART clock as "BASE_BAUD * 16". In case of ARC
"BASE_BAUD" is calculated dynamically in runtime, basically it is an
alias to arc_early_base_baud(), which in turn just does
"arc_base_baud/16".

8250 UART on AXS/SDP board uses 33.3MHz clock source which is set in
"arc_base_baud" with this change.

Additional compatibility string "snps,arc-sdp" is introduced as well
because there're different flavours of AXS boards but they all share the
same motherboard and so it's possible to re-use the same code for
motherbord even if CPU daughterboard changes.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:30 +05:30
Alexey Brodkin 556cc1c5f5 ARC: [axs101] Add support for AXS101 SDP (software development platform)
The AXS10x platforms consist of a mainboard with peripherals,
on which several daughter cards can be placed. The daughter cards
typically contain a CPU and memory.

Signed-off-by: Mischa Jonker <mjonker@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:30 +05:30
Vineet Gupta 4db27dca60 ARC: mm: document system mem map clearly
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:29 +05:30
Vineet Gupta def32fad84 ARC: stack unwinder to bail if PC is not kernel mode
Currently, it doesn't invoke the callback but continues to unwind

Also while at it - simplify the code a bit

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:29 +05:30
Tobias Klauser 082ae1e157 ARC: perf: Remove unnecessary local variable
Directly return the result of perf_pmu_register() in
arc_pmu_device_probe() instead of assigning and returning variable ret.

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:28 +05:30
Max Filippov 7002f77541 arc: fix use of uninitialized arc_pmu
static arc_pmu in the arch/arc/kernel/perf_event.c is not initialized as
it's shadowed by a local variable of the same name in the
arc_pmu_device_probe.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Fixes: 03c94fcf95 "ARC: perf: make @arc_pmu static global"
CC: <stable@vger.kernel.org>	# 4.1
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:28 +05:30
Vineet Gupta b27f739171 ARC: fix section mismatch with allyesconfig
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:27 +05:30
Vineet Gupta 036b2c5664 ARC: explicit'ify uboot support
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:27 +05:30
Vineet Gupta fd1557923b ARC: [plat_arcfpga]->[plat_sim]
* Remove remanants of legacy ARC FPGA platforms (AA4, ML509...)
* Only nsim simulation platform is left, rename platform accordingly
* AA4 DT stuff is compatible with nsim for ARC700 so rename it too

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:26 +05:30
Vineet Gupta 6623146cb7 ARC: [arcfpga] RIP legacy ISS based SMP extension
With ISS long unsupported, no point in having extension based on it

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:26 +05:30
Vineet Gupta 40b552d95a ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:25 +05:30
Vineet Gupta 5b9bd17840 ARC: clocksource cleanups
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:25 +05:30
Vineet Gupta 565a9b497c ARC: RIP broken 64bit RTSC
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:24 +05:30
Vineet Gupta 742f8af6cb ARC: [kbuild] Retire CONFIG_ARC_CPU_REL_4_10
Back when ARC700 4.10 was released, the related kernel features were
tied to this config item so they could be disabled in one shot (i.e.
LLOCK/SCOND, SWAPE, RTSC..)

That having happened a while back, all new ARC customers weill get 4.11+
so those features can be assumed to be present and need not be tied to a
top-level (we still retain the ability to individually disable them).

Further, since ARCv2 also shares some of those feautes, removing it
simplifies things a bit in Kconfig

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:24 +05:30
Vineet Gupta 454bfda9ac ARC: remove the unused platform helpers from dma mapping API
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:23 +05:30
Palik, Imre 2c33645d36 perf/x86: Honor the architectural performance monitoring version
Architectural performance monitoring, version 1, doesn't support fixed counters.

Currently, even if a hypervisor advertises support for architectural
performance monitoring version 1, perf may still try to use the fixed
counters, as the constraints are set up based on the CPU model.

This patch ensures that perf honors the architectural performance monitoring
version returned by CPUID, and it only uses the fixed counters for version 2
and above.

(Some of the ideas in this patch came from Peter Zijlstra.)

Signed-off-by: Imre Palik <imrep@amazon.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Anthony Liguori <aliguori@amazon.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1433767609-1039-1-git-send-email-imrep.amz@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-06-19 09:38:48 +02:00
Alexander Shishkin 1b7b938f18 perf/x86/intel: Fix PMI handling for Intel PT
Intel PT is a separate PMU and it is not using any of the x86_pmu
code paths, which means in particular that the active_events counter
remains intact when new PT events are created.

However, PT uses the generic x86_pmu PMI handler for its PMI handling needs.

The problem here is that the latter checks active_events and in case of it
being zero, exits without calling the actual x86_pmu.handle_nmi(), which
results in unknown NMI errors and massive data loss for PT.

The effect is not visible if there are other perf events in the system
at the same time that keep active_events counter non-zero, for instance
if the NMI watchdog is running, so one needs to disable it to reproduce
the problem.

At the same time, the active_events counter besides doing what the name
suggests also implicitly serves as a PMC hardware and DS area reference
counter.

This patch adds a separate reference counter for the PMC hardware, leaving
active_events for actually counting the events and makes sure it also
counts PT and BTS events.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: acme@infradead.org
Cc: adrian.hunter@intel.com
Link: http://lkml.kernel.org/r/87k2v92t0s.fsf@ashishki-desk.ger.corp.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-06-19 09:38:47 +02:00
Alexander Shishkin 6b099d9b04 perf/x86/intel/bts: Fix DS area sharing with x86_pmu events
Currently, the intel_bts driver relies on the DS area allocated by the x86_pmu
code in its event_init() path, which is a bug: creating a BTS event while
no x86_pmu events are present results in a NULL pointer dereference.

The same DS area is also used by PEBS sampling, which makes it quite a bit
trickier to have a separate one for intel_bts' purposes.

This patch makes intel_bts driver use the same DS allocation and reference
counting code as x86_pmu to make sure it is always present when either
intel_bts or x86_pmu need it.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: acme@infradead.org
Cc: adrian.hunter@intel.com
Link: http://lkml.kernel.org/r/1434024837-9916-2-git-send-email-alexander.shishkin@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-06-19 09:38:47 +02:00
Andi Kleen 4b36f1a413 perf/x86: Add more Broadwell model numbers
This patch adds additional model numbers for Broadwell to perf.
Support for Broadwell with Iris Pro (Intel Core i7-57xxC)
and support for Broadwell Server Xeon.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1434055942-28253-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-06-19 09:38:46 +02:00
Michael Ellerman 6096f88451 Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next
Freescale updates from Scott:

"Highlights include more 8xx optimizations, an e6500 hugetlb optimization,
QMan device tree nodes, t1024/t1023 support, and various fixes and
cleanup."
2015-06-19 17:23:48 +10:00
Alexey Kardashevskiy 5c89a87d13 powerpc/powernv: Fix wrong IOMMU table in pnv_ioda_setup_bus_dma()
When pnv_pci_ioda_fixup() is called during PHB fixup time, each PE in
the sorted list of PEs (phb::pe_dma_list) is iterated to setup the PE's
DMA32 space by pnv_ioda_setup_bus_dma() if the PE's DMA32 weight is bigger
than zero. The function also assigns all the subordinate PCI devices of
the PE's primary bus with the PE's DMA32 IOMMU table. It causes the PCI
devicess in the child PEs, which don't have DMA weight, receives wrong
IOMMU table and then IOMMU group.

The patch fixes above issue by more check on the PE's coverage and don't
assign IOMMU table to those PCI devices, which belong to the child PEs.
The problem was found on Firestone platform initially.

Suggested-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-19 17:10:29 +10:00
Aneesh Kumar K.V e148315852 powerpc/mm: Change the swap encoding in pte.
Current swap encoding in pte can't support large pfns
above 4TB. Change the swap encoding such that we put
the swap type in the PTE bits. Also add build checks
to make sure we don't overlap with HPTEFLAGS.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-19 17:10:29 +10:00
Aneesh Kumar K.V 02505cebc1 powerpc/mm: PTE_RPN_MAX is not used, remove the same
Remove the unused #define

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-19 17:10:28 +10:00
Sam bobroff b4b56f9eca powerpc/tm: Abort syscalls in active transactions
This patch changes the syscall handler to doom (tabort) active
transactions when a syscall is made and return very early without
performing the syscall and keeping side effects to a minimum (no CPU
accounting or system call tracing is performed). Also included is a
new HWCAP2 bit, PPC_FEATURE2_HTM_NOSC, to indicate this
behaviour to userspace.

Currently, the system call instruction automatically suspends an
active transaction which causes side effects to persist when an active
transaction fails.

This does change the kernel's behaviour, but in a way that was
documented as unsupported.  It doesn't reduce functionality as
syscalls will still be performed after tsuspend; it just requires that
the transaction be explicitly suspended.  It also provides a
consistent interface and makes the behaviour of user code
substantially the same across powerpc and platforms that do not
support suspended transactions (e.g. x86 and s390).

Performance measurements using
http://ozlabs.org/~anton/junkcode/null_syscall.c indicate the cost of
a normal (non-aborted) system call increases by about 0.25%.

Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-19 17:10:28 +10:00
Rafael J. Wysocki b306976ef7 Merge branches 'pm-clk', 'pm-domains' and 'powercap'
* pm-clk:
  PM / clk: Print acquired clock name in addition to con_id
  PM / clk: Fix clock error check in __pm_clk_add()
  drivers: sh: remove boilerplate code and use USE_PM_CLK_RUNTIME_OPS
  arm: davinci: remove boilerplate code and use USE_PM_CLK_RUNTIME_OPS
  arm: omap1: remove boilerplate code and use USE_PM_CLK_RUNTIME_OPS
  arm: keystone: remove boilerplate code and use USE_PM_CLK_RUNTIME_OPS
  PM / clock_ops: Provide default runtime ops to users

* pm-domains:
  PM / Domains: Skip timings during syscore suspend/resume

* powercap:
  powercap / RAPL: Support Knights Landing
  powercap / RAPL: Floor frequency setting in Atom SoC
2015-06-19 01:18:30 +02:00
Rafael J. Wysocki ab232ba570 Merge branches 'pm-sleep' and 'pm-runtime'
* pm-sleep:
  PM / sleep: trace_device_pm_callback coverage in dpm_prepare/complete
  PM / wakeup: add a dummy wakeup_source to record statistics
  PM / sleep: Make suspend-to-idle-specific code depend on CONFIG_SUSPEND
  PM / sleep: Return -EBUSY from suspend_enter() on wakeup detection
  PM / tick: Add tracepoints for suspend-to-idle diagnostics
  PM / sleep: Fix symbol name in a comment in kernel/power/main.c
  leds / PM: fix hibernation on arm when gpio-led used with CPU led trigger
  ARM: omap-device: use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS
  bus: omap_l3_noc: add missed callbacks for suspend-to-disk
  PM / sleep: Add macro to define common noirq system PM callbacks
  PM / sleep: Refine diagnostic messages in enter_state()
  PM / wakeup: validate wakeup source before activating it.

* pm-runtime:
  PM / Runtime: Update last_busy in rpm_resume
  PM / runtime: add note about re-calling in during device probe()
2015-06-19 01:18:02 +02:00
Sebastian Ott 7fc611ff3f s390/pci: improve handling of hotplug event 0x301
Hypervisors may deliver event 0x301 not only for standby
but also for reserved devices.
Just handle event 0x301 regardless of the device's state.

Reviewed-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-18 15:45:54 +02:00
Sebastian Ott 0c36b8ac70 s390/setup: fix DMA_API_DEBUG warnings
Addresses from the usable space in [_ehead, _stext] lead to false
positives in DMA_API_DEBUG code (which will complain when an address
is in [_text, _etext]).

Avoid these warnings by not using that memory in case of
CONFIG_DMA_API_DEBUG=y.

Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-18 15:45:46 +02:00
Russell King 7f77c5c39d ARM: gemini: Fix race in installing GPIO chained IRQ handler
The gemini code was installing its chained interrupt handler (which
enables the interrupt) before it was setting its data, which is bad if
the IRQ was previously pending.  Avoid this problem by converting it to
irq_set_chained_handler_and_data().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/E1Z4z07-0002SO-Gv@rmk-PC.arm.linux.org.uk
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-18 14:03:08 +02:00
Russell King 056c0acf87 ARM: sa1100: convert SA11x0 related code to use new chained handler helper
Convert SA11x0 (Neponset, SA1111, and UCB1x00 code) to use the new
irq_set_chained_handler_and_data() helper.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/E1Z4yzx-0002S6-7p@rmk-PC.arm.linux.org.uk
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-18 14:03:08 +02:00
Aravind Gopalakrishnan cc2749e409 x86/cpu/amd: Give access to the number of nodes in a physical package
Stash the number of nodes in a physical processor package
locally and add an accessor to be called by interested parties.
The first user is the MCE injection module which uses it to find
the node base core in a package for injecting a certain type of
errors.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
[ Rewrote the commit message, merged it with the accessor patch and unified naming. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jacob Shin <jacob.w.shin@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mchehab@osg.samsung.com
Link: http://lkml.kernel.org/r/1433868317-18417-2-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-06-18 11:16:06 +02:00
Feng Tang b58d930750 x86/platform/intel/baytrail: Add comments about why we disabled HPET on Baytrail
This question has been asked many times, and finally I found the
official document which explains the problem of HPET on Baytrail,
that it will halt in deep idle states.

Signed-off-by: Feng Tang <feng.tang@intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: john.stultz@linaro.org
Cc: len.brown@intel.com
Cc: matthew.lee@intel.com
Link: http://lkml.kernel.org/r/1434361201-31743-1-git-send-email-feng.tang@intel.com
[ Prettified things a bit. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-06-18 10:57:38 +02:00
Linus Torvalds 32e0e382ee Merge git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm bugfix from Marcelo Tosatti:
 "Rrestore APIC migration functionality"

* git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: x86: fix lapic.timer_mode on restore
2015-06-17 20:54:47 -10:00
Mark Brown 9a8d141d5a Merge remote-tracking branches 'spi/topic/ath79', 'spi/topic/atmel' and 'spi/topic/davinci' into spi-next 2015-06-18 00:19:50 +01:00
Bjorn Helgaas 9f3d162071 Merge branch 'pci/resource' into next
* pci/resource:
  x86/PCI: Use host bridge _CRS info on systems with >32 bit addressing
  x86/PCI: Use host bridge _CRS info on Foxconn K8M890-8237A
2015-06-17 17:24:32 -05:00
Bjorn Helgaas 3d9fecf6bf x86/PCI: Use host bridge _CRS info on systems with >32 bit addressing
We enable _CRS on all systems from 2008 and later.  On older systems, we
ignore _CRS and assume the whole physical address space (excluding RAM and
other devices) is available for PCI devices, but on systems that support
physical address spaces larger than 4GB, it's doubtful that the area above
4GB is really available for PCI.

After d56dbf5bab ("PCI: Allocate 64-bit BARs above 4G when possible"), we
try to use that space above 4GB *first*, so we're more likely to put a
device there.

On Juan's Toshiba Satellite Pro U200, BIOS left the graphics, sound, 1394,
and card reader devices unassigned (but only after Windows had been
booted).  Only the sound device had a 64-bit BAR, so it was the only device
placed above 4GB, and hence the only device that didn't work.

Keep _CRS enabled even on pre-2008 systems if they support physical address
space larger than 4GB.

Fixes: d56dbf5bab ("PCI: Allocate 64-bit BARs above 4G when possible")
Reported-and-tested-by: Juan Dayer <jdayer@outlook.com>
Reported-and-tested-by: Alan Horsfield <alan@hazelgarth.co.uk>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=99221
Link: https://bugzilla.opensuse.org/show_bug.cgi?id=907092
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.14+
2015-06-17 17:24:06 -05:00
Alexey Kardashevskiy b5926430df powerpc/iommu/ioda2: Enable compile with IOV=on and IOMMU_API=off
The pnv_pci_ioda2_unset_window() function is used to do the final
cleanup of a DMA window being released:
- via VFIO ioctl by the guest request;
- via unplugging a virtual PCI function.
However the function was under #ifdef CONFIG_IOMMU_API and was missing.

This moves the helper outside of IOMMU_API block and enables it
for either or both IOMMU_API and PCI_IOV.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-18 07:16:02 +10:00
Jeremy Kerr cdf2bc1c28 powerpc/include: Add opal-prd to installed uapi headers
We'll want to build the opal-prd daemon with the prd headers, so include
this in the uapi headers list.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-18 07:16:02 +10:00
Jeremy Kerr 7185795a62 powerpc/powernv: fix construction of opal PRD messages
We currently have a bug in the PRD code, where the contents of an
incoming message (beyond the header) will be overwritten by the list
item manipulations when adding to to the prd_msg_queue.

This change reorders struct opal_prd_msg_queue_item, so that the
message body doesn't overlap the list_head.

We also clarify the memcpy of the message, as we're copying unnecessary
bytes at the end of the message data.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Acked-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-18 07:16:01 +10:00
Alistair Popple 02b6505c8f powerpc/powernv: Increase opal-irqchip initcall priority
The eeh subsystem for powernv requires the opal event irqchip to be
initialised prior to initialisation or the following errors are
produced (and eeh doesn't work as expected):

irq: XICS didn't like hwirq-0x9 to VIRQ17 mapping (rc=-22)
pnv_eeh_post_init: Can't request OPAL event interrupt (0)

On powernv eeh is initialised from a subsys_initcall due to a check
for machine_is(powernv) in eeh_init(). This patch increases the
initcall priority of opal_event_init() to an arch_initcall to ensure
the opal event interface is initialised prior to any users of it.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
Reported-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-18 07:16:01 +10:00
Michael Turquette b2d8bc21ce Merge remote-tracking branch 'clk/clk-next' into clk-next 2015-06-17 13:20:43 -07:00
Julien Grall 90d73c4f43 arm/xen: Drop duplicate define mfn_to_virt
Signed-off-by: Julien Grall <julien.grall@citrix.com>
Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
2015-06-17 16:35:17 +01:00
Thomas Petazzoni 2f5bc307be ARM: mvebu: fix suspend to RAM on big-endian configurations
The current Armada XP suspend to RAM implementation, as added in
commit 27432825ae ("ARM: mvebu: Armada XP GP specific
suspend/resume code") does not handle big-endian configurations
properly: the small bit of assembly code putting the DRAM in
self-refresh and toggling the GPIOs to turn off power forgets to
convert the values to little-endian.

This commit fixes that by making sure the two values we will write to
the DRAM controller register and GPIO register are already in
little-endian before entering the critical assembly code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.19+
Fixes: 27432825ae ("ARM: mvebu: Armada XP GP specific suspend/resume code")
2015-06-17 17:23:36 +02:00
Julien Grall a9fd60e268 xen: Include xen/page.h rather than asm/xen/page.h
Using xen/page.h will be necessary later for using common xen page
helpers.

As xen/page.h already include asm/xen/page.h, always use the later.

Signed-off-by: Julien Grall <julien.grall@citrix.com>
Reviewed-by: David Vrabel <david.vrabel@citrix.com>
Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Wei Liu <wei.liu2@citrix.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: netdev@vger.kernel.org
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
2015-06-17 16:14:18 +01:00
Thomas Petazzoni 8c19a731a1 ARM: mvebu: adjust Armada XP DT spi muxing after pinctrl function rename
Following the merge of "pinctrl: mvebu: armada-xp: rename spi to spi0"
by Linus Walleij, we need to adjust the Armada XP Device Tree
accordingly, by adjusting the pinctrl configuration for SPI pins.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-06-17 15:42:15 +02:00
Vladimir Murzin 4e2ee96a63 arm64: compat: print compat_sp instead of sp
We check against compat_sp, but print out arm64's sp - fix it.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-17 14:30:53 +01:00
Dave P Martin b9bcc91993 arm64: mm: Fix freeing of the wrong memmap entries with !SPARSEMEM_VMEMMAP
The memmap freeing code in free_unused_memmap() computes the end of
each memblock by adding the memblock size onto the base.  However,
if SPARSEMEM is enabled then the value (start) used for the base
may already have been rounded downwards to work out which memmap
entries to free after the previous memblock.

This may cause memmap entries that are in use to get freed.

In general, you're not likely to hit this problem unless there
are at least 2 memblocks and one of them is not aligned to a
sparsemem section boundary.  Note that carve-outs can increase
the number of memblocks by splitting the regions listed in the
device tree.

This problem doesn't occur with SPARSEMEM_VMEMMAP, because the
vmemmap code deals with freeing the unused regions of the memmap
instead of requiring the arch code to do it.

This patch gets the memblock base out of the memblock directly when
computing the block end address to ensure the correct value is used.

Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-17 14:29:34 +01:00
Mark Rutland 46b0567c85 arm64: entry: fix context tracking for el0_sp_pc
Commit 6c81fe7925 ("arm64: enable context tracking") did not
update el0_sp_pc to use ct_user_exit, but this appears to have been
unintentional. In commit 6ab6463aeb ("arm64: adjust el0_sync so
that a function can be called") we made x0 available, and in the return
to userspace we call ct_user_enter in the kernel_exit macro.

Due to this, we currently don't correctly inform RCU of the user->kernel
transition, and may erroneously account for time spent in the kernel as
if we were in an extended quiescent state when CONFIG_CONTEXT_TRACKING
is enabled.

As we do record the kernel->user transition, a userspace application
making accesses from an unaligned stack pointer can demonstrate the
imbalance, provoking the following warning:

------------[ cut here ]------------
WARNING: CPU: 2 PID: 3660 at kernel/context_tracking.c:75 context_tracking_enter+0xd8/0xe4()
Modules linked in:
CPU: 2 PID: 3660 Comm: a.out Not tainted 4.1.0-rc7+ #8
Hardware name: ARM Juno development board (r0) (DT)
Call trace:
[<ffffffc000089914>] dump_backtrace+0x0/0x124
[<ffffffc000089a48>] show_stack+0x10/0x1c
[<ffffffc0005b3cbc>] dump_stack+0x84/0xc8
[<ffffffc0000b3214>] warn_slowpath_common+0x98/0xd0
[<ffffffc0000b330c>] warn_slowpath_null+0x14/0x20
[<ffffffc00013ada4>] context_tracking_enter+0xd4/0xe4
[<ffffffc0005b534c>] preempt_schedule_irq+0xd4/0x114
[<ffffffc00008561c>] el1_preempt+0x4/0x28
[<ffffffc0001b8040>] exit_files+0x38/0x4c
[<ffffffc0000b5b94>] do_exit+0x430/0x978
[<ffffffc0000b614c>] do_group_exit+0x40/0xd4
[<ffffffc0000c0208>] get_signal+0x23c/0x4f4
[<ffffffc0000890b4>] do_signal+0x1ac/0x518
[<ffffffc000089650>] do_notify_resume+0x5c/0x68
---[ end trace 963c192600337066 ]---

This patch adds the missing ct_user_exit to the el0_sp_pc entry path,
correcting the context tracking for this case.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Fixes: 6c81fe7925 ("arm64: enable context tracking")
Cc: <stable@vger.kernel.org> # v3.17+
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-17 11:53:19 +01:00
Wolfram Sang b6eba5598d ARM: shmobile: r8a7740: remove I2C errata handling
This is now done in the I2C driver.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-17 12:40:47 +02:00
Marc Zyngier 4642019dc4 arm/arm64: KVM: vgic: Do not save GICH_HCR / ICH_HCR_EL2
The GIC Hypervisor Configuration Register is used to enable
the delivery of virtual interupts to a guest, as well as to
define in which conditions maintenance interrupts are delivered
to the host.

This register doesn't contain any information that we need to
read back (the EOIcount is utterly useless for us).

So let's save ourselves some cycles, and not save it before
writing zero to it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-06-17 09:59:55 +01:00
Lorenzo Pieralisi e2d997366d ARM: kvm: psci: fix handling of unimplemented functions
According to the PSCI specification and the SMC/HVC calling
convention, PSCI function_ids that are not implemented must
return NOT_SUPPORTED as return value.

Current KVM implementation takes an unhandled PSCI function_id
as an error and injects an undefined instruction into the guest
if PSCI implementation is called with a function_id that is not
handled by the resident PSCI version (ie it is not implemented),
which is not the behaviour expected by a guest when calling a
PSCI function_id that is not implemented.

This patch fixes this issue by returning NOT_SUPPORTED whenever
the kvm PSCI call is executed for a function_id that is not
implemented by the PSCI kvm layer.

Cc: <stable@vger.kernel.org> # 3.18+
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-06-17 09:46:29 +01:00
Alex Bennée 921ef1e16c KVM: arm64: fix misleading comments in save/restore
The elr_el2 and spsr_el2 registers in fact contain the processor state
before entry into EL2. In the case of guest state it could be in either
el0 or el1.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-06-17 09:46:29 +01:00
Kim Phillips 8889583c03 KVM: arm/arm64: Enable the KVM-VFIO device
The KVM-VFIO device is used by the QEMU VFIO device. It is used to
record the list of in-use VFIO groups so that KVM can manipulate
them.

Signed-off-by: Kim Phillips <kim.phillips@linaro.org>
Signed-off-by: Eric Auger <eric.auger@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-06-17 09:46:29 +01:00
Christoffer Dall 1b3d546daf arm/arm64: KVM: Properly account for guest CPU time
Until now we have been calling kvm_guest_exit after re-enabling
interrupts when we come back from the guest, but this has the
unfortunate effect that CPU time accounting done in the context of timer
interrupts occurring while the guest is running doesn't properly notice
that the time since the last tick was spent in the guest.

Inspired by the comment in the x86 code, move the kvm_guest_exit() call
below the local_irq_enable() call and change __kvm_guest_exit() to
kvm_guest_exit(), because we are now calling this function with
interrupts enabled.  We have to now explicitly disable preemption and
not enable preemption before we've called kvm_guest_exit(), since
otherwise we could be preempted and everything happening before we
eventually get scheduled again would be accounted for as guest time.

At the same time, move the trace_kvm_exit() call outside of the atomic
section, since there is no reason for us to do that with interrupts
disabled.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-06-17 09:46:28 +01:00
Tiejun Chen ea2c6d9745 kvm: remove one useless check extension
We already check KVM_CAP_IRQFD in generic once enable CONFIG_HAVE_KVM_IRQFD,

kvm_vm_ioctl_check_extension_generic()
    |
    + switch (arg) {
    +   ...
    +   #ifdef CONFIG_HAVE_KVM_IRQFD
    +       case KVM_CAP_IRQFD:
    +   #endif
    +   ...
    +   return 1;
    +   ...
    + }
    |
    + kvm_vm_ioctl_check_extension()

So its not necessary to check this in arch again, and also fix one typo,
s/emlation/emulation.

Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2015-06-17 09:46:28 +01:00
Marc Zyngier 85e84ba310 arm: KVM: force execution of HCPTR access on VM exit
On VM entry, we disable access to the VFP registers in order to
perform a lazy save/restore of these registers.

On VM exit, we restore access, test if we did enable them before,
and save/restore the guest/host registers if necessary. In this
sequence, the FPEXC register is always accessed, irrespective
of the trapping configuration.

If the guest didn't touch the VFP registers, then the HCPTR access
has now enabled such access, but we're missing a barrier to ensure
architectural execution of the new HCPTR configuration. If the HCPTR
access has been delayed/reordered, the subsequent access to FPEXC
will cause a trap, which we aren't prepared to handle at all.

The same condition exists when trapping to enable VFP for the guest.

The fix is to introduce a barrier after enabling VFP access. In the
vmexit case, it can be relaxed to only takes place if the guest hasn't
accessed its view of the VFP registers, making the access to FPEXC safe.

The set_hcptr macro is modified to deal with both vmenter/vmexit and
vmtrap operations, and now takes an optional label that is branched to
when the guest hasn't touched the VFP registers.

Reported-by: Vikram Sethi <vikrams@codeaurora.org>
Cc: stable@kernel.org	# v3.9+
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-06-17 09:40:14 +01:00
Shreyas B. Prabhu 3609d819a3 powerpc: Make doorbell check preemption safe
Doorbell can be used to cause ipi on cpus which are sibling threads on
the same core. So icp_native_cause_ipi checks if the destination cpu
is a sibling thread of the current cpu and uses doorbell in such cases.

But while running with CONFIG_PREEMPT=y, since this section is
preemtible, we can run into issues if after we check if the destination
cpu is a sibling cpu, the task gets migrated from a sibling cpu to a
cpu on another core.

Fix this by using get_cpu()/ put_cpu()

Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-17 08:01:03 +10:00
Paul Gortmaker b0c6d93014 MIPS: don't use module_init in non-modular cobalt/mtd.c file
As of commit 34b1252bd9 ("MIPS:
Cobalt: Do not build MTD platform device registration code as module.")
this file became built-in instead of modular.  So we should also
stop using module_init as an alias for __initcall as that can be
rather misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Direct use of __initcall is discouraged, vs prioritized ones.
Use of device_initcall is consistent with what __initcall
maps onto, and hence does not change the init order, making the
impact of this change zero.

Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:34:36 -04:00
Paul Gortmaker 32e805e7c6 tile: add init.h to usb.c to avoid compile failure
Pending header cleanups will reveal this file is using the
init.h content implicitly with the following fail:

arch/tile/kernel/usb.c:69:1: warning: data definition has no type or storage class [enabled by default]
arch/tile/kernel/usb.c:69:1: error: type defaults to 'int' in declaration of 'arch_initcall'
arch/tile/kernel/usb.c:69:1: warning: parameter names (without types) in function declaration [enabled by default]
arch/tile/kernel/usb.c:62:19: warning: 'tilegx_usb_init' defined but not used

Explicitly add init.h to get arch_initcall and avoid this.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: Chris Metcalf <cmetcalf@ezchip.com>
Acked-by: Chris Metcalf <cmetcalf@ezchip.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:41 -04:00
Paul Gortmaker 9b9cf81a2d arm: fix implicit #include <linux/init.h> in entry asm.
They use the "_INIT" macro and friends, and hence need to
source this header file, vs. relying on getting it implicitly.

Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:41 -04:00
Paul Gortmaker 70c4f78b23 x86: replace __init_or_module with __init in non-modular vsmp_64.c
The __init_or_module is from commit 05e12e1c4c
("x86: fix 27-rc crash on vsmp due to paravirt during module load").

But as of commit 70511134f6
("Revert "x86: don't compile vsmp_64 for 32bit") this file became
obj-y and hence is now only for built-in.  That makes any
"_or_module" support no longer necessary.

We need to distinguish between the two in order to do some header
reorganization between init.h and module.h and we don't want to
be including module.h in non-modular code.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:41 -04:00
Paul Gortmaker 5b00c1eb94 x86: perf_event_intel_pt.c: use arch_initcall to hook in enabling
This was using module_init, but the current Kconfig situation is
as follows:

In arch/x86/kernel/cpu/Makefile:

  obj-$(CONFIG_CPU_SUP_INTEL)    += perf_event_intel_pt.o perf_event_intel_bts.o

and in arch/x86/Kconfig.cpu:

  config CPU_SUP_INTEL
        default y
        bool "Support Intel processors" if PROCESSOR_SELECT

So currently, the end user can not build this code into a module.
If in the future, there is desire for this to be modular, then
it can be changed to include <linux/module.h> and use module_init.

But currently, in the non-modular case, a module_init becomes a
device_initcall.  But this really isn't a device, so we should
choose a more appropriate initcall bucket to put it in.

The obvious choice here seems to be arch_initcall, but that does
make it earlier than it was currently through device_initcall.
As long as perf_pmu_register() is functional, we should be OK.

Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:35 -04:00
Paul Gortmaker ca41d24cf5 x86: perf_event_intel_bts.c: use arch_initcall to hook in enabling
This was using module_init, but the current Kconfig situation is
as follows:

In arch/x86/kernel/cpu/Makefile:

  obj-$(CONFIG_CPU_SUP_INTEL)    += perf_event_intel_pt.o perf_event_intel_bts.o

and in arch/x86/Kconfig.cpu:

  config CPU_SUP_INTEL
        default y
        bool "Support Intel processors" if PROCESSOR_SELECT

So currently, the end user can not build this code into a module.
If in the future, there is desire for this to be modular, then
it can be changed to include <linux/module.h> and use module_init.

But currently, in the non-modular case, a module_init becomes a
device_initcall.  But this really isn't a device, so we should
choose a more appropriate initcall bucket to put it in.

The obvious choice here seems to be arch_initcall, but that does
make it earlier than it was currently through device_initcall.
As long as perf_pmu_register() is functional, we should be OK.

Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:35 -04:00
Paul Gortmaker 6f114281c4 powerpc: don't use module_init for non-modular core hugetlb code
The hugetlbpage.o is obj-y (always built in).  It will never
be modular, so using module_init as an alias for __initcall is
somewhat misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of arch_initcall (which
makes sense for arch code) will thus change this registration
from level 6-device to level 3-arch (i.e. slightly earlier).
However no observable impact of that small difference has
been observed during testing, or is expected.

Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:34 -04:00
Paul Gortmaker 383d14a536 powerpc: use subsys_initcall for Freescale Local Bus
The FSL_SOC option is bool, and hence this code is either
present or absent.  It will never be modular, so using
module_init as an alias for __initcall is rather misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of subsys_initcall (which
makes sense for bus code) will thus change this registration
from level 6-device to level 4-subsys (i.e. slightly earlier).
However no observable impact of that small difference has
been observed during testing, or is expected.

Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:34 -04:00
Paul Gortmaker 1206f53589 x86: don't use module_init for non-modular core bootflag code
The bootflag.o is obj-y (always built in).  It will never be
modular, so using module_init as an alias for __initcall is
somewhat misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of arch_initcall (which
makes sense for arch code) will thus change this registration
from level 6-device to level 3-arch (i.e. slightly earlier).
However no observable impact of that small difference has
been observed during testing, or is expected.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:34 -04:00
Paul Gortmaker 84c3e5bf1d cris: don't use module_init for non-modular core eeprom.c code
The eeprom.c code is compiled based on the Kconfig setting
ETRAX_I2C_EEPROM, which is bool.  So the code is either built in
or absent.  It will never be modular, so using module_init as an
alias for __initcall is rather misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Direct use of __initcall is discouraged, vs prioritized ones.
Use of device_initcall is consistent with what __initcall
maps onto, and hence does not change the init order, making the
impact of this change zero.   Should someone with real hardware
for boot testing want to change it later to arch_initcall or
something different, they can do that at a later date.

Cc: Mikael Starvik <starvik@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: linux-cris-kernel@axis.com
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:31 -04:00
Paul Gortmaker 30e3c6428f xtensa: don't use module_init for non-modular core network.c code
The network.c code is piggybacking off of the arch independent
CONFIG_NET, which is bool.  So the code is either built in or
absent.  It will never be modular, so using module_init as an
alias for __initcall is rather misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Direct use of __initcall is discouraged, vs prioritized ones.
Use of device_initcall is consistent with what __initcall
maps onto, and hence does not change the init order, making the
impact of this change zero.   Should someone with real hardware
for boot testing want to change it later to arch_initcall or
something different, they can do that at a later date.

Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Thomas Meyer <thomas@m3y3r.de>
Cc: linux-xtensa@linux-xtensa.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:31 -04:00
Paul Gortmaker b205118bdb sh: don't use module_init in non-modular psw.c code
The psw.o is built for obj-y -- and hence this code is always
present.  It will never be modular, so using module_init as an alias
for __initcall can be somewhat misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:31 -04:00
Paul Gortmaker 1b4d5beecb mn10300: don't use module_init in non-modular flash.c code
The flash.o is built for obj-y -- and hence this code is always
present.  It will never be modular, so using module_init as an alias
for __initcall can be somewhat misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: David Howells <dhowells@redhat.com>
Acked-by: David Howells <dhowells@redhat.com>
Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
Cc: linux-am33-list@redhat.com
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:30 -04:00
Paul Gortmaker 15becabd89 parisc64: don't use module_init for non-modular core perf code
The perf.c code depends on CONFIG_64BIT, so it is either built-in
or absent.  It will never be modular, so using module_init as an
alias for __initcall is rather misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.  Aside from it not making sense, it also
causes a ~10% increase in CPP overhead due to module.h having a
large list of headers itself -- for example compare line counts:

 device_initcall() and <linux/init.h>
	20238 arch/parisc/kernel/perf.i

 module_init() and <linux/module.h>
	22194 arch/parisc/kernel/perf.i

Direct use of __initcall is discouraged, vs prioritized ones.
Use of device_initcall is consistent with what __initcall
maps onto, and hence does not change the init order, making the
impact of this change zero.   Should someone with real hardware
for boot testing want to change it later to arch_initcall or
something different, they can do that at a later date.

Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
Cc: Helge Deller <deller@gmx.de>
Cc: linux-parisc@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:30 -04:00
Paul Gortmaker aed6850a13 parisc: don't use module_init for non-modular core pdc_cons code
The pdc_cons.c code is always built in.  It will never be modular,
so using module_init as an alias for __initcall is rather
misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Direct use of __initcall is discouraged, vs prioritized ones.
Use of device_initcall is consistent with what __initcall
maps onto, and hence does not change the init order, making the
impact of this change zero.   Should someone with real hardware
for boot testing want to change it later to arch_initcall or
something different, they can do that at a later date.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
Cc: Helge Deller <deller@gmx.de>
Cc: linux-parisc@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:30 -04:00
Paul Gortmaker 73de14e8cd cris: don't use module_init for non-modular core intmem.c code
The intmem.c code is always built in.  It will never be modular,
so using module_init as an alias for __initcall is rather
misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Direct use of __initcall is discouraged, vs prioritized ones.
Use of device_initcall is consistent with what __initcall
maps onto, and hence does not change the init order, making the
impact of this change zero.   Should someone with real hardware
for boot testing want to change it later to arch_initcall or
something different, they can do that at a later date.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: Mikael Starvik <starvik@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: linux-cris-kernel@axis.com
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:30 -04:00
Paul Gortmaker 2a177fd1d9 ia64: don't use module_init in non-modular sim/simscsi.c code
The simscsi.o is built for HP_SIMSCSI -- which is bool, and hence
this code is either present or absent.  It will never be modular,
so using module_init as an alias for __initcall can be somewhat
misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.

And since it can't be modular, we remove all the __exitcall
stuff related to module_exit() -- it is dead code that won't
ever be executed.

Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: linux-ia64@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:30 -04:00
Paul Gortmaker 2e21fa2d11 ia64: don't use module_init for non-modular core kernel/mca.c code
The mca.c code is always built in.  It will never be modular,
so using module_init as an alias for __initcall is rather
misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Direct use of __initcall is discouraged, vs prioritized ones.
Use of device_initcall is consistent with what __initcall
maps onto, and hence does not change the init order, making the
impact of this change zero.   Should someone with real hardware
for boot testing want to change it later to arch_initcall or
something different, they can do that at a later date.

Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: linux-ia64@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:30 -04:00
Paul Gortmaker 4a0ece7cec arm: don't use module_init in non-modular mach-vexpress/spc.c code
The spc.o is built for ARCH_VEXPRESS_SPC -- which is bool, and hence
this code is either present or absent.  It will never be modular,
so using module_init as an alias for __initcall can be somewhat
misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.

Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:29 -04:00
Paul Gortmaker a390a2f181 powerpc: don't use module_init in non-modular 83xx suspend code
The suspend.o is built for SUSPEND -- which is bool, and hence
this code is either present or absent.  It will never be modular,
so using module_init as an alias for __initcall can be somewhat
misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:29 -04:00
Paul Gortmaker 8f6b9512ce powerpc: use device_initcall for registering rtc devices
Currently these two RTC devices are in core platform code
where it is not possible for them to be modular.  It will
never be modular, so using module_init as an alias for
__initcall can be somewhat misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- they will remain at level 6 in initcall ordering.

Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Geoff Levand <geoff@infradead.org>
Acked-by: Geoff Levand <geoff@infradead.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:29 -04:00
Paul Gortmaker d54b675a6b x86: don't use module_init in non-modular devicetree.c code
The devicetree.o is built for "OF" -- which is bool, and hence
this code is either present or absent.  It will never be modular,
so using module_init as an alias for __initcall can be somewhat
misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:29 -04:00
Paul Gortmaker 4711e2f9ca x86: don't use module_init in non-modular intel_mid_vrtc.c
The X86_INTEL_MID option is bool, and hence this code is either
present or absent.  It will never be modular, so using
module_init as an alias for __initcall is rather misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:29 -04:00
Paul Gortmaker 7cac34370a frv: add module.h to mb93090-mb00/flash.c to avoid compile fail
This file is built off of a tristate Kconfig option and also contains
modular function calls so it should explicitly include module.h to
avoid compile breakage during header shuffles done in the future.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: David Howells <dhowells@redhat.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:26 -04:00
Paul Gortmaker 0bbad249a6 sh: mach-highlander/psw.c is tristate and should use module.h
This file is controlled by a tristate Kconfig option, and hence
needs to include module.h so that it can get module_init() once
we relocate it from init.h into module.h in the future.

Note that module_exit() appears to be missing from the driver, so
it is questionable whether it would actually work for a removal
and reload cycle if it was configured for a modular build.

Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:26 -04:00
Paul Gortmaker 87d0729edd mips/mm/tlbex: remove new instance of __cpuinit that crept back in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a new instance was added in commit c5b367835c
("MIPS: Add support for XPA.")

Since we want to clobber the stubs soon, get this removed now.

Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:22 -04:00
Paul Gortmaker 719cc170b0 mips/c-r4k: remove legacy __cpuinit section that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a new instance was added in commit 4caa906ee9
("MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functions")

Since we want to clobber the stubs soon, get this removed now.

Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:22 -04:00
Paul Gortmaker 52252c3ed7 mips/bcm77xx: remove legacy __cpuinit sections that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a few more crept in as of commit 6ee1d93455
("MIPS: BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)")

Since we want to clobber the stubs soon, get this removed now.

Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:22 -04:00
Paul Gortmaker 01f0aa8ed7 mips/ath25: remove legacy __cpuinit section that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However this one crept back in as of commit 43cc739fd9
("MIPS: ath25: add common parts")

Since we want to clobber the stubs soon, get this removed now.

Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Acked-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:22 -04:00
Paul Gortmaker 6a15fe9f2d arm/mach-hisi: remove legacy __CPUINIT section that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a new instance was added in commit 06cc5c1d4d
("ARM: hisi: enable hix5hd2 SoC")

Since we want to clobber the stubs soon, get this removed now.
Note that there would normally be a corresponding removal of
a ".previous" directive, but in this case it appears that this
single function file was never paired off with one.

Cc: Haifeng Yan <yanhaifeng@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:21 -04:00
Paul Gortmaker 374d4dd3ef arm/mach-rockchip: remove legacy __cpuinit section that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However this one crept back in as of commit a7a2b3118b
("ARM: rockchip: add smp bringup code").

Since we want to clobber the stubs soon, get this removed now.

Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:21 -04:00
Paul Gortmaker ff6138ad19 arm/mach-mvebu: remove legacy __cpuinit sections that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time
ago.  However these ones crept back in as of commit 1ee89e2231
("ARM: mvebu: add SMP support for Armada 375 and Armada 38x")

Since we want to clobber the stubs soon, get this removed now.
Note that there would normally be a corresponding removal of
a ".previous" directive for each __CPUINIT in asm files, but in
this case it appears that this single function file was never
paired off with one.

Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:21 -04:00
Paul Gortmaker 02d6e63307 arm/mach-keystone: remove legacy __cpuinit sections that crept in
We removed __cpuinit support (leaving no-op stubs) quite some time
ago.  However two crept back in as of commit 5eb3da7246
("ARM: keystone: Switch over to coherent memory address space")

Since we want to clobber the stubs too, get these removed now.

Cc: Santosh Shilimkar <ssantosh@kernel.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:21 -04:00
Bjorn Helgaas bf933dbb84 Merge branches 'pci/host-designware', 'pci/host-designware-common', 'pci/host-generic', 'pci/host-imx6', 'pci/host-iproc' and 'pci/host-xgene' into next
* pci/host-designware:
  PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM
  PCI: designware: Consolidate outbound iATU programming functions
  PCI: designware: Add support for x8 links

* pci/host-designware-common:
  PCI: designware: Wait for link to come up with consistent style
  PCI: layerscape: Factor out ls_pcie_establish_link()
  PCI: layerscape: Use dw_pcie_link_up() consistently
  PCI: dra7xx: Use dw_pcie_link_up() consistently
  PCI: imx6: Rename imx6_pcie_start_link() to imx6_pcie_establish_link()

* pci/host-generic:
  of/pci: Fix pci_address_to_pio() conversion of CPU address to I/O port

* pci/host-imx6:
  PCI: imx6: Add #define PCIE_RC_LCSR
  PCI: imx6: Use "u32", not "uint32_t"
  PCI: imx6: Add speed change timeout message

* pci/host-iproc:
  PCI: iproc: Free resource list after registration
  PCI: iproc: Directly add PCI resources
  PCI: iproc: Add BCMA PCIe driver
  PCI: iproc: Allow override of device tree IRQ mapping function

* pci/host-xgene:
  arm64: dts: Add APM X-Gene PCIe MSI nodes
  PCI: xgene: Add APM X-Gene v1 PCIe MSI/MSIX termination driver
2015-06-16 08:19:55 -05:00
Luis R. Rodriguez 6c6685055a kconfig: add xenconfig defconfig helper
This lets you build a kernel which can support xen dom0
or xen guests on i386, x86-64 and arm64 by just using:

   make xenconfig

You can start from an allnoconfig and then switch to xenconfig.
This also splits out the options which are available currently
to be built with x86 and 'make ARCH=arm64' under a shared config.

Technically xen supports a dom0 kernel and also a guest
kernel configuration but upon review with the xen team
since we don't have many dom0 options its best to just
combine these two into one.

A few generic notes: we enable both of these:

CONFIG_INET=y
CONFIG_BINFMT_ELF=y

although technically not required given you likely will
end up with a pretty useless system otherwise.

A few architectural differences worth noting:

$ make allnoconfig; make xenconfig > /dev/null ; \
	grep XEN .config > 64-bit-config
$ make ARCH=i386 allnoconfig; make ARCH=i386 xenconfig > /dev/null; \
	grep XEN .config > 32-bit-config
$ make ARCH=arm64 allnoconfig; make ARCH=arm64 xenconfig > /dev/null; \
	grep XEN .config > arm64-config

Since the options are already split up with a generic config and
architecture specific configs you anything on the x86 configs
are known to only work right now on x86. For instance arm64 doesn't
support MEMORY_HOTPLUG yet as such although we try to enabe it
generically arm64 doesn't have it yet, so we leave the xen
specific kconfig option XEN_BALLOON_MEMORY_HOTPLUG on x86's config
file to set expecations correctly.

Then on x86 we have differences between i386 and x86-64. The difference
between 64-bit-config and 32-bit-config is you don't get XEN_MCE_LOG as
this is only supported on 64-bit. You also do not get on i386
XEN_BALLOON_MEMORY_HOTPLUG, there does not seem to be any technical
reasons to not allow this but I gave up after a few attempts.

Cc: Josh Triplett <josh@joshtriplett.org>
Cc: Borislav Petkov <bp@suse.de>
Cc: Pekka Enberg <penberg@kernel.org>
Cc: David Rientjes <rientjes@google.com>
Cc: Michal Marek <mmarek@suse.cz>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: penberg@kernel.org
Cc: levinsasha928@gmail.com
Cc: mtosatti@redhat.com
Cc: fengguang.wu@intel.com
Cc: David Vrabel <david.vrabel@citrix.com>
Cc: Ian Campbell <Ian.Campbell@citrix.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: xen-devel@lists.xenproject.org
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Michal Marek <mmarek@suse.cz>
Acked-by: David Rientjes <rientjes@google.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com>
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
2015-06-16 11:04:29 +01:00
Joe Perches 73cb9dc0cd m68k: Use vsprintf %pM extension
Format mac addresses with the normal kernel extension.

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2015-06-16 16:45:38 +10:00
Radim Krčmář b6ac069532 KVM: x86: fix lapic.timer_mode on restore
lapic.timer_mode was not properly initialized after migration, which
broke few useful things, like login, by making every sleep eternal.

Fix this by calling apic_update_lvtt in kvm_apic_post_state_restore.

There are other slowpaths that update lvtt, so this patch makes sure
something similar doesn't happen again by calling apic_update_lvtt
after every modification.

Cc: stable@vger.kernel.org
Fixes: f30ebc312c ("KVM: x86: optimize some accesses to LVTT and SPIV")
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2015-06-16 01:01:10 -03:00
Vaishali Thakkar 2587dc65e1 ia64: Use setup_timer
Use the timer API function setup_timer instead of structure field
assignments to initialize a timer.

A simplified version of the Coccinelle semantic patch that performs
this transformation is as follows:

@change@
expression e1, e2, a;
@@

-init_timer(&e1);
+setup_timer(&e1, a, 0UL);
... when != a = e2
-e1.function = a;

Signed-off-by: Vaishali Thakkar <vthakkar1994@gmail.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2015-06-15 15:45:18 -07:00
Luis R. Rodriguez 511beeb588 ia64: export flush_icache_range for module use
This is needed the following modules:

"Linux Kernel Dump Test Tool Module"
CONFIG_LKDTM		drivers/misc/lkdtm.c

Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2015-06-15 14:58:24 -07:00
Mark Rutland 822bf4833e arm64: defconfig: enable memtest
The kernel memtest utility is incredibly useful for detecting memory
problems, but sadly isn't in defconfig.

The memtest itself is only run when the user has explicitly passed a
memtest option on the kernel command line, so simply enabling the option
should not have a negative impact.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-15 16:57:46 +01:00
Suthikulpanit, Suravee b6197b93fa arm64 : Introduce support for ACPI _CCA object
section 6.2.17 _CCA states that ARM platforms require ACPI _CCA
object to be specified for DMA-cabpable devices. Therefore, this patch
specifies ACPI_CCA_REQUIRED in arm64 Kconfig.

In addition, to handle the case when _CCA is missing, arm64 would assign
dummy_dma_ops to disable DMA capability of the device.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2015-06-15 14:40:49 +02:00
Jeremiah Mahler de1e00871d crypto: aesni - fix crypto_fpu_exit() section mismatch
The '__init aesni_init()' function calls the '__exit crypto_fpu_exit()'
function directly.  Since they are in different sections, this generates
a warning.

  make CONFIG_DEBUG_SECTION_MISMATCH=y
  ...
  WARNING: arch/x86/crypto/aesni-intel.o(.init.text+0x12b): Section
  mismatch in reference from the function init_module() to the function
  .exit.text:crypto_fpu_exit()
  The function __init init_module() references
  a function __exit crypto_fpu_exit().
  This is often seen when error handling in the init function
  uses functionality in the exit path.
  The fix is often to remove the __exit annotation of
  crypto_fpu_exit() so it may be used outside an exit section.

Fix the warning by removing the __exit annotation.

Signed-off-by: Jeremiah Mahler <jmmahler@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-15 18:15:58 +08:00
Geert Uytterhoeven 4e0a64124f s390/mm: s/specifiation/specification/, s/an specification/a specification/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-15 10:50:48 +02:00
Michael Ellerman 4bece972fc powerpc/powernv: pnv_init_idle_states() should only run on powernv
Although this init call checks for device tree properties before doing
anything, it should still only run on powernv machines.

Reviewed-by: Shreyas B Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-15 16:45:12 +10:00
Linus Torvalds 1f1e34f723 Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull more MIPS fixes from Ralf Baechle:
 "Another round of 4.1 MIPS fixes, one fix to a MIPS-specific #if
  condition in lib/mpi, one fix to the MIPS GIC irqchip driver and one
  SSB fix.

  Details:
   - fix handling of clock in chipco SSB driver.
   - fix two MIPS-specific #if conditions to correctly work for GCC 5.1.
   - fix damage to R6 pgtable bits done by XPA support.
   - fix possible crash due to unloading modules that contain statically
     defined platform devices.
   - fix disabling of the MSA ASE on context switch to also work
     correctly when a new thread/process has the CPU for the very first
     time.

  This is part of linux-next and has been beaten to death on
  Imagination's test farm.

  While things are not looking too grim this pull request also means the
  rate of fixes for 4.1 remains nearly constant so I'd not be unhappy if
  you'd delay the release"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MPI: MIPS: Fix compilation error with GCC 5.1
  IRQCHIP: mips-gic: Don't nest calls to do_IRQ()
  MIPS: MSA: bugfix - disable MSA correctly for new threads/processes.
  MIPS: Loongson: Do not register 8250 platform device from module.
  MIPS: Cobalt: Do not build MTD platform device registration code as module.
  SSB: Fix handling of ssb_pmu_get_alp_clock()
  MIPS: pgtable-bits: Fix XPA damage to R6 definitions.
2015-06-14 15:38:57 -10:00
Linus Torvalds d37479aac5 Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar:
 "A regression fix for a crash, and a Intel HSW uncore PMU driver fix"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  Revert "perf/x86/intel/uncore: Move uncore_box_init() out of driver initialization"
  perf/x86/intel/uncore: Fix CBOX bit wide and UBOX reg on Haswell-EP
2015-06-14 14:00:13 -10:00
David S. Miller 25c43bf13b Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 2015-06-13 23:56:52 -07:00
Kevin Hilman e75ea4569d Merge branch 'for-arm-soc' of http://ftp.arm.linux.org.uk/pub/armlinux/kernel/git-cur/linux-2.6-arm into next/cleanup
* 'for-arm-soc' of http://ftp.arm.linux.org.uk/pub/armlinux/kernel/git-cur/linux-2.6-arm:
  ARM: fix EFM32 build breakage caused by cpu_resume_arm
  ARM: 8389/1: Add cpu_resume_arm() for firmwares that resume in ARM state
  ARM: v7 setup function should invalidate L1 cache
2015-06-12 13:40:12 -07:00
Kevin Hilman dec36f6ab8 ARM: multi_v7_defconfig: remove duplicate CONFIG_COMMON_CLK_QCOM=y
commit dcf9a03bff (ARM: multi_v7_defconfig: Enable PMIC and MUIC
drivers for exynos) mistakenly added an duplicate line for
CONFIG_COMMON_CLK_QCOM=y.  Remove it.

Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-12 13:30:53 -07:00
Russell King 9ce93bdda7 ARM: fix new BSYM() usage introduced via for-arm-soc branch
Commit 32e55a777f ("ARM: 8389/1: Add cpu_resume_arm() for firmwares
that resume in ARM state") needed to introduce a new usage of BSYM()
to fix a problem with a previous patch.  This in turn causes a conflict
with the "bsym" branch which removes this symbol, replacing it with a
'badr' assembly macro.  Fix this up.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-12 21:19:35 +01:00
Russell King a9dd3865dd Merge branch 'for-arm-soc' into for-next 2015-06-12 21:18:59 +01:00
Russell King 27a513ca86 Merge branch 'devel-stable' into for-next
Conflicts:
	arch/arm/kernel/perf_event_cpu.c
2015-06-12 21:18:57 +01:00
Stefan Agner 970d96f9a8 ARM: 8383/1: nommu: avoid deprecated source register on mov
In Thumb2 mode, the stack register r13 is deprecated if the
destination register is the program counter (r15). Similar to
head.S, head-nommu.S uses r13 to store the return address used
after configuring the CPU's CP15 register. However, since we do
not enable a MMU, there will be no address switch and it is
possible to use branch with link instruction to call
__after_proc_init.

Avoid using r13 completely by using bl to call __after_proc_init
and get rid of __secondary_switched.

Beside removing unnecessary complexity, this also fixes a
compiler warning when compiling a !MMU kernel:
Warning: Use of r13 as a source register is deprecated when r15
is the destination register.

Tested-?by: Maxime Coquelin <mcoquelin.stm32@gmail.com>

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-12 21:18:48 +01:00
Russell King 05c9ca8843 Merge branch 'bsym' into for-next
Conflicts:
	arch/arm/kernel/head.S
2015-06-12 21:18:38 +01:00
Russell King c62af70ff3 Merge branch 'sa1100' into for-next 2015-06-12 21:18:13 +01:00
Russell King 9de44aa4dc Merge branches 'arnd-fixes', 'clk', 'misc', 'v7' and 'fixes' into for-next 2015-06-12 21:18:08 +01:00
Russell King 2678bb9fa1 ARM: fix EFM32 build breakage caused by cpu_resume_arm
Fix:
arch/arm/kernel/sleep.S:121: Error: selected processor does not support ARM opcodes
arch/arm/kernel/sleep.S:123: Error: attempt to use an ARM instruction on a Thumb-only processor -- `adr r9,1f+1'
arch/arm/kernel/sleep.S:124: Error: attempt to use an ARM instruction on a Thumb-only processor -- `bx r9'

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-12 21:17:37 +01:00
Stephen Boyd 32e55a777f ARM: 8389/1: Add cpu_resume_arm() for firmwares that resume in ARM state
Some platforms always enter the kernel in the ARM state even if
the kernel is compiled for THUMB2. Add a small wrapper on top of
cpu_resume() that switches into THUMB2 state.

This provides the functionality to fix a problem reported by Kevin
Hilman on next-20150601 where the ifc6410 fails to boot a THUMB2
kernel because the platform's firmware always enters the kernel in
ARM mode from deep idle states.

(rmk: tweaked to work without BSYM->badr changes.)

Reported-by: Kevin Hilman <khilman@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-12 21:17:17 +01:00
Vladimir Murzin c7d6b573fe arm64: mm: remove reference to tlb.S from comment block
tlb.S has been removed since fa48e6f "arm64: mm: Optimise tlb flush logic
where we have >4K granule", so align comment with that.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-12 15:36:52 +01:00
Catalin Marinas 565630d503 arm64: Do not attempt to use init_mm in reset_context()
After secondary CPU boot or hotplug, the active_mm of the idle thread is
&init_mm. The init_mm.pgd (swapper_pg_dir) is only meant for TTBR1_EL1
and must not be set in TTBR0_EL1. Since when active_mm == &init_mm the
TTBR0_EL1 is already set to the reserved value, there is no need to
perform any context reset.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: <stable@vger.kernel.org>
2015-06-12 15:36:18 +01:00
Marc Zyngier 8a14849b4a arm64: KVM: Switch vgic save/restore to alternative_insn
So far, we configured the world-switch by having a small array
of pointers to the save and restore functions, depending on the
GIC used on the platform.

Loading these values each time is a bit silly (they never change),
and it makes sense to rely on the instruction patching instead.

This leads to a nice cleanup of the code.

Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-12 15:12:08 +01:00
Marc Zyngier 94a9e04aa1 arm64: alternative: Introduce feature for GICv3 CPU interface
Add a new item to the feature set (ARM64_HAS_SYSREG_GIC_CPUIF)
to indicate that we have a system register GIC CPU interface

This will help KVM switching to alternative instruction patching.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-06-12 15:11:50 +01:00
Feng Wu 959c870f73 iommu, x86: Provide irq_remapping_cap() interface
Add a new interface irq_remapping_cap() to detect whether irq
remapping supports new features, such as VT-d Posted-Interrupts.

Export the function, so that KVM code can check this and use this
mechanism properly.

Signed-off-by: Feng Wu <feng.wu@intel.com>
Reviewed-by: Jiang Liu <jiang.liu@linux.intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org
Cc: dwmw2@infradead.org
Link: http://lkml.kernel.org/r/1433827237-3382-10-git-send-email-feng.wu@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-12 11:33:52 +02:00
Feng Wu 8541186faf iommu, x86: Implement irq_set_vcpu_affinity for intel_ir_chip
Interrupt chip callback to set the VCPU affinity for posted interrupts.

[ tglx: Use the helper function to copy from the remap irte instead of
        open coding it. Massage the comment as well ]

Signed-off-by: Feng Wu <feng.wu@intel.com>
Reviewed-by: Jiang Liu <jiang.liu@linux.intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: iommu@lists.linux-foundation.org
Cc: joro@8bytes.org
Cc: dwmw2@infradead.org
Link: http://lkml.kernel.org/r/1433827237-3382-5-git-send-email-feng.wu@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-12 11:33:52 +02:00
Feng Wu 6f28192394 iommu: Add new member capability to struct irq_remap_ops
Add a new member 'capability' to struct irq_remap_ops for storing
information about available capabilities such as VT-d
Posted-Interrupts.

Signed-off-by: Feng Wu <feng.wu@intel.com>
Reviewed-by: Jiang Liu <jiang.liu@linux.intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org
Cc: dwmw2@infradead.org
Link: http://lkml.kernel.org/r/1433827237-3382-2-git-send-email-feng.wu@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-12 11:33:51 +02:00
Dave Hansen a842400367 x86/fpu: Fix double-increment in setup_xstate_features()
I noticed that my MPX tracepoints were producing garbage for the
lower and upper bounds:

	mpx_bounds_register_exception: address referenced: 0x00007fffffffccb7 bounds: lower: 0x0 ~upper: 0xffffffffffffffff
	mpx_bounds_register_exception: address referenced: 0x00007fffffffccbf bounds: lower: 0x0 ~upper: 0xffffffffffffffff

This is, of course, bogus because 0x00007fffffffccbf is *within*
the bounds.  I assumed that my instruction decoder was bad and
went looking at it.  But I eventually realized that I was
getting a '0' offset back from xstate_offsets[BNDREGS].

It was being skipped in the initialization, which is obviously
bogus, so remove the extra leaf++.

This also goes an initializes xstate_offsets/sizes[] to -1 so
so that bugs like this will oops instead of silently failing
in interesting ways.

This was introduced by:

	39f1acd ("x86/fpu/xstate: Don't assume the first zero xfeatures zero bit means the end")

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: dave@sr71.net
Link: http://lkml.kernel.org/r/20150611193400.2E0B00DB@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-06-12 10:48:12 +02:00
Kevin Hilman 2879e43f09 Omap hwmod changes for v4.2 via Paul Walmsley <paul@pwsan.com>:
Several OMAP2+ hwmod changes for v4.2.  One patch cleans up a nasty
 interaction between the OMAP GPMC and the hwmod code when debugging is
 enabled.  IP block integration data has been added for the AM43xx EMIF
 RAM controller.  There's also a fix for the omap-aes driver when used in
 QEMU.  And finally, some changes to the OMAP3 hwmod code to support the
 use of the security IP blocks (AES and SHA) on GP devices, or when they've
 specifically been enabled in the DT data.
 
 Basic build, boot, and power management test results are here:
 
 http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.2/20150601192349/
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Merge tag 'omap-for-v4.2/soc-pt1-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Omap hwmod changes for v4.2 via Paul Walmsley <paul@pwsan.com>:

Several OMAP2+ hwmod changes for v4.2.  One patch cleans up a nasty
interaction between the OMAP GPMC and the hwmod code when debugging is
enabled.  IP block integration data has been added for the AM43xx EMIF
RAM controller.  There's also a fix for the omap-aes driver when used in
QEMU.  And finally, some changes to the OMAP3 hwmod code to support the
use of the security IP blocks (AES and SHA) on GP devices, or when they've
specifically been enabled in the DT data.

Basic build, boot, and power management test results are here:

http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.2/20150601192349/

* tag 'omap-for-v4.2/soc-pt1-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP3: Fix crypto support for HS devices
  ARM: OMAP2+: Return correct error values from device and hwmod
  ARM: OMAP: AM43xx hwmod: Add data for am43xx emif hwmod
  memory: omap-gpmc: Add Kconfig option for debug
2015-06-11 16:36:32 -07:00
Kevin Hilman b3f30fb41b Few omap2plus_defconfig changes for v4.2 merge window:
- Enable dm9000 as built-in for NFSroot
 
 - Enable dm816x USB phy as a loadable module
 
 - Enable Pixcir touch screen as a loadable module
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Merge tag 'omap-for-v4.2/o2_dc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/defconfig

Few omap2plus_defconfig changes for v4.2 merge window:

- Enable dm9000 as built-in for NFSroot

- Enable dm816x USB phy as a loadable module

- Enable Pixcir touch screen as a loadable module

* tag 'omap-for-v4.2/o2_dc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: omap2plus_defconfig: Enable TOUCHSCREEN_PIXCIR
  ARM: omap2plus_defconfig: Add dm816x USB PHY as a loadable module
  ARM: omap2plus_defconifg: Enable DM9000 in omap2plus_defconfig
2015-06-11 16:33:20 -07:00
Kevin Hilman 1647e3c73c Few more omap device tree changes for v4.2 merge window:
- Add dm9000 Ethernet support to omap3-devkit8000
 
 - Add Toby-Churchill SL50 board support
 
 - Add vendor prefix for Toby Churchill Ltd
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Merge tag 'omap-for-v4.2/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Few more omap device tree changes for v4.2 merge window:

- Add dm9000 Ethernet support to omap3-devkit8000

- Add Toby-Churchill SL50 board support

- Add vendor prefix for Toby Churchill Ltd

* tag 'omap-for-v4.2/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: am335x-sl50: Add Toby-Churchill SL50 board support.
  of: Add vendor prefix for Toby Churchill Ltd.
  ARM: dts: omap3-devkit8000: Add dm9000 support
2015-06-11 16:30:19 -07:00
Kevin Hilman 4d48614ec4 Merge branch 'zte/soc' into next/soc
* zte/soc:
  ARM: zx: Add basic defconfig support for ZX296702
  ARM: dts: zx: add an initial zx296702 dts and doc
  clk: zx: add clock support to zx296702
  dt-bindings: Add #defines for ZTE ZX296702 clocks
2015-06-11 16:19:29 -07:00
Jun Nie 405817f678 ARM: zx: Add basic defconfig support for ZX296702
Add basic defconfig support to zx SOC, including uart, mmc
 and other common config

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11 16:18:31 -07:00
Jun Nie d5553cb05a ARM: dts: zx: add an initial zx296702 dts and doc
Add initial dts file and document for ZX296702 and board ZX296702-AD1.
More peripherals will be added later.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11 16:18:30 -07:00
Kevin Hilman 259f47eb44 Merge branch 'socfpga/soc' into next/soc
* socfpga/soc:
  ARM: socfpga: fix build error due to secondary_startup
2015-06-11 15:50:10 -07:00
Kevin Hilman 89b8da06ba ARM: socfpga: fix build error due to secondary_startup
After commit 02b4e2756e (ARM: v7 setup function should invalidate L1
cache) the soc specific secondary_startup is removed, causing build
failures:

../arch/arm/mach-socfpga/platsmp.c: In function 'socfpga_a10_boot_secondary':
../arch/arm/mach-socfpga/platsmp.c:66:140: error: 'socfpga_secondary_startup' undeclared (first use in this function)
../arch/arm/mach-socfpga/platsmp.c:66:140: note: each undeclared identifier is reported only once for each function it appears in

To fix, use the generic secondary_startup.

Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11 15:41:58 -07:00
Kevin Hilman eec6492861 Samsung updates for v4.2
- add failure(exception) handling
   : of_iomap(), of_find_device_by_node() and kstrdup()
 
 - add common poweroff to use PS_HOLD based for all of exynos SoCs
 - add exnos_get/set_boot_addr() helper
 - constify platform_device_id and irq_domain_ops
 - get current parent clock for power domain on/off
 - use core_initcall to register power domain driver
 - make exynos_core_restart() less verbose
 
 - add support coupled CPUidle for exynos3250
 
 - fix exynos_boot_secondary() return value on timeout
 - fix clk_enable() in s3c24xx adc
 - fix missing of_node_put() for power domains
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Merge tag 'samsung-mach-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

Samsung updates for v4.2

- add failure(exception) handling
  : of_iomap(), of_find_device_by_node() and kstrdup()

- add common poweroff to use PS_HOLD based for all of exynos SoCs
- add exnos_get/set_boot_addr() helper
- constify platform_device_id and irq_domain_ops
- get current parent clock for power domain on/off
- use core_initcall to register power domain driver
- make exynos_core_restart() less verbose

- add support coupled CPUidle for exynos3250

- fix exynos_boot_secondary() return value on timeout
- fix clk_enable() in s3c24xx adc
- fix missing of_node_put() for power domains

* tag 'samsung-mach-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (301 commits)
  ARM: EXYNOS: register power domain driver from core_initcall
  ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
  ARM: SAMSUNG: Constify platform_device_id
  ARM: EXYNOS: Constify irq_domain_ops
  ARM: EXYNOS: add coupled cpuidle support for Exynos3250
  ARM: EXYNOS: add exynos_get_boot_addr() helper
  ARM: EXYNOS: add exynos_set_boot_addr() helper
  ARM: EXYNOS: make exynos_core_restart() less verbose
  ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
  ARM: EXYNOS: Get current parent clock for power domain on/off
  ARM: SAMSUNG: fix clk_enable() WARNing in S3C24XX ADC
  ARM: EXYNOS: Add missing of_node_put() when parsing power domains
  ARM: EXYNOS: Handle of_find_device_by_node() and kstrdup() failures
  ARM: EXYNOS: Handle of of_iomap() failure
  Linux 4.1-rc4
  ....
2015-06-11 14:44:21 -07:00
Kevin Hilman 7d5a0ff5a8 Samsung another DT udpates for v4.2
- use labels for overriding nodes for all of exynos stuff
   (by Krzysztof Kozlowski)
 
 - add sysmmu nodes for exynos SoCs (by Marek Szyprowski)
 
 - for exynos5422-odroidxu3
   : enalbe wake alarm of S2MPS11 RTC
   : Hook up PWM and use it for LEDs
   : add support for Odroid XU3 Lite
 
 - remove duplicated i2c7 for exynos5250-snow
 - add JPEG codec nodes for exynos5420
 - add vendor prefix for Hardkernel
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Merge tag 'samsung-dt-4' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt

Samsung another DT udpates for v4.2

- use labels for overriding nodes for all of exynos stuff
  (by Krzysztof Kozlowski)

- add sysmmu nodes for exynos SoCs (by Marek Szyprowski)

- for exynos5422-odroidxu3
  : enalbe wake alarm of S2MPS11 RTC
  : Hook up PWM and use it for LEDs
  : add support for Odroid XU3 Lite

- remove duplicated i2c7 for exynos5250-snow
- add JPEG codec nodes for exynos5420
- add vendor prefix for Hardkernel

* tag 'samsung-dt-4' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (33 commits)
  ARM: dts: add sysmmu nodes for exynos5420
  ARM: dts: add sysmmu nodes for exynos5250
  ARM: dts: add sysmmu nodes for exynos4415
  ARM: dts: add sysmmu nodes for exynos3250
  ARM: dts: add sysmmu nodes for exynos4
  ARM: dts: Add Odroid XU3 Lite support
  of: Add vendor prefix for Hardkernel
  ARM: dts: odroidxu3: Enable wake alarm of S2MPS11 RTC
  ARM: dts: exynos5420: add nodes for jpeg codec
  ARM: dts: s3c2416: Use labels for overriding nodes in SMDK2416
  ARM: dts: s3c2416: Add labels to S3C2416 nodes
  ARM: dts: Use labels for overriding nodes in exynos5422-odroidxu3
  ARM: dts: Use labels for overriding nodes in exynos5440 boards
  ARM: dts: Use labels for overriding nodes in exynos5420-smdk5420
  ARM: dts: Use labels for overriding nodes in exynos542x
  ARM: dts: Use labels for overriding nodes in exynos5420-arndale-octa
  ARM: dts: Remove duplicated I2C7 nodes in exynos5250-snow
  ARM: dts: Use labels for overriding nodes in exynos5250
  ARM: dts: Add labels to exynos5 nodes
  ARM: dts: exynos5422-odroidxu3: Hook up PWM and use it for LEDs
  ...
2015-06-11 14:39:19 -07:00
Kevin Hilman ecdf94da6f Linux 4.1-rc6
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Merge tag 'v4.1-rc6' into next/dt

Linux 4.1-rc6

 Conflicts:
	arch/arm/boot/dts/zynq-7000.dtsi

Resolution summary:

 Mainline had an earlier version of the commit, resolve in favor of the
 newer patch in next/dt branch.
2015-06-11 14:37:45 -07:00
Kevin Hilman e28f23d8aa Samsung DT updates for v4.2
- for exyos3250
   : use s3c6410-rtc instead of exynos3250-rtc
   : add JPEG codec node and support it on exynos3250-rinato
   : use s3c-rtc clock id for exynos3250-rinato and monk boards
 
 - for exynos4
   : add JPEG codec node and syscon property to MIPI DPHY
   : remove obsolete MIPI DPHY reg property
   : enable s3c-rtc on exynos4412-trats2
 
 - for exynos5
   : add syscon property to MIPI DPHY for exynos5420
   : enable s3c-rtc on exynos5420-arndale-octa
   : add missing irq pinctrl for max77686 on exynos5250-smdk5250
 
   : clk: add bindings for 32kHz clocks from s2mps11
   : fix pinctrl for s2mps11-irq on exynos5420-arndale-octa
 
 - for exynos5422-odroidxu3
   : add mmc detect gpio and LEDs
   : add HS400 support, simple-audio-card and rtc_src clock
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Merge tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt

Samsung DT updates for v4.2

- for exyos3250
  : use s3c6410-rtc instead of exynos3250-rtc
  : add JPEG codec node and support it on exynos3250-rinato
  : use s3c-rtc clock id for exynos3250-rinato and monk boards

- for exynos4
  : add JPEG codec node and syscon property to MIPI DPHY
  : remove obsolete MIPI DPHY reg property
  : enable s3c-rtc on exynos4412-trats2

- for exynos5
  : add syscon property to MIPI DPHY for exynos5420
  : enable s3c-rtc on exynos5420-arndale-octa
  : add missing irq pinctrl for max77686 on exynos5250-smdk5250

  : clk: add bindings for 32kHz clocks from s2mps11
  : fix pinctrl for s2mps11-irq on exynos5420-arndale-octa

- for exynos5422-odroidxu3
  : add mmc detect gpio and LEDs
  : add HS400 support, simple-audio-card and rtc_src clock

* tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: Add syscon property to the MIPI DPHY for exynos4415
  ARM: dts: Remove obsolete MIPI DPHY 'reg' property for exynos4
  ARM: dts: Use last parent for clocks during power domain on/off
  ARM: dts: add support JPEG codec for exynos3250-rinato
  ARM: dts: support simple-audio-card for exynos5420 and exynos5422-odroidxu3
  ARM: dts: add jpeg-codec node for exynos4 and exynos4x12
  ARM: dts: Enable S3C RTC on exynos4412-trats2 and exynos5420-arndale-octa
  ARM: dts: Use define for s3c-rtc clock id for exynos3250-monk
  ARM: dts: Use define for s3c-rtc clock id for exynos3250-rinato
  ARM: dts: Use s3c6410-rtc instead of exynos3250-rtc for exynos3250/4415
  ARM: dts: add 'rtc_src' clock to rtc node for exynos5422-odroidxu3
  clk: samsung: Add bindings for 32kHz clocks from s2mps11
  ARM: dts: fix pinctrl for s2mps11-irq on exynos5420-arndale-octa
  ARM: dts: Add syscon property to the MIPI phy in exynos5420
  ARM: dts: Add HS400 support for exynos5422-odroidxu3
  ARM: dts: Add LEDs for exynos5422-odroidxu3
  ARM: dts: add mmc detect gpio for exynos5422-odroidxu3
  ARM: dts: add JPEG codec device node for exynos3250
  ARM: dts: Add missing irq pinctrl for max77686 on smdk5250
2015-06-11 14:31:55 -07:00
Krzysztof Kozlowski 662cfed8a1 ARM: multi_v7_defconfig: Enable display on Trats2 board
Enable the Exynos DSI and S6E8AA0 panel for full X11 display on Trats2.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11 14:29:34 -07:00
Kevin Hilman c182048058 exynos_defconfig updates for v4.2
- enable DRM_EXYNOS_DSI and DRM_PANEL_S6E8AA0
   for full X11 display on Trats2 board
 - enable SENSORS_PWM_FAN
   to control fan power on Odroid-XU3 board
 - enable SENSORS_INA2XX
   for power monitor sensor on Odriod-XU3 board
 - do savedefconfig
   to remove useless configs and check its dependencies
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Merge tag 'samsung-defconfig-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/defconfig

exynos_defconfig updates for v4.2

- enable DRM_EXYNOS_DSI and DRM_PANEL_S6E8AA0
  for full X11 display on Trats2 board
- enable SENSORS_PWM_FAN
  to control fan power on Odroid-XU3 board
- enable SENSORS_INA2XX
  for power monitor sensor on Odriod-XU3 board
- do savedefconfig
  to remove useless configs and check its dependencies

* tag 'samsung-defconfig-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: exynos_defconfig: Enable CONFIG_SENSORS_INA2XX for Odroid-XU3
  ARM: exynos_defconfig: Enable CONFIG_SENSORS_PWM_FAN for Odroid-XU3
  ARM: exynos_defconfig: savedefconfig
  ARM: exynos_defconfig: Enable display on Trats2 board
2015-06-11 14:24:47 -07:00
Mika Westerberg d50bfa4763 ARM: ep93xx: simone: support for SPI-based MMC/SD cards
This includes setting up EGPIOs 0 and 9 for card detection and
chip select respectively. This patch is needed to mount a root
filesystem on the SPI-based MMC card reader found on the Sim.One.

Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11 14:21:29 -07:00
Linus Walleij 386f56bb73 ARM: nomadik: set proper compatible for accelerometer
Adjust device tree entry to the proper registered compatible
string for LIS3LV02DL.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11 14:20:25 -07:00