Commit Graph

40 Commits

Author SHA1 Message Date
Liu Ying 9a8406ba1a phy: dphy: Correct clk_pre parameter
The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
parameter's unit is Unit Interval(UI) and the minimum value is 8.  Also,
kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy
mentions that it should be in UI.  However, the dphy core driver wrongly
sets 'clk_pre' to 8000, which seems to hint that it's in picoseconds.

So, let's fix the dphy core driver to correctly reflect the T-CLK-PRE
parameter's minimum value according to the D-PHY specification.

I'm assuming that all impacted custom drivers shall program values in
TxByteClkHS cycles into hardware for the T-CLK-PRE parameter.  The D-PHY
specification mentions that the frequency of TxByteClkHS is exactly 1/8
the High-Speed(HS) bit rate(each HS bit consumes one UI).  So, relevant
custom driver code is changed to program those values as
DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE), then.

Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK.
Help is needed to test with other i.MX8mq, Meson and Rockchip platforms,
as I don't have the hardwares.

Fixes: 2ed869990e ("phy: Add MIPI D-PHY configuration options")
Tested-by: Liu Ying <victor.liu@nxp.com> # RM67191 DSI panel on i.MX8mq EVK
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> # for phy-meson-axg-mipi-dphy.c
Tested-by: Neil Armstrong <narmstrong@baylibre.com> # for phy-meson-axg-mipi-dphy.c
Tested-by: Guido Günther <agx@sigxcpu.org> # Librem 5 (imx8mq) with it's rather picky panel
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Link: https://lore.kernel.org/r/20220124024007.1465018-1-victor.liu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-02 10:33:04 +05:30
Martin Blumenstingl e45dbd3a4b phy: amlogic: Add a new driver for the HDMI TX PHY on Meson8/8b/8m2
Amlogic Meson8/8b/8m2 have a built-in HDMI PHY in the HHI register
region. Unfortunately only few register bits are documented. For
HHI_HDMI_PHY_CNTL0 the magic numbers are taken from the 3.10 vendor
kernel.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20211020195107.1564533-3-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-11-23 11:17:49 +05:30
Anand Moon c7c4024348 phy: amlogic: meson8b-usb2: don't log an error on -EPROBE_DEFER
devm_phy_create can return -EPROBE_DEFER if the vbus-supply is not ready
yet. Silence this warning as the driver framework will re-attempt
registering the PHY. Use dev_err_probe() for phy resources to indicate
the deferral reason when waiting for the resource to come up.

Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20210817041548.1276-7-linux.amoon@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 16:00:44 +05:30
Anand Moon e1f31c93a8 phy: amlogic: meson8b-usb2: Power off the PHY by putting it into reset mode
Power off the PHY by putting it into reset mode.

Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20210817041548.1276-6-linux.amoon@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 16:00:44 +05:30
Yejune Deng 15ee627781 phy: amlogic: replace devm_reset_control_array_get()
devm_reset_control_array_get_exclusive() looks more readable

Signed-off-by: Yejune Deng <yejune.deng@gmail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/1605666995-16462-1-git-send-email-yejune.deng@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30 16:32:37 +05:30
Neil Armstrong 122586d622 phy: amlogic: phy-meson-gxl-usb2: keep ID pull-up even in Host mode
In order to keep OTG ID detection even when in Host mode, the ID line of
the PHY (if the current phy is an OTG one) pull-up should be kept
enable in both modes.

This fixes OTG switch on GXL, GXM & AXG platforms, otherwise once switched
to Host, the ID detection doesn't work anymore to switch back to Device.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20201120153855.3920757-1-narmstrong@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30 16:31:03 +05:30
Neil Armstrong 4eed2812de phy: amlogic: meson-axg-mipi-pcie-analog: replace DSI_LANE definitions with BIT() macro
For consistency, replace DSI_LANE definitions with BIT() macro and remove the unused
DSI_LANE_MASK definition.

Suggested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20201120150347.3914901-1-narmstrong@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30 16:30:24 +05:30
Neil Armstrong 8eff8b4e22 phy: amlogic: phy-meson-axg-mipi-pcie-analog: add support for MIPI DSI analog
The AXG Analog MIPI-DSI PHY also provides functions to the PCIe PHY,
thus we need to have inclusive support for both interfaces at runtime.

This fixes the regmap get from parent node, removes cell param
to select a mode and implement runtime configuration & power on/off
for both functions since they are not exclusive.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Remi Pommarel <repk@triplefau.lt>
Link: https://lore.kernel.org/r/20201116101647.73448-4-narmstrong@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20 15:23:33 +05:30
Neil Armstrong 76aefb2211 phy: amlogic: Add AXG MIPI D-PHY driver
The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI
panels.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20201116101315.71720-3-narmstrong@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20 15:23:33 +05:30
Vinod Koul 53cde0fe02 phy: amlogic: Revert "phy: amlogic: Replace devm_reset_control_array_get()"
This reverts commit 3cc8e86721 ("phy: amlogic: Replace
devm_reset_control_array_get()") as it caused build failure

drivers/soc/amlogic/meson-ee-pwrc.c: In function 'meson_ee_pwrc_init_domain':
drivers/soc/amlogic/meson-ee-pwrc.c:416:65: error: expected ';' before 'if'

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-17 15:29:42 +05:30
Yejune Deng 3cc8e86721 phy: amlogic: Replace devm_reset_control_array_get()
devm_reset_control_array_get_exclusive() looks more readable

Signed-off-by: Yejune Deng <yejune.deng@gmail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/1604378274-6860-1-git-send-email-yejune.deng@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 13:04:47 +05:30
Chunfeng Yun 202de02556 phy: amlogic: convert to devm_platform_ioremap_resource
Use devm_platform_ioremap_resource to simplify code

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Remi Pommarel <repk@triplefau.lt>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/1604642930-29019-2-git-send-email-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 12:47:46 +05:30
Greg Kroah-Hartman ca681aa492 USB: changes for v5.8 merge window
Rather busy cycle. We have a total 99 non-merge commits going into v5.8
 merge window. The majority of the changes are in dwc3 this around (31.7%
 of all changes). It's composed mostly Thinh's recent updates to get dwc3
 to behave correctly with stream transfers. We have also have Roger's for
 Keystone platforms and Neil's updates for the meson glue layer.
 
 Apart from those, we have the usual set of non-critical fixes, new
 device IDs, spelling fixes all over the place.
 
 Signed-off-by: Felipe Balbi <balbi@kernel.org>
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEElLzh7wn96CXwjh2IzL64meEamQYFAl7LktsRHGJhbGJpQGtl
 cm5lbC5vcmcACgkQzL64meEamQZjHRAA1lTH1Uv8wMoLpsefXYvc5w98kUu1CQGA
 a23m14xNCv66pzgWTDKIk0zQpPiIpoWgvuwohVnDV0ygyCmEyg4Qp5Y6HQcFbDsY
 JEQDK41TT9GIEza6b/rhBSzR90MXlXxAMnFRKnxlLgMw1na8Y6Jmn3c0MtQNCfZo
 3roOhWnSittEbczNRzMVdZXV/CI8/CL6ykmnsjUipYrtQJHtdzx+M/BWxj/inoUP
 Hl9hr6jH6zxQS+8UyoHSzNKtfWYvPMFUrwKNscsdAqjfpQyWV4uGoSFqGc+lGhXx
 wrWdR+8WGchWNgJPlykAeaHVf4yyV/bOeQjpngC3HU2FQxc5Ohn3UVtfG7SOeMxD
 ZNKZukZzRhZzXX8ha28nYu3r6++heKWS+rspOHwKR56HVhpQlSwvNwoqzTkPxxB5
 p9ODyIfirsn2+Maj4weCpNARNxlc31rAybaQ8+uxAg8q6XcSD4lB5U929ajxpHQK
 UErgDkIbjGpYY13Lrm7GjBuagiYyyvMKp3+6lR50tKlLYQSFB5EjTaYW15az2Yc+
 xwTqSusxhP9MNMp3brU9ZJwzIA4s1gyjelbLsTYs/D3pgYA2YiYnajbwqmHJDINu
 Nh+C6xyKiTC9OJspQv6+mHjMzc0VjBhr1KMPdRAdwLw1dHENyEhf6DrfHt/FjGxC
 3fS6/uQ5jao=
 =OiS0
 -----END PGP SIGNATURE-----

Merge tag 'usb-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next

Felipe writes:

USB: changes for v5.8 merge window

Rather busy cycle. We have a total 99 non-merge commits going into v5.8
merge window. The majority of the changes are in dwc3 this around (31.7%
of all changes). It's composed mostly Thinh's recent updates to get dwc3
to behave correctly with stream transfers. We have also have Roger's for
Keystone platforms and Neil's updates for the meson glue layer.

Apart from those, we have the usual set of non-critical fixes, new
device IDs, spelling fixes all over the place.

Signed-off-by: Felipe Balbi <balbi@kernel.org>

* tag 'usb-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb: (99 commits)
  usb: dwc3: keystone: Turn on USB3 PHY before controller
  dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property
  dt-bindings: usb: convert keystone-usb.txt to YAML
  usb: dwc3: gadget: Check for prepared TRBs
  usb: gadget: Fix issue with config_ep_by_speed function
  usb: cdns3: ep0: delete the redundant status stage
  usb: dwc2: Update Core Reset programming flow.
  usb: gadget: fsl: Fix a wrong judgment in fsl_udc_probe()
  usb: gadget: fix potential double-free in m66592_probe.
  usb: cdns3: Fix runtime PM imbalance on error
  usb: gadget: lpc32xx_udc: don't dereference ep pointer before null check
  usb: dwc3: Increase timeout for CmdAct cleared by device controller
  USB: dummy-hcd: use configurable endpoint naming scheme
  usb: cdns3: gadget: assign interrupt number to USB gadget structure
  usb: gadget: core: sync interrupt before unbind the udc
  arm64: dts: qcom: sc7180: Add interconnect properties for USB
  arm64: dts: qcom: sdm845: Add interconnect properties for USB
  dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver
  ARM: dts: at91: Remove the USB EP child node
  dt-bindings: usb: atmel: Mark EP child node as deprecated
  ...
2020-05-25 13:28:20 +02:00
Martin Blumenstingl 40f6706862 phy: amlogic: meson-gxl-usb3: remove code for non-existing PHY
The registers which are managed by the meson-gxl-usb3 PHY driver are
actually "USB control" registers (which are "glue" registers which
manage OTG detection and routing of the OTG capable port between the
DWC2 peripheral-only controller and the DWC3 host-only controller).

Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-g12a-usb
driver supports the USB control registers on GXL and GXM SoCs (these
were previously managed by the meson-gxl-usb3 PHY driver).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
2020-05-25 11:09:38 +03:00
Martin Blumenstingl f004be596c phy: amlogic: meson8b-usb2: Add a compatible string for Meson8m2
The 3.10 vendor kernel sets the ACA_ENABLE bit on Meson8b, Meson8m2 and
GXBB, but not on Meson8. Add a compatible string for Meson8m2 which also
sets that bit.
While here, also update the Kconfig text and MODULE_DESCRIPTION.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-7-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Martin Blumenstingl 7cafc01744 phy: amlogic: meson8b-usb2: unset the IDDQ bit during PHY power-on
The vendor driver unsets the set_iddig bit during power-on as well and
sets it when suspending the PHY. I did not notice this in the vendor
driver first, because it's part of the dwc_otg driver there (instead of
their PHY code). While here, also add all other REG_DBG_UART register
bit definitions.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-6-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Martin Blumenstingl 6b99262fd2 phy: amlogic: meson8b-usb2: Don't set REG_ADP_BC_ACA_ENABLE on Meson8
Skip setting REG_ADP_BC_ACA_ENABLE on Meson8 SoCs and polling for the
REG_ADP_BC_ACA_PIN_FLOAT bit. The vendor also skips this part on Meson8
SoCs.
This fixes initialization of the host-only USB PHY on Meson8 which would
otherwise fail with "USB ID detect failed!".

Fixes: 4a3449d1a0 ("phy: meson8b-usb2: add support for the USB PHY on Meson8 SoCs")
Reported-by: Thomas Graichen <thomas.graichen@gmail.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-5-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Martin Blumenstingl de143a40fa phy: amlogic: meson8b-usb2: Use a MMIO regmap
Using a MMIO regmap and switch to regmap_update_bits() to simplify the
code in the driver. Also switch to devm_platform_ioremap_resource()
instead of open-coding it. No functional changes intended.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-4-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Linus Torvalds 86f26a77cb pci-v5.7-changes
-----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAl6GTQMUHGJoZWxnYWFz
 QGdvb2dsZS5jb20ACgkQWYigwDrT+vy3PhAAmqpYBRobOsG8QbmKDjoJEFtkqdvD
 z6+4zf/R+hF11RyXjMDwihIe8d+tkQ4eAaYu6Oh5PrTyanz0G0PgeCrivZeytULk
 thqQIWzDQMVA5vN/2/Vy8s5s+3HzP8z/MZOFScJ7+xA1MndXptPRTNmFUbjx+GAv
 x8/pTp0u9AF6m7itX65DxXvwkzjWamt+Ar4Yx2IcuKAU/M5RtfuZO3PpDnqn7/wk
 JFlkRoYeFB6qNnnkPdeyPHl9dALhuhzgdTyklQEnKVW3nf3xThYDhcEwdh6kBQgl
 0dH8lL5LXy7PKGN8RES4wB0Vqndw/HlsCF5O4wkkfItbnbJxGJtS139e5973m0ud
 sgWvF4yJAT2jCKhIeNz34sePQJMyWALhv0XzZCsJ0YeGHsrV1jrHELkwUT1+eIsT
 3UV0iZ6aL06zQJDyKUbbIcQzEQ/wwBC+x9VgsyL54K1quCQZ1N1Nl/dvrb4cRG9m
 m9EhJK/brDf4c0uFlOmMTSxV1t5J+z6ZSQnh1ShD/o5yBsxqN6q5brDT6LEs+jbM
 LsIkA18jJOd4OyiDs98YiFKvIfFQbQ0LEBQpJwhF0snvfBFMMbUYN/T/NYneWON/
 F0TpkFoP7PXDuq55iNaLdnObfzrpC9kdzUyWvePUvjxIl55bkf+/qtUny+H48t4L
 dNggvW052d7BHes=
 =deWu
 -----END PGP SIGNATURE-----

Merge tag 'pci-v5.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull pci updates from Bjorn Helgaas:
 "Enumeration:

   - Revert sysfs "rescan" renames that broke apps (Kelsey Skunberg)

   - Add more 32 GT/s link speed decoding and improve the implementation
     (Yicong Yang)

  Resource management:

   - Add support for sizing programmable host bridge apertures and fix a
     related alpha Nautilus regression (Ivan Kokshaysky)

  Interrupts:

   - Add boot interrupt quirk mechanism for Xeon chipsets and document
     boot interrupts (Sean V Kelley)

  PCIe native device hotplug:

   - When possible, disable in-band presence detect and use PDS
     (Alexandru Gagniuc)

   - Add DMI table for devices that don't use in-band presence detection
     but don't advertise that correctly (Stuart Hayes)

   - Fix hang when powering slots up/down via sysfs (Lukas Wunner)

   - Fix an MSI interrupt race (Stuart Hayes)

  Virtualization:

   - Add ACS quirks for Zhaoxin devices (Raymond Pang)

  Error handling:

   - Add Error Disconnect Recover (EDR) support so firmware can report
     devices disconnected via DPC and we can try to recover (Kuppuswamy
     Sathyanarayanan)

  Peer-to-peer DMA:

   - Add Intel Sky Lake-E Root Ports B, C, D to the whitelist (Andrew
     Maier)

  ASPM:

   - Reduce severity of common clock config message (Chris Packham)

   - Clear the correct bits when enabling L1 substates, so we don't go
     to the wrong state (Yicong Yang)

  Endpoint framework:

   - Replace EPF linkup ops with notifier call chain and improve locking
     (Kishon Vijay Abraham I)

   - Fix concurrent memory allocation in OB address region (Kishon Vijay
     Abraham I)

   - Move PF function number assignment to EPC core to support multiple
     function creation methods (Kishon Vijay Abraham I)

   - Fix issue with clearing configfs "start" entry (Kunihiko Hayashi)

   - Fix issue with endpoint MSI-X ignoring BAR Indicator and Table
     Offset (Kishon Vijay Abraham I)

   - Add support for testing DMA transfers (Kishon Vijay Abraham I)

   - Add support for testing > 10 endpoint devices (Kishon Vijay Abraham I)

   - Add support for tests to clear IRQ (Kishon Vijay Abraham I)

   - Add common DT schema for endpoint controllers (Kishon Vijay Abraham I)

  Amlogic Meson PCIe controller driver:

   - Add DT bindings for AXG PCIe PHY, shared MIPI/PCIe analog PHY (Remi
     Pommarel)

   - Add Amlogic AXG PCIe PHY, AXG MIPI/PCIe analog PHY drivers (Remi
     Pommarel)

  Cadence PCIe controller driver:

   - Add Root Complex/Endpoint DT schema for Cadence PCIe (Kishon Vijay
     Abraham I)

  Intel VMD host bridge driver:

   - Add two VMD Device IDs that require bus restriction mode (Sushma
     Kalakota)

  Mobiveil PCIe controller driver:

   - Refactor and modularize mobiveil driver (Hou Zhiqiang)

   - Add support for Mobiveil GPEX Gen4 host (Hou Zhiqiang)

  Microsoft Hyper-V host bridge driver:

   - Add support for Hyper-V PCI protocol version 1.3 and
     PCI_BUS_RELATIONS2 (Long Li)

   - Refactor to prepare for virtual PCI on non-x86 architectures (Boqun
     Feng)

   - Fix memory leak in hv_pci_probe()'s error path (Dexuan Cui)

  NVIDIA Tegra PCIe controller driver:

   - Use pci_parse_request_of_pci_ranges() (Rob Herring)

   - Add support for endpoint mode and related DT updates (Vidya Sagar)

   - Reduce -EPROBE_DEFER error message log level (Thierry Reding)

  Qualcomm PCIe controller driver:

   - Restrict class fixup to specific Qualcomm devices (Bjorn Andersson)

  Synopsys DesignWare PCIe controller driver:

   - Refactor core initialization code for endpoint mode (Vidya Sagar)

   - Fix endpoint MSI-X to use correct table address (Kishon Vijay
     Abraham I)

  TI DRA7xx PCIe controller driver:

   - Fix MSI IRQ handling (Vignesh Raghavendra)

  TI Keystone PCIe controller driver:

   - Allow AM654 endpoint to raise MSI-X interrupt (Kishon Vijay Abraham I)

  Miscellaneous:

   - Quirk ASMedia XHCI USB to avoid "PME# from D0" defect (Kai-Heng
     Feng)

   - Use ioremap(), not phys_to_virt(), for platform ROM to fix video
     ROM mapping with CONFIG_HIGHMEM (Mikel Rychliski)"

* tag 'pci-v5.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (96 commits)
  misc: pci_endpoint_test: remove duplicate macro PCI_ENDPOINT_TEST_STATUS
  PCI: tegra: Print -EPROBE_DEFER error message at debug level
  misc: pci_endpoint_test: Use full pci-endpoint-test name in request_irq()
  misc: pci_endpoint_test: Fix to support > 10 pci-endpoint-test devices
  tools: PCI: Add 'e' to clear IRQ
  misc: pci_endpoint_test: Add ioctl to clear IRQ
  misc: pci_endpoint_test: Avoid using module parameter to determine irqtype
  PCI: keystone: Allow AM654 PCIe Endpoint to raise MSI-X interrupt
  PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address
  PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
  misc: pci_endpoint_test: Add support to get DMA option from userspace
  tools: PCI: Add 'd' command line option to support DMA
  misc: pci_endpoint_test: Use streaming DMA APIs for buffer allocation
  PCI: endpoint: functions/pci-epf-test: Print throughput information
  PCI: endpoint: functions/pci-epf-test: Add DMA support to transfer data
  PCI: pciehp: Fix MSI interrupt race
  PCI: pciehp: Fix indefinite wait on sysfs requests
  PCI: endpoint: Fix clearing start entry in configfs
  PCI: tegra: Add support for PCIe endpoint mode in Tegra194
  PCI: sysfs: Revert "rescan" file renames
  ...
2020-04-03 14:25:02 -07:00
Hanjie Lin 23bcbb4164 phy: amlogic: Add Amlogic A1 USB2 PHY Driver
This adds support for the USB2 PHY found in the Amlogic A1 SoC Family.

It supports host mode only.

Signed-off-by: Yue Wang <yue.wang@amlogic.com>
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20 19:34:29 +05:30
Joe Perches 014b35d932 phy: amlogic: G12A: Fix misuse of GENMASK macro
Arguments are supposed to be ordered high then low.

Signed-off-by: Joe Perches <joe@perches.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20 19:34:29 +05:30
Remi Pommarel e2463559ff phy: amlogic: Add Amlogic AXG PCIE PHY Driver
This adds support for the PCI PHY found in the Amlogic AXG SoC Family.
This will allow to mutualize code in pci-meson.c between AXG and G12A
SoC.

This PHY also uses and chains an analog PHY, which on AXG platform
is needed to have reliable PCIe communication.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2020-03-04 10:53:30 +00:00
Remi Pommarel af3f5722d1 phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver
This adds support for the MIPI analog PHY which is also used for PCIE
found in the Amlogic AXG SoC Family.

MIPI or PCIE selection is done by the #phy-cells, making the mode
static and exclusive.

For now only PCIE functionality is supported.

This PHY will be used to replace the mipi_enable clock gating logic
which was mistakenly added in the clock subsystem. This also activates
a non documented band gap bit in those registers that allows reliable
PCIE clock signal generation on AXG platforms.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
2020-03-04 10:53:30 +00:00
Neil Armstrong 631627253d phy: meson-g12a-usb3-pcie: Add support for PCIe mode
This adds extended PCIe PHY functions for the Amlogic G12A
USB3+PCIE Combo PHY to support reset, power_on and power_off for
PCIe exclusively.

With these callbacks, we can handle all the needed operations of the
Amlogic PCIe controller driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2019-10-15 14:57:32 +01:00
Greg Kroah-Hartman aa9083faa1 phy: for 5.3
*) Add a new PHY driver for Qualcomm PCIe2 PHY
   *) Add a new PHY driver for Mixel DPHY present in i.MX8
   *) Fix Qualcomm QMP UFS PHY driver from incorrectly reporting that
      PHY enable failed
   *) Fix _BUG_ on Amlogic G12A USB3 + PCIE Combo PHY Driver due to
      calling a sleeping function from invalid context
   *) Fix WARN_ON dump on rcar-gen3-usb2 PHY driver caused due to
      imbalance powered flag
   *) Fix .cocci and sparse warnings
 
 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
 -----BEGIN PGP SIGNATURE-----
 
 iQJCBAABCgAsFiEEUXMr/TfP2p4suIY5Dlx4XIBNgtkFAl0Z3rAOHGtpc2hvbkB0
 aS5jb20ACgkQDlx4XIBNgtlvxBAAppuQXXioXA4+HSwhTTTGOfGwR4C9J+fLpfzH
 7uzFCTIG/nJnGWDyI5c093XXvvnPggh2zkRRAoy2iGDUmOtFJX3olOmDnmsyYtPW
 gMOArOCaIuTu9kDUmkes9N19QvkC11y4rQKvtbR+HhpQa96ucOaeDDMuedWlnqmB
 EeDN8tzhPSDdkkkuHnrJCfL4Mp6ZNFdTxZcEaU2vnx9pra3xq0Q7b90mm3Iyzy6E
 cTuQqWr9sClFMmL1cCZwfQlRHTFIeh2+/kBzycOnLUCsF6gQ7IVVYNyIu44qlmCM
 B0dtlvkB/z4qPj6kTh/2P6cMxf3sd8ZmW/cCXTPacpHio4gO9shRXp+yFamMC05i
 +yoL3pCQyp0t+1NjNal1N7jVEHmB+MwBhlQNiqwCYxEtBeTNMh/wVPr7cXHfO19a
 DrSUkrB0n5nYhv1adWCNEmzx4/ZA48j7hDLIVY/PFDddn1czz+5Lw6X+XR46o1tt
 qe6PodUa5nRPKoVXVnfA/0jHrjU9x4fE4OSxpBo7MbbQxWoU8LwibDuWMdWaooc9
 JlJBaTDPv4yXQg1EvHLvRvp/7S/dNRTKZgcY6E0YDYWH8ki+v3gRm5wP8eVlbGG5
 WKpChsxj6d53TdFnGs0Ngi3FOdqBHE8RXWXd0mCoDTh5SLgoF6eWmGwBr02rdX7x
 uNJTVGo=
 =5mPE
 -----END PGP SIGNATURE-----

Merge tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next

phy: for 5.3

  *) Add a new PHY driver for Qualcomm PCIe2 PHY
  *) Add a new PHY driver for Mixel DPHY present in i.MX8
  *) Fix Qualcomm QMP UFS PHY driver from incorrectly reporting that
     PHY enable failed
  *) Fix _BUG_ on Amlogic G12A USB3 + PCIE Combo PHY Driver due to
     calling a sleeping function from invalid context
  *) Fix WARN_ON dump on rcar-gen3-usb2 PHY driver caused due to
     imbalance powered flag
  *) Fix .cocci and sparse warnings

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy:
  phy: qcom-qmp: Raise qcom_qmp_phy_enable() polling delay
  phy: meson-g12a-usb3-pcie: disable locking for cr_regmap
  phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs
  dt-bindings: phy: Add documentation for mixel dphy
  dt-bindings: phy-pxa-usb: add bindings
  phy: renesas: rcar-gen3-usb2: fix imbalance powered flag
  phy: qcom-qmp: Drop useless msm8998_pciephy_cfg setting
  phy: qcom-qmp: Correct READY_STATUS poll break condition
  phy: ti: am654-serdes: Make serdes_am654_xlate() static
  phy: usb: phy-brcm-usb: Fix platform_no_drv_owner.cocci warnings
  phy: samsung: Use struct_size() in devm_kzalloc()
  phy: qcom: Add Qualcomm PCIe2 PHY driver
  dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY
2019-07-01 15:04:59 +02:00
Neil Armstrong 5fc2aa3ec9 phy: meson-g12a-usb3-pcie: disable locking for cr_regmap
Locking is not needed for the phy_g12a_usb3_pcie_cr_bus_read/write() and
currently it causes the following BUG because of the usage of the
regmap_read_poll_timeout() running in spinlock_irq, configured by regmap fast_io.

Simply disable locking in the cr_regmap config since it's only used from the
PHY init callback function.

BUG: sleeping function called from invalid context at drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c:85
in_atomic(): 1, irqs_disabled(): 128, pid: 60, name: kworker/3:1
[snip]
Workqueue: events deferred_probe_work_func
Call trace:
 dump_backtrace+0x0/0x190
 show_stack+0x14/0x20
 dump_stack+0x90/0xb4
 ___might_sleep+0xec/0x110
 __might_sleep+0x50/0x88
 phy_g12a_usb3_pcie_cr_bus_addr.isra.0+0x80/0x1a8
 phy_g12a_usb3_pcie_cr_bus_read+0x34/0x1d8
 _regmap_read+0x60/0xe0
 _regmap_update_bits+0xc4/0x110
 regmap_update_bits_base+0x60/0x90
 phy_g12a_usb3_pcie_init+0xdc/0x210
 phy_init+0x74/0xd0
 dwc3_meson_g12a_probe+0x2cc/0x4d0
 platform_drv_probe+0x50/0xa0
 really_probe+0x20c/0x3b8
 driver_probe_device+0x68/0x150
 __device_attach_driver+0xa8/0x170
 bus_for_each_drv+0x64/0xc8
 __device_attach+0xd8/0x158
 device_initial_probe+0x10/0x18
 bus_probe_device+0x90/0x98
 deferred_probe_work_func+0x94/0xe8
 process_one_work+0x1e0/0x338
 worker_thread+0x230/0x458
 kthread+0x134/0x138
 ret_from_fork+0x10/0x1c

Fixes: 36077e16c0 ("phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-25 19:17:36 +05:30
Thomas Gleixner 3c910ecbdd treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation you should have received a
  copy of the gnu general public license along with this program if
  not see http www gnu org licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 30 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.962665879@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:37:18 +02:00
Thomas Gleixner ec8f24b7fa treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 10:50:46 +02:00
Chunfeng Yun 42c7cb71b5 phy: phy-meson-gxl-usb2: get optional clock by devm_clk_get_optional()
Use devm_clk_get_optional() to get optional clock

Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17 14:13:16 +05:30
Neil Armstrong 36077e16c0 phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver
This adds support for the shared USB3 + PCIE PHY found in the
Amlogic G12A SoC Family.

It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of
the board.

Selection is done by the #phy-cells, making the mode static and exclusive.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17 14:12:51 +05:30
Neil Armstrong 16df8bcb67 phy: amlogic: add Amlogic G12A USB2 PHY Driver
This adds support for the USB2 PHY found in the Amlogic G12A SoC Family.

It supports Host and/or Peripheral mode, depending on it's position.
The first PHY is only used as Host, but the second supports Dual modes
defined by the USB Control Glue HW in front of the USB Controllers.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17 14:12:50 +05:30
Grygorii Strashko 79a5a18aa9 phy: core: rework phy_set_mode to accept phy mode and submode
Currently the attempt to add support for Ethernet interface mode PHY
(MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and
duplicate there values from phy_interface_t enum (or introduce more PHY
callbacks) [1]. Both approaches are ineffective and would lead to fast
bloating of enum phy_mode or struct phy_ops in the process of adding more
PHYs for different subsystems which will make them unmaintainable.

As discussed in [1] the solution could be to introduce dual level PHYs mode
configuration - PHY mode and PHY submode. The PHY mode will define generic
PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem
specific interface mode. The last is usually already defined in
corresponding subsystem headers (phy_interface_t for Ethernet, enum
usb_device_speed for USB).

This patch is cumulative change which refactors PHY framework code to
support dual level PHYs mode configuration - PHY mode and PHY submode. It
extends .set_mode() callback to support additional parameter "int submode"
and converts all corresponding PHY drivers to support new .set_mode()
callback declaration.
The new extended PHY API
 int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
is introduced to support dual level PHYs mode configuration and existing
phy_set_mode() API is converted to macros, so PHY framework consumers do
not need to be changed (~21 matches).

[1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12 10:01:33 +05:30
Martin Blumenstingl 115de9fd68 phy: amlogic: add USB3 PHY support for Meson GXL and GXM
This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs
(both SoCs are using the same USB PHY register layout).

Unfortunately there is no documentation for this PHY in the public S905X
datasheet (published for example by Khadas). What we know so far about
this PHY:
- even though the Meson GXL and GXM SoCs do not expose an USB3 port (the
  dwc3 controller only has USB2 ports enabled) we need to initialize the
  USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this
  initialization high-speed USB devices (especially USB hard disks and
  thumb drives, slower devices like mice do not seem to be affected)
- on some boards the USB3 PHY starts in "device mode" - we want to bring
  it into a known state (by switching it to host mode for now).
- it is responsible for the OTG detection and for switching the first
  USB2 PHY between host and peripheral (aka device) mode. an interrupt
  can be used to detect changes between host and device mode.

There are five inputs to this register area:
- the clock and reset line for the USB3 PHY itself
- the clock and reset line for the peripheral mode and OTG detection
  logic (on the GXL and GXM SoCs these are the same clock and reset line
  as for the USB3 PHY itself, but Amlogic sees this as two different
  components - even though they share the same register space - so they
  have to be passed individually to allow specifying different inputs on
  other SoCs if needed)
- the interrupt for the OTG detection logic

The whole OTG detection logic is not implemented yet.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Yixun Lan <yixun.lan@amlogic.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-16 13:40:44 +05:30
Martin Blumenstingl ae91a799fb phy: amlogic: phy-meson-gxl-usb2: rename some of the U2P_R2 registers
The U2P_R2 register provides "test mode" functionality for bits 17:0.
These are only used during SoC development and should be left untouched
on production SoC versions.
Rename these register definitions to indicate that these are for "test
mode" only.

While here, also merge the definitions for U2P_R2_DATA_IN_MASK and
U2P_R2_DATA_IN_EN_MASK (bits 0:7) because Amlogic's internal
documentation suggests that these bits belong together. The old
definition was not taken from the documentation but rather from a struct
definition in the Amlogic GPL kernel sources.

No functional changes.

Suggested-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08 13:56:29 +05:30
Martin Blumenstingl 05818862bc phy: amlogic: phy-meson-gxl-usb2: default to host mode
The USB2 PHY can switch between PHY_MODE_USB_HOST and
PHY_MODE_USB_DEVICE. However, it cannot do it on it's own since it
requires re-routing of the corresponding USB pins from dwc3 (which is
used for host-mode) to dwc2 (which is used for device-mode).
Thus we don't need to auto-detect the mode based on the USB controller,
which simplifies the driver code.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08 13:56:28 +05:30
Martin Blumenstingl bc4a0241d4 phy: amlogic: phy-meson-gxl-usb2: support the clock and reset line
The Meson GXL USB2 PHYs require an additional clock (USB) which has to
be enabled. If that clock is disabled then all PHY registers read 0x0.
Luckily for us that clock is always enabled (either by harddware
defaults, the bootrom, or any of the bootloaders before u-boot/BL3-3).

The OTG capable USB2 PHY additionally has a reset line (USB_OTG, which
is shared with other components, such as the USB3 PHY for example).

Extend the driver so it handles this clock and the shared reset line.
We only trigger the reset during the .init phase since it's a shared
reset line, so triggering it during the driver's .reset implementation
would effectively also only trigger it once anyways.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08 13:56:27 +05:30
Martin Blumenstingl cba1372812 phy: amlogic: phy-meson-gxl-usb2: don't log an error on -EPROBE_DEFER
devm_phy_create can return -EPROBE_DEFER if the phy-supply is not ready
yet. Silence this warning as the driver framework will re-attempt
registering the PHY - this second try works without any errors. So only
log actual errors to keep the kernel log free of misleading error
messages.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08 13:56:26 +05:30
Martin Blumenstingl 4a3449d1a0 phy: meson8b-usb2: add support for the USB PHY on Meson8 SoCs
Meson8 uses the same USB PHY as found on the Meson8b and GXBB SoCs. Add
a new of_device_id to indicate this. Also update the Kconfig option and
MODULE_DESCRIPTION accordingly.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06 14:50:14 +05:30
Martin Blumenstingl 697b373c6d phy: meson: add USB2 PHY support for Meson GXL and GXM
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs
(both SoCs are using the same USB PHY register layout).

The USB2 PHY is a simple PHY which only has a few registers to configure
the mode (host/device) and a reset register (to enable/disable the PHY).

Unfortunately there are no datasheets available for this PHY. The driver
was written by reading the code from Amlogic's GPL kernel sources and
by analyzing the registers on an actual GXL and GXM device running the
kernel that was shipped on the boards I have.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06 14:49:47 +05:30
Vivek Gautam 0b56e9a7e8 phy: Group vendor specific phy drivers
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.

Also updated the MAINTAINERS file to reflect the correct
directory structure for phy drivers.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stephen Boyd <stephen.boyd@linaro.org>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-01 15:28:33 +05:30