this patch make it more reasonable and readable, because when we chose
I2S_CKR_TRCM_TXONLY, we only output clk_lrck_tx, and hardware need to
confirm this signal is wired to external codec lrck_tx/rx at the same time.
for convenience, we just handle lrck_txonly if we enable symmetric_rates
in driver and dai_link. otherwise, we use the separate lrck_tx/rx.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
There are 3 i2s sdio pins, which iomux mode is as follows:
- sdi3_sdo1
- sdi2_sdo2
- sdi1_sdo3
we need to configure these pins' iomux mode via the GRF register
when use multi channel playback/capture.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
share lrck_tx to lrck_rx when symmetric_rates enabled.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
support max 8 channels capture, please add property
'rockchip,capture-channels' in dts to enable this,
if not, support 2 channels capture default.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
According to description about "Transmit Data Level",
This bit field controls the level at which a DMA request
is made by the transmit logic.
It is equal to the watermark level.
That is, the dma_tx_req signal is generated when the number
of valid data entries in the TXFIFO
(TXFIFO0 if CSR=00
TXFIFO1 if CSR=01
TXFIFO2 if CSR=10
TXFIFO3 if CSR=11)
is equal to or below this field value.
Different to receive data level, transmit data level does not need
to "-1".
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add driver for i2s controller found on rk3066, rk3168 and rk3288
processors from rockchip.
Tested on the RK3288 SDK board.
Signed-off-by: Jianqun Xu <xjq@rock-chips.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
zhangjun