Commit Graph

3 Commits

Author SHA1 Message Date
Keerthy 7901063617 thermal: ti-soc-thermal: dra7: Implement Workaround for Errata i814
Bandgap Temperature read Dtemp can be corrupted

DESCRIPTION
        Read accesses to registers listed below can be corrupted due to
	incorrect resynchronization between clock domains.

        Read access to registers below can be corrupted :
                • CTRL_CORE_DTEMP_MPU/GPU/CORE/DSPEVE/IVA_n (n = 0 to 4)
        • CTRL_CORE_TEMP_SENSOR_MPU/GPU/CORE/DSPEVE/IVA_n

WORKAROUND
    Multiple reads to CTRL_CORE_TEMP_SENSOR_MPU/GPU/CORE/DSPEVE/IVA[9:0]:
    BGAP_DTEMPMPU/GPU/CORE/DSPEVE/IVA is needed to discard false value and
    read right value:
       1. Perform two successive reads to BGAP_DTEMP bit field.
               (a) If read1 returns Val1 and read2 returns Val1, then
       	right value is Val1.
               (b) If read1 returns Val1, read 2 returns Val2, a third
       	read is needed.
       2. Perform third read
               (a) If read3 returns Val2 then right value is Val2.
               (b) If read3 returns Val3, then right value is Val3.

    The above in gist means if val1 and val2 are the same then we can go
    ahead with that value else we need a third read which will be right
    since synchronization will be complete by then.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
2015-05-08 17:55:46 -07:00
Ranganath Krishnan 547f72ab7d thermal: ti-soc-thermal: Initialize counter_delay field for TI DRA752 sensors
Initialize MPU, GPU, CORE, DSPEVE and IVA thermal sensors of DRA752 bandgap
with the counter delay mask.

Signed-off-by: Ranganath Krishnan <ranganath@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
2013-08-29 09:36:13 -04:00
Eduardo Valentin 8926fa4f9b thermal: ti-soc-thermal: add thermal data for DRA752 chips
This patch adds the thermal data for TI DRA752 chips.
In this change it includes (autogen):
. Register offset definitions
. Bitfields and masks for all registers
. Conversion table

Also, the thermal limits, thresholds and extrapolation
rules are included. The extrapolation rule is simply
add +2C as margin.

All 5 sensors, MPU, GPU, CORE, DSPEVE and IVA, are defined
and exposed. Only MPU has cooling device.

Cc: Zhang Rui <rui.zhang@intel.com>
Cc: linux-pm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2013-06-13 10:15:52 +08:00