Enable the driver for the Layerscape SFP (Security Fuse Processor) found
on most Layerscape SoCs. For example, a per-device unique serial number
is stored in the fuses.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.18, please pull the following:
- Krzysztof aligns the PL330 DMA controller node name to the schema
- Rafal corrects the TWD (Timer/Watchdog) block, adds the watchdog node,
I2C controller node and the pinctrl node for the 4908 SoC
- Kuldeep fixes the Northstar 2 SPI properties as well as the PL022 SPI
controller clock names
- Frank fixes the SATA node names to conform to the AHCI controller
schema
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmImX64ACgkQh9CWnEQH
BwRKhQ//RUIUtJqWOZNMkvspu2VaIOa4DeDFXHQ2F8X7hoRsRw93mksxk90xBuIG
Oz4UdzF5D0cKwXdlNWeJ3V8er6qSkl5V37Z0iBUft6n1vYiqPzQHAG7lvI3r0ZNX
Ial9H1TLuT36CeubcUlb88ztPvMZYDPoUDFQv8GKoavGldwMithoHe6SZ3SFGFVh
/lzRyqJImJR3wITZJboLdyqkUvksj1lofR0kRM25bNZ1QeDxzEdA48svZYnexnGh
PNPGvuhNlT63CBSdteXs5lU2pmt6OhaxUH6Vl9dWE5LznqCrEPAlSy6jiNsymgHp
GqijueWGQyVQYqCE2T0VNowCTLY1a3bl7rFQUigZLCurbqYr932GwZP+r/1/xfqI
pP96QjA/Fz4fjuH9yZ30dTCB3xe69GurM80V3udNi1nr8ExDjOY/3rmrEmKVLKDR
Y94wgzjgzy1Wopvnzu9CtlabixQ7sv0NLJB6YjSSqc+ziBZsnJOl0+b7hWaBTuno
UxBY3pIsekBg4MP6evPHs8muUHO9STXijDwnny6tNj5o/usGrfWIBtilNYnAYg/1
/3UWnDArcV+/zpRhIwsAwYb19pUBOQCpKFLdZYw4yNss12KLqxvmA3fe6JXAu9HF
bmCUEjAwuf3mtEN41V8Tjyp3ftuh7rO3VVjDuT72VfYiEh2QtKU=
=nJaL
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIndl0ACgkQmmx57+YA
GNk5PhAAxL+CTTI8nidIhzO5kO/KZ4NIb7LO/QnMWknn+HeUdXPl0GDRyIpsXml9
X5qcIzL4Npj0U8+UAHYarT6ngDcj8EZDWv+H5zRmt5qXSNhpfnlm+1OEgicy8Y1u
XwgIfLtGbdE9w05i9fPPtSIjoAjMQpJEplOkKKzex3k8GN653dT8bLm/manevoL7
7Sn27jxfQUcRM10QOJcWmF1fqgdl542J31bE4xl1axXww1Fa6aoZAXeeh+XlO8KB
oXJhcw4HLW7LKpZUESCwTiXS7fymSgp73U2bRhr41g40BPzt8wJbmS5MMsY7eiLP
9+kgfswtDrNt5NBDHFye71bU1YXvIAdcWkexlJfio8bsv8HweS+hU61+jpULpbtp
EzttCHoljyyAIpnjOMe7mrQKsm4hTnTcB0vKBgZqpxAlLZaoKcrkknfZz57nwcHL
xLtkug5lEp6jIXtAAQAYZ5ZwkQCUo4oaHlN16DypGvAsvSUd3UjQbLJBtfb7joac
wQ8stJQGhMcSzjyiOAEwSHqJeau9uJ03xWHrKNYPAx8aj5eVtNLMXxNcq69mzMvb
BbDUt8SMedxxficxteZfC3tkoH6CQ+zOHSEAzm/A+Q0GvJkxOkyDt6IW+BE30bGE
vDzfJmwBrf2N8FhnkbJsob+vlWZuAz4ezM5q8i4zHx6U2MoSc3I=
=B+QM
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.18/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 5.18, please pull the following:
- Krzysztof aligns the PL330 DMA controller node name to the schema
- Rafal corrects the TWD (Timer/Watchdog) block, adds the watchdog node,
I2C controller node and the pinctrl node for the 4908 SoC
- Kuldeep fixes the Northstar 2 SPI properties as well as the PL022 SPI
controller clock names
- Frank fixes the SATA node names to conform to the AHCI controller
schema
* tag 'arm-soc/for-5.18/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: stingray: Fix spi clock name
arm64: dts: ns2: Fix spi clock name
arm64: dts: broadcom: Fix sata nodename
arm64: dts: ns2: Fix spi-cpol and spi-cpha property
arm64: dts: broadcom: bcm4908: add I2C block
arm64: dts: broadcom: bcm4908: add watchdog block
arm64: dts: broadcom: bcm4908: add pinctrl binding
arm64: dts: broadcom: bcm4908: use proper TWD binding
arm64: dts: broadcom: align pl330 node name with dtschema
Link: https://lore.kernel.org/r/20220307194817.3754107-3-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.18, please pull the following:
- Arinc defines the switch ports of the RTL8365MB switch on the Asus
RT-AC88U
- Richard provides cache information for the BCM2835/36/37 and BCM2711
SoCs such that tools like "lscpu -C" can report it when supported
- Stefan adds support for the Raspberry Pi Zero 2 W (wireless)
- Matthew defines the MAC address NVMEM cells for the Cisco Meraki
MX64/MX65 devices, he also fixes the LED for these platforms.
- Rafal adds the MAC addres NVMEM cell for the Luxul XWR-3150
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmImXvIACgkQh9CWnEQH
BwTVXxAAoyyP5yDDRysvcEoK0bgNnInp2RyVbYPgI/lMCkn5Ngs/9jTPEveVO3hq
UOljI3uqmi4h+K+bLp7NpqybiueFH/92t26J2V+mqRQ7G1ivKnHXh08B3LBv5OU0
IeOQgUwe+lQLlb6boH4O7dvju/3cnBpJUGW4KZpAzjxtmyRjekutmd+dIlkJr7zM
jvNT+MLvpapCECWgXYo0km7TP1SnIB9TG1EWFPvf7YjYfBhroLEeKQS7K1VANtjG
sVP0FVAuiXRx4cs751EnGoIR2Nla+XrbYrJxZBya81xAZ3rCzwjxbGztdCFDqm5j
gf4D3Ww4NZHVIONOJOWGy7c6KIU1aiSGPzNaqK8rNGyxRH6cmavh5QEIEb6fSQOH
9Gyg0aEbxxaH/j75pa4e60pbivise7+TI1yN23aJDTaIKTEYtkSADVZw3PW++il6
kIOaCGmOaYHMQRCByjTxg6soqbaaSuUZ/A1Frh1Ox/EpfU+6N04+RC+D2OPuSPT/
yuN0P3gYo8/Le1Zv1RB2+0CmNsgrAiRFy9kbD//6WEOaa7r7t3z4RTfFduGrZF2R
XtxDatKKqIkNpWmHp0s2g28QXcDow1mnM/x6g6aA2UR8rCj7mg/odULZyxqStGxj
ehh0M7gZo1P92HVf+HT5A6t/jXk+HEw0xddRh+xdzzrd+JHwTUo=
=ZPvV
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIndXEACgkQmmx57+YA
GNm+zA//RCHiiWwfAgJXPquuZcdcioZw2R451MmvgfVA1ST2hTZexL2jkHym6X/b
UE01YttV0A82JNWy+4zxMVkTefjhbp+rSNSSlMHN+Z3SXIXOZSIEW3eWc+D6UCqw
/XQx8wthJUDCPdGw+e1sW8GqcagY6uwa2xyrBGlhQu9uv7Waor+Q6rbUOKRCr9oD
j4o3wFdBFrMRCg6AzGhchDJ7454C87Nc6hC5xpst9za2O+4uU6LE3GOMuWEHQmTz
hsqkuOPvMNW+6dXicC6nihRUdRS6Km781VFtc5+7xRvPRqpzdAhi83dJz0KmL/Aq
mucnIn+hfPvL6DMGUzSLh+fGR3e2m7586RA7IeRA2Bd/xyJsEBZr59iXg+qhde3V
0odwGqRNWPR5XKOhkSTBW5+JJZveCk7QcLvIYdfPMiNMSEBCSt8M46golgWTmbgA
RB7cOzp5OPUjNmKKN2io4VO6pmnsFUT5ygR652x7LgpX/5t5nanjrOAOQJbObEid
kgO8lFd2arOBW530x6xAyW/RGNZ7rbrCQVoa1jXD5lP1V3isGl32weNp5+dC1OeF
IvEeU7chZli0dXpmKuD8tKU4M0XStBmMYQJHu44UArjYeB4gSR/aYztkaUhX01Aj
jWILMQPMgfvEXb6NYqqxgJhmNpbscwLfhUHDu0gUJ2IhBwRKwTw=
=8qCg
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.18/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.18, please pull the following:
- Arinc defines the switch ports of the RTL8365MB switch on the Asus
RT-AC88U
- Richard provides cache information for the BCM2835/36/37 and BCM2711
SoCs such that tools like "lscpu -C" can report it when supported
- Stefan adds support for the Raspberry Pi Zero 2 W (wireless)
- Matthew defines the MAC address NVMEM cells for the Cisco Meraki
MX64/MX65 devices, he also fixes the LED for these platforms.
- Rafal adds the MAC addres NVMEM cell for the Luxul XWR-3150
* tag 'arm-soc/for-5.18/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul XWR-3150
ARM: dts: NSP: MX6X: correct LED function types
ARM: dts: NSP: MX6X: get mac-address from eeprom
arm64: dts: broadcom: Add reference to RPi Zero 2 W
ARM: dts: Add Raspberry Pi Zero 2 W
dt-bindings: arm: bcm2835: Add Raspberry Pi Zero 2 W
ARM: dts: bcm2835/6: Add the missing L1/L2 cache information
ARM: dts: bcm2711: Add the missing L1/L2 cache information
ARM: dts: bcm2837: Add the missing L1/L2 cache information
ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U
Link: https://lore.kernel.org/r/20220307194817.3754107-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support for the CPU PMUs on the Apple M1.
* for-next/perf-m1:
drivers/perf: Add Apple icestorm/firestorm CPU PMU driver
drivers/perf: arm_pmu: Handle 47 bit counters
irqchip/apple-aic: Move PMU-specific registers to their own include file
arm64: dts: apple: Add t8303 PMU nodes
arm64: dts: apple: Add t8103 PMU interrupt affinities
irqchip/apple-aic: Wire PMU interrupts
irqchip/apple-aic: Parse FIQ affinities from device-tree
dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts
dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts
dt-bindings: arm-pmu: Document Apple PMU compatible strings
Add a new, weird and wonderful driver for the equally weird Apple
PMU HW. Although the PMU itself is functional, we don't know much
about the events yet, so this can be considered as yet another
random number generator...
Nonetheless, it can reliably count at least cycles and instructions
in the usually wonky big-little way. For anything else, it of course
supports raw event numbers.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
Arm ARM documents PMU event numbers as 16-bits in the table and more 0x4XXX
events have been added in the header file, so use 16-bits for all event
numbers and make them consistent.
No functional change intended.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Link: https://lore.kernel.org/r/20220303100710.2238-1-zhangshaokun@hisilicon.com
Signed-off-by: Will Deacon <will@kernel.org>
Armv9[1] has introduced some common architectural events (0x400C-0x400F)
and common microarchitectural events (0x4010-0x401B), which can be detected
by PMCEID0_EL0 from bit44 to bit59, so expose these common events under
sysfs.
[1] https://developer.arm.com/documentation/ddi0608/ba
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Link: https://lore.kernel.org/r/20220303085419.64085-1-zhangshaokun@hisilicon.com
Signed-off-by: Will Deacon <will@kernel.org>
Remove unused gen-y.
Remove redundant $(shell ...) because 'mkdir' is done in cmd_gen_cpucaps.
Replace $(filter-out $(PHONY), $^) with the $(real-prereqs) shorthand.
The '&&' in cmd_gen_cpucaps should be replaced with ';' because it is
run under 'set -e' environment.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20220227085232.206529-1-masahiroy@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Drop several includes of <linux/personality.h> which are not used.
git-blame indicates they were used at some point, but they're not needed
anymore.
Signed-off-by: Sagar Patel <sagarmp@cs.unc.edu>
Link: https://lore.kernel.org/r/20220307222412.146506-1-sagarmp@cs.unc.edu
Signed-off-by: Will Deacon <will@kernel.org>
The following patches resulted in deferring crash kernel reservation to
mem_init(), mainly aimed at platforms with DMA memory zones (no IOMMU),
in particular Raspberry Pi 4.
commit 1a8e1cef76 ("arm64: use both ZONE_DMA and ZONE_DMA32")
commit 8424ecdde7 ("arm64: mm: Set ZONE_DMA size based on devicetree's dma-ranges")
commit 0a30c53573 ("arm64: mm: Move reserve_crashkernel() into mem_init()")
commit 2687275a58 ("arm64: Force NO_BLOCK_MAPPINGS if crashkernel reservation is required")
Above changes introduced boot slowdown due to linear map creation for
all the memory banks with NO_BLOCK_MAPPINGS, see discussion[1]. The proposed
changes restore crash kernel reservation to earlier behavior thus avoids
slow boot, particularly for platforms with IOMMU (no DMA memory zones).
Tested changes to confirm no ~150ms boot slowdown on our SoC with IOMMU
and 8GB memory. Also tested with ZONE_DMA and/or ZONE_DMA32 configs to confirm
no regression to deferring scheme of crash kernel memory reservation.
In both cases successfully collected kernel crash dump.
[1] https://lore.kernel.org/all/9436d033-579b-55fa-9b00-6f4b661c2dd7@linux.microsoft.com/
Signed-off-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
Cc: stable@vger.kernel.org
Reviewed-by: Pasha Tatashin <pasha.tatashin@soleen.com>
Link: https://lore.kernel.org/r/1646242689-20744-1-git-send-email-vijayb@linux.microsoft.com
[will: Add #ifdef CONFIG_KEXEC_CORE guards to fix 'crashk_res' references in allnoconfig build]
Signed-off-by: Will Deacon <will@kernel.org>
Commit 18107f8a2d ("arm64: Support execute-only permissions with
Enhanced PAN") re-introduced execute-only permissions when EPAN is
available. When EPAN is not available, arch_filter_pgprot() is supposed
to change a PAGE_EXECONLY permission into PAGE_READONLY_EXEC. However,
if BTI or MTE are present, such check does not detect the execute-only
pgprot in the presence of PTE_GP (BTI) or MT_NORMAL_TAGGED (MTE),
allowing the user to request PROT_EXEC with PROT_BTI or PROT_MTE.
Remove the arch_filter_pgprot() function, change the default VM_EXEC
permissions to PAGE_READONLY_EXEC and update the protection_map[] array
at core_initcall() if EPAN is detected.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Fixes: 18107f8a2d ("arm64: Support execute-only permissions with Enhanced PAN")
Cc: <stable@vger.kernel.org> # 5.13.x
Acked-by: Will Deacon <will@kernel.org>
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com>
This contains a single, last-minute fix to disable the display SMMU by
default because under some circumstances leaving it enabled by default
can cause SMMU faults on boot.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmImSxQTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoVELD/9exQGVRakSmrp/kcySASsJa9El8Tkh
9rOnmP/+E+V7531G6Nkzhntb5gEnvFRMr36sCJMkyd6J7v7mGKR2/JpgOLH5cIJx
odbN9F68PpVtgG3JUCy8vOl6+5bg7uxTcNaArBRjzghO5Y/vvliL/k647I3mwVfy
6Q3B3Qiq0mMqbxBo5DZDAnElR34Npnmus4LQqSd0P+tEb7LwahfbiRC8mF3YlbEl
p3njS5CJbx8mbXMY2hpM0e7CnVJeFy5i8On4IEdSset3/wR6DuUsbFjyXQPCdX4y
dV0JxDpkAi3lc48tS3h/wM+pCHLR5OSByjGa0qLTLfZUHqEAHLv07GMgDOisBsZw
gDZZHi7na3gOoDDzTFKM8HoHiFssrQSr9Q/DjJoRYVIOssq1aTn5+JNDuD4eJRiB
ukANMZinXuqlmCu/jD+Pm+uOK3zvwvlACPj8BQvF/a51DhczfwEIuilbCC2APAR4
Nl4By38Ee5TNH8X+7zc1x+hX7TvWZWkC/KnOH5Re32rs0b2Wg0lis2gjlDYodgDO
0Ca549fnqHxuC5LHyiUxHJcK5v0i47AtkWpP5Dy4skpbL70GKpJpZvTzWd5CmsyH
UnmGQxACcMCylabC7patqwLrQGSQWiXgA+zJpTp+2lrGNVMMl77jXqukHkmRa2xD
VCAR/jFPpAKmgQ==
=9uGD
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmImhf4ACgkQmmx57+YA
GNlLDhAAwYqtpHFMYBg0HPOwIkPUX9WhAK2WtG83rd5YY8Y5jPZxmCbJyDxveIt4
eQ+6DYtZG+FnZ/0CIKN6XUWENzXJl9fjB40dLXX53TbCxf2llrfr3zZgY8p8sHHP
Kxo2vU79mxmLvZcV9lkp5yNd7Co+Rxoe+KJMMGcvvjWNZZ5lgX9J44+ahmNA7M49
KhV8zMzLHC8FuoeZyQV1AxIXEalPLU34aGrRpBmuEbhv86Gb4MFw5V/5LmLO5jFp
ApWlAiMBM78FqCpvd1/cJs37ckmy8lDnOI/RNM5Ye+2PjIDyC7fC0Pd2N4Odvx2V
VXLVKJ/+4YlXsIMnqh5qHJJr7f3QNFAv2WQDnSitBtyKFLy9IcVmhArDJBLHpXVY
2lPZthcGvawoQJuVYItYTkbBfQkeYisXzZICvEwSZwfb8SK7ZdvvzzOvq2YSg5KR
5XUEuWhYcaFe+Be/LcCJ5PVUfhnlbmvFtK4TpBq/TA3/QjAEdHIsvHR+Q8wMnMoL
qfgx2bTpZiuI6ymmvQyVy8G+8sg3IbRO9CooDLoBQdaQSoh8jzAgSiER70fETf08
7TdsjsWJpkmXgr4UyuXmsHQG/tf/P8dn+53fWe9r5ELxbHOeSHwMaLaqnWm40Iii
FN9KIDQYSMRgvnGapL7iRYv6CMxCJbBc6/Lztj9EU6xGVxlRckg=
=qW8w
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.17-arm64-dt-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes
arm64: tegra: Device tree fixes for v5.17
This contains a single, last-minute fix to disable the display SMMU by
default because under some circumstances leaving it enabled by default
can cause SMMU faults on boot.
* tag 'tegra-for-5.17-arm64-dt-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Disable ISO SMMU for Tegra194
Link: https://lore.kernel.org/r/20220307182120.2169598-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This reverts commit 59a68d4138.
Now that the str{n}cmp functions have been updated to handle MTE
properly, the workaround to use the generic functions is no longer
needed.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220301101435.19327-4-joey.gouly@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Import the latest version of the Arm Optimized Routines strncmp function based
on the upstream code of string/aarch64/strncmp.S at commit 189dfefe37d5 from:
https://github.com/ARM-software/optimized-routines
This latest version includes MTE support.
Note that for simplicity Arm have chosen to contribute this code to Linux under
GPLv2 rather than the original MIT OR Apache-2.0 WITH LLVM-exception license.
Arm is the sole copyright holder for this code.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220301101435.19327-3-joey.gouly@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Import the latest version of the Arm Optimized Routines strcmp function based
on the upstream code of string/aarch64/strcmp.S at commit 189dfefe37d5 from:
https://github.com/ARM-software/optimized-routines
This latest version includes MTE support.
Note that for simplicity Arm have chosen to contribute this code to Linux under
GPLv2 rather than the original MIT OR Apache-2.0 WITH LLVM-exception license.
Arm is the sole copyright holder for this code.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220301101435.19327-2-joey.gouly@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
When a IAR register read races with a GIC interrupt RELEASE event,
GIC-CPU interface could wrongly return a valid INTID to the CPU
for an interrupt that is already released(non activated) instead of 0x3ff.
As a side effect, an interrupt handler could run twice, once with
interrupt priority and then with idle priority.
As a workaround, gic_read_iar is updated so that it will return a
valid interrupt ID only if there is a change in the active priority list
after the IAR read on all the affected Silicons.
Since there are silicon variants where both 23154 and 38545 are applicable,
workaround for erratum 23154 has been extended to address both of them.
Signed-off-by: Linu Cherian <lcherian@marvell.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220307143014.22758-1-lcherian@marvell.com
Signed-off-by: Will Deacon <will@kernel.org>
pud_sect_supported() already checks for PUD level block mapping support i.e
on ARM64_4K_PAGES config. Hence pud_sect_supported(), along with some other
required alignment checks can help completely drop use_1G_block().
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/1644988012-25455-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
When a contiguous HugeTLB page is mapped, set_pte_at() will be called
CONT_PTES/CONT_PMDS times. Therefore, __sync_icache_dcache() will
flush cache multiple times if the page is executable (to ensure
the I-D cache coherency). However, the first flushing cache already
covers subsequent cache flush operations. So only flusing cache
for the head page if it is a HugeTLB page to avoid redundant cache
flushing. In the next patch, it is also depends on this change
since the tail vmemmap pages of HugeTLB is mapped with read-only
meanning only head page struct can be modified.
Signed-off-by: Muchun Song <songmuchun@bytedance.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220302084624.33340-1-songmuchun@bytedance.com
Signed-off-by: Will Deacon <will@kernel.org>
Add a WARN_ON_ONCE() when extracting a field if no width is specified. This
should never happen outside of development since it will be triggered with
or without the feature so long as the relevant ID register is present. If
the warning triggers hope that the field was the standard 4 bits wide and
soldier on.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220307180900.3045812-1-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
This was missed when making specification of a field standard.
Fixes: 0a2eec83c2 ("arm64: cpufeature: Always specify and use a field width for capabilities")
Reported-by: Qian Cai <quic_qiancai@quicinc.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220302134225.159217-1-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Commit 6d502b6ba1 ("arm64: signal: nofpsimd: Handle fp/simd context for
signal frames") introduced saving the fp/simd context for signal handling
only when support is available. But setup_sigframe_layout() always
reserves memory for fp/simd context. The additional memory is not touched
because preserve_fpsimd_context() is not called and thus the magic is
invalid.
This may lead to an error when parse_user_sigframe() checks the fp/simd
area and does not find a valid magic number.
Signed-off-by: David Engraf <david.engraf@sysgo.com>
Reviwed-by: Mark Brown <broonie@kernel.org>
Fixes: 6d502b6ba1 ("arm64: signal: nofpsimd: Handle fp/simd context for signal frames")
Cc: <stable@vger.kernel.org> # 5.6.x
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220225104008.820289-1-david.engraf@sysgo.com
Signed-off-by: Will Deacon <will@kernel.org>
We may call arm64_apply_bp_hardening() early during entry (e.g. in
el0_ia()) before it is safe to run instrumented code. Unfortunately this
may result in running instrumented code in two cases:
* The hardening callbacks called by arm64_apply_bp_hardening() are not
marked as `noinstr`, and have been observed to be instrumented when
compiled with either GCC or LLVM.
* Since arm64_apply_bp_hardening() itself is only marked as `inline`
rather than `__always_inline`, it is possible that the compiler
decides to place it out-of-line, whereupon it may be instrumented.
For example, with defconfig built with clang 13.0.0,
call_hvc_arch_workaround_1() is compiled as:
| <call_hvc_arch_workaround_1>:
| d503233f paciasp
| f81f0ffe str x30, [sp, #-16]!
| 320183e0 mov w0, #0x80008000
| d503201f nop
| d4000002 hvc #0x0
| f84107fe ldr x30, [sp], #16
| d50323bf autiasp
| d65f03c0 ret
... but when CONFIG_FTRACE=y and CONFIG_KCOV=y this is compiled as:
| <call_hvc_arch_workaround_1>:
| d503245f bti c
| d503201f nop
| d503201f nop
| d503233f paciasp
| a9bf7bfd stp x29, x30, [sp, #-16]!
| 910003fd mov x29, sp
| 94000000 bl 0 <__sanitizer_cov_trace_pc>
| 320183e0 mov w0, #0x80008000
| d503201f nop
| d4000002 hvc #0x0
| a8c17bfd ldp x29, x30, [sp], #16
| d50323bf autiasp
| d65f03c0 ret
... with a patchable function entry registered with ftrace, and a direct
call to __sanitizer_cov_trace_pc(). Neither of these are safe early
during entry sequences.
This patch avoids the unsafe instrumentation by marking
arm64_apply_bp_hardening() as `__always_inline` and by marking the
hardening functions as `noinstr`. This avoids the potential for
instrumentation, and causes clang to consistently generate the function
as with the defconfig sample.
Note: in the defconfig compilation, when CONFIG_SVE=y, x30 is spilled to
the stack without being placed in a frame record, which will result in a
missing entry if call_hvc_arch_workaround_1() is backtraced. Similar is
true of qcom_link_stack_sanitisation(), where inline asm spills the LR
to a GPR prior to corrupting it. This is not a significant issue
presently as we will only backtrace here if an exception is taken, and
in such cases we may omit entries for other reasons today.
The relevant hardening functions were introduced in commits:
ec82b567a7 ("arm64: Implement branch predictor hardening for Falkor")
b092201e00 ("arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support")
... and these were subsequently moved in commit:
d4647f0a2a ("arm64: Rewrite Spectre-v2 mitigation code")
The arm64_apply_bp_hardening() function was introduced in commit:
0f15adbb28 ("arm64: Add skeleton to harden the branch predictor against aliasing attacks")
... and was subsequently moved and reworked in commit:
6279017e80 ("KVM: arm64: Move BP hardening helpers into spectre.h")
Fixes: ec82b567a7 ("arm64: Implement branch predictor hardening for Falkor")
Fixes: b092201e00 ("arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support")
Fixes: d4647f0a2a ("arm64: Rewrite Spectre-v2 mitigation code")
Fixes: 0f15adbb28 ("arm64: Add skeleton to harden the branch predictor against aliasing attacks")
Fixes: 6279017e80 ("KVM: arm64: Move BP hardening helpers into spectre.h")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220224181028.512873-1-mark.rutland@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
The following interrelated ranges are needed by the kdump crash tool:
MODULES_VADDR ~ MODULES_END,
VMALLOC_START ~ VMALLOC_END,
VMEMMAP_START ~ VMEMMAP_END
Since these values change from time to time, it is preferable to export
them via vmcoreinfo than to change the crash's code frequently.
Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20220209092642.9181-1-shijie@os.amperecomputing.com
Signed-off-by: Will Deacon <will@kernel.org>
SPI clock name for pl022 is "sspclk" and not "spiclk".
Also fix below dtc warning:
clock-names:0: 'spiclk' is not one of ['SSPCLK', 'sspclk']
Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
SPI clock name for pl022 is "sspclk" and not "spiclk".
Also fix below dtc warning:
clock-names:0: 'spiclk' is not one of ['SSPCLK', 'sspclk']
Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The mitigations for Spectre-BHB are only applied when an exception is
taken from user-space. The mitigation status is reported via the spectre_v2
sysfs vulnerabilities file.
When unprivileged eBPF is enabled the mitigation in the exception vectors
can be avoided by an eBPF program.
When unprivileged eBPF is enabled, print a warning and report vulnerable
via the sysfs vulnerabilities file.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Based on a brief discussion on the mailing list it was determined that
clock-cells should be a required parameter in the event that a consumer
of the clock gets added in an overlay.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/20220303203958.4904-3-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Rockchip rk808 Power Management IC does not have a vcc13 or a
vcc14. The schematics for at least the Pinebook Pro suggest this is
actually vcc1 and vcc2, and may be an artifact from the reference
design schematic).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/20220303203958.4904-2-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
A label reference without brackets is a path string, not a phandle as
intended. Add the missing brackets.
Fixes: a5002c41c3 ("arm64: dts: rockchip: add WiFi module support for Firefly-RK3399")
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220304202559.317749-1-robh@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Daniel Borkmann says:
====================
pull-request: bpf-next 2022-03-04
We've added 32 non-merge commits during the last 14 day(s) which contain
a total of 59 files changed, 1038 insertions(+), 473 deletions(-).
The main changes are:
1) Optimize BPF stackmap's build_id retrieval by caching last valid build_id,
as consecutive stack frames are likely to be in the same VMA and therefore
have the same build id, from Hao Luo.
2) Several improvements to arm64 BPF JIT, that is, support for JITing
the atomic[64]_fetch_add, atomic[64]_[fetch_]{and,or,xor} and lastly
atomic[64]_{xchg|cmpxchg}. Also fix the BTF line info dump for JITed
programs, from Hou Tao.
3) Optimize generic BPF map batch deletion by only enforcing synchronize_rcu()
barrier once upon return to user space, from Eric Dumazet.
4) For kernel build parse DWARF and generate BTF through pahole with enabled
multithreading, from Kui-Feng Lee.
5) BPF verifier usability improvements by making log info more concise and
replacing inv with scalar type name, from Mykola Lysenko.
6) Two follow-up fixes for BPF prog JIT pack allocator, from Song Liu.
7) Add a new Kconfig to allow for loading kernel modules with non-matching
BTF type info; their BTF info is then removed on load, from Connor O'Brien.
8) Remove reallocarray() usage from bpftool and switch to libbpf_reallocarray()
in order to fix compilation errors for older glibc, from Mauricio Vásquez.
9) Fix libbpf to error on conflicting name in BTF when type declaration
appears before the definition, from Xu Kuohai.
10) Fix issue in BPF preload for in-kernel light skeleton where loaded BPF
program fds prevent init process from setting up fd 0-2, from Yucong Sun.
11) Fix libbpf reuse of pinned perf RB map when max_entries is auto-determined
by libbpf, from Stijn Tintel.
12) Several cleanups for libbpf and a fix to enforce perf RB map #pages to be
non-zero, from Yuntao Wang.
* https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next: (32 commits)
bpf: Small BPF verifier log improvements
libbpf: Add a check to ensure that page_cnt is non-zero
bpf, x86: Set header->size properly before freeing it
x86: Disable HAVE_ARCH_HUGE_VMALLOC on 32-bit x86
bpf, test_run: Fix overflow in XDP frags bpf_test_finish
selftests/bpf: Update btf_dump case for conflicting names
libbpf: Skip forward declaration when counting duplicated type names
bpf: Add some description about BPF_JIT_ALWAYS_ON in Kconfig
bpf, docs: Add a missing colon in verifier.rst
bpf: Cache the last valid build_id
libbpf: Fix BPF_MAP_TYPE_PERF_EVENT_ARRAY auto-pinning
bpf, selftests: Use raw_tp program for atomic test
bpf, arm64: Support more atomic operations
bpftool: Remove redundant slashes
bpf: Add config to allow loading modules with BTF mismatches
bpf, arm64: Feed byte-offset into bpf line info
bpf, arm64: Call build_prologue() first in first JIT pass
bpf: Fix issue with bpf preload module taking over stdout/stdin of kernel.
bpftool: Bpf skeletons assert type sizes
bpf: Cleanup comments
...
====================
Link: https://lore.kernel.org/r/20220304164313.31675-1-daniel@iogearbox.net
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Now that we properly account for interrupts taken whilst the guest
was running, it becomes obvious that there is no need to open
this accounting window if we didn't exit because of an interrupt.
This saves a number of system register accesses and other barriers
if we exited for any other reason (such as a trap, for example).
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20220304135914.1464721-1-maz@kernel.org
Add support for ptp interrupt. This interrupt is used when using 2-step
timestamping. For each timestamp that is added in a queue, an interrupt
is generated.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Currently the first thing checked is whether the PCSI cpu_suspend function
has been initialized.
Another change will be overloading `acpi_processor_ffh_lpi_probe` and
calling it sooner. So make the `has_lpi` check the first thing checked
to prepare for that change.
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Move the check for the actual pgmap types that need the free at refcount
one behavior into the out of line helper, and thus avoid the need to
pull memremap.h into mm.h.
Link: https://lkml.kernel.org/r/20220210072828.2930359-7-hch@lst.de
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: "Sierra Guiza, Alejandro (Alex)" <alex.sierra@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Alistair Popple <apopple@nvidia.com>
Cc: Ben Skeggs <bskeggs@redhat.com>
Cc: Chaitanya Kulkarni <kch@nvidia.com>
Cc: Karol Herbst <kherbst@redhat.com>
Cc: Lyude Paul <lyude@redhat.com>
Cc: Miaohe Lin <linmiaohe@huawei.com>
Cc: Muchun Song <songmuchun@bytedance.com>
Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>
Cc: Ralph Campbell <rcampbell@nvidia.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
dma-cells property is required for dma-controller. Fixes dtbs_check
warnings like:
dma@c1128000: '#dma-cells' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanho Min <chanho.min@lge.com>
Link: https://lore.kernel.org/r/20220129175514.298942-1-krzysztof.kozlowski@canonical.com
The recently added configuration option for Cortex A510 erratum 2077057 does
not have a "default y" unlike other errata fixes. This appears to simply be
an oversight since the help text suggests enabling the option if unsure and
there's nothing in the commit log to suggest it is intentional.
Fixes: 1dd498e5e2 ("KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata")
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220225184658.172527-1-broonie@kernel.org
After converting ahci-platform txt binding to yaml nodename is reported
as not matching the standard:
arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dt.yaml:
ahci@663f2000: $nodename:0: 'ahci@663f2000' does not match '^sata(@.*)?$'
Fix it to match binding.
Fixes: ac9aae00f0 ("arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
second patch was supposed to fix the first, but in reality it was
just as broken, so both have to go.
x86 host:
* Revert incorrect assumption that cr3 changes come with preempt notifier
callbacks (they don't when static branches are changed, for example)
ARM host:
* Correctly synchronise PMR and co on PSCI CPU_SUSPEND
* Skip tests that depend on GICv3 when the HW isn't available
-----BEGIN PGP SIGNATURE-----
iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmIeGnUUHHBib256aW5p
QHJlZGhhdC5jb20ACgkQv/vSX3jHroMCYgf9GPVUOQUbHVxVqvKB1ABnY3ZIZuS3
+/XLgVifSmXb2sPQmcKIPk7eQkxlzpnVdbznJO5qFMtVKRv/ppj+/ly2wwF8l+rR
m1XvyYo2sukK5vTpBrQiRm3aWY7vpx0ds4DStLnrnBuPF/U7x6WlHSL/BqXaNcSJ
e+SXd/UFhkg7dEQaU3eqXyf2/mMfR2ZLdUb4v+/UiV7kfzzvRqNERd8HUoVk2FcM
VYBr07ChaV4XB/dZsCDVSz2Z7f7rH3sMMW82ZHKjuFUEW4Dij9NiX2ycaeRvkSLG
tnliTuROCY2bOQeIVCTHf5XqCAAm7sA1AoClFaUy30+UW9s9j45NuhUQbA==
=nuHK
-----END PGP SIGNATURE-----
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm fixes from Paolo Bonzini:
"The bigger part of the change is a revert for x86 hosts. Here the
second patch was supposed to fix the first, but in reality it was just
as broken, so both have to go.
x86 host:
- Revert incorrect assumption that cr3 changes come with preempt
notifier callbacks (they don't when static branches are changed,
for example)
ARM host:
- Correctly synchronise PMR and co on PSCI CPU_SUSPEND
- Skip tests that depend on GICv3 when the HW isn't available"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: selftests: aarch64: Skip tests if we can't create a vgic-v3
Revert "KVM: VMX: Save HOST_CR3 in vmx_prepare_switch_to_guest()"
Revert "KVM: VMX: Save HOST_CR3 in vmx_set_host_fs_gs()"
KVM: arm64: Don't miss pending interrupts for suspended vCPU
Build the CVP driver in the standard arm64 defconfig.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
The N5X platform has the Synopsys DDR controller the includes an EDAC
controller. Add the entry for the controller in the DTS file instead of
the base Agilex DTSI because the base Agilex does not have the
controller.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
USB DWC2 requires clock-names:
arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dt.yaml:
usb@ffb00000: 'clock-names' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
New platforms: Snapdragon 625 and Snapdragon 632
New boards: Google Herobrine R1, Fairphone FP3, SHIFT6mq, Samsung Galaxy
Book2 and Snapdragon 8 Gen 1 Hardware Development Kit (HDK)
On IPQ6018 the USB reference period is corrected, GICv2m support is
enabled and the max-link-speed for PCIe is specified.
IPQ8074 adds description of GIVv2m and SMEM, and ensures that TrustZone
related memory is reserved from Linux.
On the Snapdragon 7c Gen 3 (SC7280) description of display, displayport,
L3 interconnect, bluetooth, CPU opp-tables are added. Another revision
of the Google Herobrine is introduced and a bunch of cleanups are
introduced.
On Snapdragon 845 new support for the SHIFT6mq device is introduced, the
OnePlus devices gains fuel gauge and the platform gains GSI DMA support,
which is enabled for SPI (for now).
On the Snapdragon 850 based WindowsOnSnapdragon laptops, initial support
for Samsugn Galaxy Book2 is introduced and the Lenovo Yoga C630 gains
description of its backlight controls.
The Snapdragon 625 platform (MSM8953) the thereof derrived Snapdragon
632 platform is introduced, with initial description of the Fairphone 3.
Fairphone 4 on the SM7225 platform gains proper WLED configuration.
On Snapdragon 855 (SM8150) description of the limits hardware (LMh) is
introduced and the SPI and I2C devices are wired to the GSI DMA controller.
On Snapdragon 865 (SM8250) the CPU and cluster idle states are
introduced, the MSI interrupts for PCIe 1 and 2 are corrected and the
CPUfreq driver gains knowledge about thermal pressure interrupts.
On Snapdragon 8 Gen 1 (SM8450) LLCC, interconnect and remoteproc
descriptions are added. The SM8450 Hardware Development Kit is
introduced and the QRD has its remoteproc instances enabled.
Cluster idle and RPMh parameters are corrected on SM8150, SM8350 and
SM8540.
The IPA device on SC7180, SC7280 and SM8350 gains knowledge of the AOSS
QMP mailbox, allowing it to enable retention of IPA registers during
power collapse.
DeviceTree validation issues related to thermal zone naming, missing
CPU, device and platform compatibles, APR, Google EC PWM, DB410c sound,
QCS404 opp-tables and SM8250 PCIe nodes are corrected.
A bunch of cleanups and style fixes for MSM8992, MSM8994, MSM8996 and
MSM8916 are introduced as well.
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmIdsU4bHGJqb3JuLmFu
ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FyaMP/0gQTc8OAvNRtsnir8th
uYgPu3OgIdJy85xE0ql5s9o2TLVgnLVTOpAimUSJsxds0GWwsFMfmE+cFaz7bdmw
Qf30xIO40IJctft79uFhW1JjrBvjHzh1LqTWNHXDN/x5ZhcDuP+xUPvQxAxf8gfu
1VCB1ZwfLmA5la/gZ9Gg5xoHM2UdbOwlWx/v7Tx/H3ra0LCOFwfMgA1ljaavmnlU
tOkcRROVgNNSDBeROBWG1tug6Nb9MOjaCQXmEIaSZkzCFmxo8+rxLbySzVU6esOr
DUp7plV0MLFG+4i9tG5VmOP+l9oZ7pyJE002v575oO7W8muLB0VqGmHRwxnHcmTF
rMuIcpRgdXzc5SjckWQC67GjL0qDAkI4tPcjKIjepP3ODFo2K0kt9oXPNUgbCyVO
DWL98UrXhZii4482+TmikceZe5mYhFoIq1dX5fzS0yXromq+QnlM5UwPrjhi1dGz
KWUIDt7BjoP8trfukNc3X61vxDU7ca5BlGwoJnH0X3Fh7b24BpNHSy7mF1sE0cfF
bn89rjm9sEf9gK9jbpkp2Xwit4wjAp8E95dsp/+J1HBV6t4L20vTBrkXwh2zRLDN
SDF/Nfof5NDITEHyIRbyP9Q8Ilbk8QdSllWyUkJa4I8/3k1C1J+p1oE3nocrtJWJ
LH5yCnajaLzPm/PCOyBflqmM
=rj9c
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmId8moACgkQmmx57+YA
GNmEVxAAhaKNPlZp4stzDhGwdwCI8heagtON6QN012QTu2KYLLh/5rFBooRhAMef
7fKk/LcNxOA6vZgOkYks4Hm5y/VwXAaKhOMEqlQ+D5JGe1Pq5iZVXt35xGpuHfrF
edcbyjy6XckjBVFpP2+wT+THmcwQgZLFsO2C9eRn/AiAY8P2akM+bG8g+giejT+f
KtL39P6TtP2dqiuyrXd/lua1TD3X5cubugw5JbsGwPk6SqoSOMkiSJbgIeH4oQan
qqu+V/S9cCKijzV34IqtudMUUF3Z+BZDZQ0snU0iiuZ8B+W963lv+O6N7azeN/h9
a0q/YuAr9+DMt8kVfI8cIpf4lRz9wS2jc7/0wbXn6UjjoxIRdcYz7jR5IVtNysNq
syqh9e9Se6bJFwQ2vCvkOuZZ8JSjj/lWcTBNjMI5QEAm9gfQKUmK+cNkQWIenll/
OA50XzSA5+AvSKvvG0TnLvfIAbkCsRwf3+XVXnIjvfYD4e2mZepbHBWhC6PTXyVO
V79jLfxM4tj891t/w9qsaEuCF5GfXT4w+Mii+mHNQtm7tfLz3NDnwz68QuogjUmp
9L6TpmbvmCwmOv1mHVk9kQPckG25CsaBg2CGIoFI3MTjMRPycIoiOpKSd+u4NejK
kLlia0qBIJVCGllhDLgct51OUcG6Am6W9bl32L8KLNXHPNiTZYc=
=EUCM
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 DeviceTree updates for v5.18
New platforms: Snapdragon 625 and Snapdragon 632
New boards: Google Herobrine R1, Fairphone FP3, SHIFT6mq, Samsung Galaxy
Book2 and Snapdragon 8 Gen 1 Hardware Development Kit (HDK)
On IPQ6018 the USB reference period is corrected, GICv2m support is
enabled and the max-link-speed for PCIe is specified.
IPQ8074 adds description of GIVv2m and SMEM, and ensures that TrustZone
related memory is reserved from Linux.
On the Snapdragon 7c Gen 3 (SC7280) description of display, displayport,
L3 interconnect, bluetooth, CPU opp-tables are added. Another revision
of the Google Herobrine is introduced and a bunch of cleanups are
introduced.
On Snapdragon 845 new support for the SHIFT6mq device is introduced, the
OnePlus devices gains fuel gauge and the platform gains GSI DMA support,
which is enabled for SPI (for now).
On the Snapdragon 850 based WindowsOnSnapdragon laptops, initial support
for Samsugn Galaxy Book2 is introduced and the Lenovo Yoga C630 gains
description of its backlight controls.
The Snapdragon 625 platform (MSM8953) the thereof derrived Snapdragon
632 platform is introduced, with initial description of the Fairphone 3.
Fairphone 4 on the SM7225 platform gains proper WLED configuration.
On Snapdragon 855 (SM8150) description of the limits hardware (LMh) is
introduced and the SPI and I2C devices are wired to the GSI DMA controller.
On Snapdragon 865 (SM8250) the CPU and cluster idle states are
introduced, the MSI interrupts for PCIe 1 and 2 are corrected and the
CPUfreq driver gains knowledge about thermal pressure interrupts.
On Snapdragon 8 Gen 1 (SM8450) LLCC, interconnect and remoteproc
descriptions are added. The SM8450 Hardware Development Kit is
introduced and the QRD has its remoteproc instances enabled.
Cluster idle and RPMh parameters are corrected on SM8150, SM8350 and
SM8540.
The IPA device on SC7180, SC7280 and SM8350 gains knowledge of the AOSS
QMP mailbox, allowing it to enable retention of IPA registers during
power collapse.
DeviceTree validation issues related to thermal zone naming, missing
CPU, device and platform compatibles, APR, Google EC PWM, DB410c sound,
QCS404 opp-tables and SM8250 PCIe nodes are corrected.
A bunch of cleanups and style fixes for MSM8992, MSM8994, MSM8996 and
MSM8916 are introduced as well.
* tag 'qcom-arm64-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (96 commits)
arm64: dts: qcom: sdm632: Add device tree for Fairphone 3
dt-bindings: arm: qcom: Document sdm632 and fairphone,fp3 board
arm64: dts: qcom: Add SDM632 device tree
arm64: dts: qcom: Add PM8953 PMIC
arm64: dts: qcom: Add MSM8953 device tree
dt-bindings: arm: cpus: Add Kryo 250 CPUs
arm64: dts: qcom: msm8916-longcheer-l8150: Add light and proximity sensor
arm64: dts: qcom: align Google CROS EC PWM node name with dtschema
arm64: dts: qcom: Add support for Samsung Galaxy Book2
arm64: dts: qcom: msm8996: convert xo_board to RPM_SMD_BB_CLK1
arm64: dts: qcom: msm8996: add cxo and sleep-clk to gcc node
arm64: dts: qcom: sdm845: add bi_tcxo to camcc
arm64: dts: qcom: sdm845: enable dma for spi
arm64: dts: qcom: sdm845: Add gsi dma node
arm64: dts: qcom: sc7280: Add cpu OPP tables
arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node
arm64: dts: qcom: ipq6018: drop the clock-frequency property
arm64: dts: qcom: ipq8074: drop the clock-frequency property
arm64: dts: qcom: sm8450: add interconnect nodes
...
Link: https://lore.kernel.org/r/20220301053929.1809684-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This starts off by fixing an issue introduced in a bug fix in the
global clock controller, where the symbol clocks for UFS would
end up picking the wrong parent clock which breaks UFS.
It then makes sure that the reference clock for the USB blocks are
enabled, even with booting without clk_ignore_unused.
It corrects the apps SMMU interrupts defintion by adding a missing
interrupt in the list.
Lastly it disables the Qualcomm crypto hardware (for now) on the Lenovo
Yoga C630, to prevent the cryptomanager tests during boot from crashing
the device.
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmIdk9IbHGJqb3JuLmFu
ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3Fi0UQAJEw6/F9aFsdaGRHO3D+
XhgEooCMMbF0QNewWdw5FXoYW46SH2enl3monIHSAbyoKO6mkzXxBmuOOfpIvkNj
mmqW6gOhsqa4ZUlAwJ9Q1OzQUuOfaLtvORMk0NSi6BohvNqtsN1mVNbYUlpEiYLj
9O2QHoLlKoq+yGUMvFOb+dLScGI2oLfqpfewLW+wRSNuDfLhZxbd850MeWH0ZpuQ
qOPSF+2WStVvf9ZZSijSPqZBl5gtf0fHiwXBJQfxdQvHcAMk4OKKZySSl8xJhX5i
Tgn/+5+B2bLIga1DdmfYu1y3h/05w2420qdVkouh5ue0YtZfp1I6LRUwJfNLnkzA
elu+p4N5g+8QstSV0ntN5cBpQSqqQodXOolcxDG9K/GdZwHdsOsC4Mgfowg6RMRI
hTWmGIT+ZDfXUlpJa6ZLv3qUEm4MqLKbNcVYYKqJD7UJJxOlw46owKvjJpJwAyxP
yzkJhXCzDb9rV6pPqj3XslWIl25xNipi5Spm8EXkL5SyZijF9RLlzCqnnMjGueNp
GHl4hKMJeyWxoOuiFhF7oCymQLnroEgzAJddWHqmH4lT2CZuri1yLiZGiTTBm8B/
Q7SuT9sAqQKUKM25o6XPdUS7JGLDVDIVSGORIQLeYLc8IddBCfDGIf7YJAzBhs0x
ROuQCmuSyUncsjO5AEXdOrSK
=soai
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmId60sACgkQmmx57+YA
GNl98w/+KWpsJ/FLxKqSsCjeqp2j6x4wkq/krSLelCI56G3BLhdI8SxnD4GUdiA3
yR5B8Hev1JFp/YlqU2F8JSyDwKKUkp1ghP1KuAkl1CWbgZo5TOGwOw4ZqBH8jUgd
mKNMfA+6m7Hqcwpq6ojN6r2HZKg315N22/egRsOPpx6Du5iGKGeepjiGXbixVyWe
EdI9gDKCuDSqg2Ium1z0oKwPUNTbFBHkrMXYDmlJFoSz63lJEpDvoJZHKx05hri1
S/PCzcoBEOVk91jKlrC1lnlofpCVcuoTnZ72awAOyIwMrvcjkw+nB6E3zHSuD818
RFBUgGu5CwfdhShMr1J8kcOgvhobnSgs0YH7shY99BsxJkwCwUkjbUJN/ihG4TN6
qnGvr2PbA6vphBIDPLcXj2gBSJyB8feu7xD9Su+H+6BgriP0hLQ0WOIMbznM808U
3fR8K0tqzfPx9MeEcdOYZ29wvATUn6++GZjszZEeDVkpqQJIhbscrHOZhOKgz/TR
l62chtqp1wt/hpspjzYOfDCbETS+qBhXtgz4Y8RArx7fGbdKbjZOMdAaoVzPQuKG
tSsjDH+7OpnBQ4+PeDd9044P8h6XyYT9SE5CqDI5WfNOLZve2fZuepbEwQI9KnKz
qzkFIyDq518IMWvTJMc2ethrgTrBlGp02fk7o6v1Jo1VwoWDhwY=
=9VJk
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-fixes-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
Qualcomm ARM64 DeviceTree fixes for 5.17
This starts off by fixing an issue introduced in a bug fix in the
global clock controller, where the symbol clocks for UFS would
end up picking the wrong parent clock which breaks UFS.
It then makes sure that the reference clock for the USB blocks are
enabled, even with booting without clk_ignore_unused.
It corrects the apps SMMU interrupts defintion by adding a missing
interrupt in the list.
Lastly it disables the Qualcomm crypto hardware (for now) on the Lenovo
Yoga C630, to prevent the cryptomanager tests during boot from crashing
the device.
* tag 'qcom-arm64-fixes-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: dts: qcom: c630: disable crypto due to serror
arm64: dts: qcom: sm8450: fix apps_smmu interrupts
arm64: dts: qcom: sm8450: enable GCC_USB3_0_CLKREF_EN for usb
arm64: dts: qcom: sm8350: Correct UFS symbol clocks
Link: https://lore.kernel.org/r/20220301033526.1801295-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch updates the format of memory node in DT adding the
device_type.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Link: https://lore.kernel.org/r/20220119123537.9968-3-sam.shih@mediatek.com
[mb: fixed commit message]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This patch updates the format of memory node in DT adding the correct
device_type.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Link: https://lore.kernel.org/r/20220119123537.9968-2-sam.shih@mediatek.com
[mb: fixed commit message]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add power domains controller node for SoC mt8192
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20210825010426.30303-1-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Broadcom ns2 platform has spi-cpol and spi-cpho properties set
incorrectly. As per spi-slave-peripheral-prop.yaml, these properties are
of flag or boolean type and not integer type. Fix the values.
Fixes: d69dbd9f41 (arm64: dts: Add ARM PL022 SPI DT nodes for NS2)
Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
CC: Ray Jui <rjui@broadcom.com>
CC: Scott Branden <sbranden@broadcom.com>
CC: Florian Fainelli <f.fainelli@gmail.com>
The code changes address mostly minor problems:
- Several NXP/FSL SoC driver fixes, addressing issues with error
handling and compilation
- Fix a clock disabling imbalance in gpcv2 driver.
- Arm Juno DMA coherency issue
- Trivial firmware driver fixes for op-tee and scmi firmware
The remaining changes address issues in the devicetree files:
- a timer regression for the OMAP devkit8000, which has to use
the alternative timer.
- A hang in the i.MX8MM power domain configuration
- Multiple fixes for the Rockchip RK3399 addressing issues
with sound and eMMC
- Cosmetic fixes for i.MX8ULP, RK3xxx, and Tegra124
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIc+ooACgkQmmx57+YA
GNnNhQ/+O3PntP8vYNO50tteeFVuClgyb4hA2P2xx6Kis4dLSTDaUcTd3745roLh
mT6k90fZH3nBKQHzDSlc5Pf0mpskuJFOwt96wDC6a40VAW7+VwTFDdFDOG3z/KyX
+8yXWv613EjzE5IYx0LEt0W2/2CaHfzysu99o1J6Wrp0DkHyh7lmgvrRzdckYCqZ
Bj4ehCyaMTFyoSyFJDrs/+HDeN7eeeEwS/UXzzvQnNfne+kKVsJKcpfg6pPsLjOV
oMadkV42uLB79XZs1R5/4bs2NL7ceFphtDovKaeZ9z3HKF0ZFudYfq93ymflS/df
l/uXBX6eRrT8C6IuJSlCN8vZWD9vLOzcBTrNx7mbk9gcXjaN91tXu7TJqurWu8xk
t5F7H1gfPcVD7jTGdD9cArqJTJAFTeyMB0eUFdGhX7KhDo+oeJQ49HTzjx8TEX6y
oEL6LnGBFYvnV6TYZtkp/aPvaqFaJ4j5WT+VzsVina8yOAKb0bWizoC3I2IvyNXS
aX3rSuJ3vYfm6wmcdx3yCS0wAD7mqOip7OeuG43L8pcnc4Fgz/cFtzsB6shl9oNj
e41/xfvnyn+mGn2QnZ41XjcnZieRcwZ62OaMfMhd3Oa7Xj7XD0lE5fFd7LnfJ0pn
5xsMpHo+AuPHO1YyMFmMopqYNuromtQLmNCdg6LDnsXAnL7g45c=
=NNpd
-----END PGP SIGNATURE-----
Merge tag 'soc-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"The code changes address mostly minor problems:
- Several NXP/FSL SoC driver fixes, addressing issues with error
handling and compilation
- Fix a clock disabling imbalance in gpcv2 driver.
- Arm Juno DMA coherency issue
- Trivial firmware driver fixes for op-tee and scmi firmware
The remaining changes address issues in the devicetree files:
- A timer regression for the OMAP devkit8000, which has to use the
alternative timer.
- A hang in the i.MX8MM power domain configuration
- Multiple fixes for the Rockchip RK3399 addressing issues with sound
and eMMC
- Cosmetic fixes for i.MX8ULP, RK3xxx, and Tegra124"
* tag 'soc-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits)
ARM: tegra: Move panels to AUX bus
soc: imx: gpcv2: Fix clock disabling imbalance in error path
soc: fsl: qe: Check of ioremap return value
soc: fsl: qe: fix typo in a comment
soc: fsl: guts: Add a missing memory allocation failure check
soc: fsl: guts: Revert commit 3c0d64e867
soc: fsl: Correct MAINTAINERS database (SOC)
soc: fsl: Correct MAINTAINERS database (QUICC ENGINE LIBRARY)
soc: fsl: Replace kernel.h with the necessary inclusions
dt-bindings: fsl,layerscape-dcfg: add missing compatible for lx2160a
dt-bindings: qoriq-clock: add missing compatible for lx2160a
ARM: dts: Use 32KiHz oscillator on devkit8000
ARM: dts: switch timer config to common devkit8000 devicetree
tee: optee: fix error return code in probe function
arm64: dts: imx8ulp: Set #thermal-sensor-cells to 1 as required
arm64: dts: imx8mm: Fix VPU Hanging
ARM: dts: rockchip: fix a typo on rk3288 crypto-controller
ARM: dts: rockchip: reorder rk322x hmdi clocks
firmware: arm_scmi: Remove space in MODULE_ALIAS name
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
...
We need the USB fixes in here, and it resolves a merge conflict in:
drivers/usb/dwc3/dwc3-pci.c
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The clock binding documents PCIe clock for a long time already. Add
clock phande into the PCIe node.
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Atomics for eBPF patch series adds support for atomic[64]_fetch_add,
atomic[64]_[fetch_]{and,or,xor} and atomic[64]_{xchg|cmpxchg}, but it
only adds support for x86-64, so support these atomic operations for
arm64 as well.
Basically the implementation procedure is almost mechanical translation
of code snippets in atomic_ll_sc.h & atomic_lse.h & cmpxchg.h located
under arch/arm64/include/asm.
When LSE atomic is unavailable, an extra temporary register is needed for
(BPF_ADD | BPF_FETCH) to save the value of src register, instead of adding
TMP_REG_4 just use BPF_REG_AX instead. Also make emit_lse_atomic() as an
empty inline function when CONFIG_ARM64_LSE_ATOMICS is disabled.
For cpus_have_cap(ARM64_HAS_LSE_ATOMICS) case and no-LSE-ATOMICS case, the
following three tests: "./test_verifier", "./test_progs -t atomic" and
"insmod ./test_bpf.ko" are exercised and passed.
Signed-off-by: Hou Tao <houtao1@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20220217072232.1186625-4-houtao1@huawei.com
Will Deacon says:
====================
On Tue, Feb 22, 2022 at 10:38:02PM +0000, Will Deacon wrote:
> On Thu, 17 Feb 2022 15:22:28 +0800, Hou Tao wrote:
> > Atomics support in bpf has already been done by "Atomics for eBPF"
> > patch series [1], but it only adds support for x86, and this patchset
> > adds support for arm64.
> >
> > Patch #1 & patch #2 are arm64 related. Patch #1 moves the common used
> > macro AARCH64_BREAK_FAULT into insn-def.h for insn.h. Patch #2 adds
> > necessary encoder helpers for atomic operations.
> >
> > [...]
>
> Applied to arm64 (for-next/insn), thanks!
>
> [1/4] arm64: move AARCH64_BREAK_FAULT into insn-def.h
> https://git.kernel.org/arm64/c/97e58e395e9c
> [2/4] arm64: insn: add encoders for atomic operations
> https://git.kernel.org/arm64/c/fa1114d9eba5
Daniel -- let's give this a day or so in -next, then if nothing catches
fire you're more than welcome to pull this branch as a base for the rest
of the series.
====================
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20220222224211.GB16976@willie-the-truck
1. Minor fixes and cleanups in newly introduced support for Exynos850.
2. Add basic support for Exynos7885 and Samsung Galaxy A8 (2018):
SM-A530F.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmIaoIgQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD16CtD/wIWks7DuJBI4l3CGqWe+30xjIuTbcClWn9
cykB6hONIz1Gpw+l2i/RFaYIDYD+HA9FyCC+dRvL+SuGp+awFqcgIOtTs3YzBVti
Tu3XKX2q9xodGeMx/1vDkAfg9dpKgIs9ua4DMYeTW0B7/WTaX7YUayEDHIV4E5Z4
FUSjD1S+JHyFQXpJrU+vlGTyLx2IbUW7ybvh0wcEdCeqVdmpg10tgjaZiKBGbNGe
m56Wnq2v0hMVN7Ol60WUuvbKS5+l1UJtbOQQEiHU/t7qHji2zO1mMrdXiAcqp4CE
9SPPS5uOQCVkNrNdpICQwDx+A4Fb96I1oiOoZ30EX/5VWLU2tCrWdYltRqqeYtIF
vq9Zha4WCj80OFYfcXzHYyZf4E+OqqORZYE8plXoO7kphqRQrX0GV6MT+Sh2hmks
zZosZUmuKj0bKZx41gDmilS5Q5a4eg0hoRFxl7DqBBulAgACJalfiLxlJXyOymwg
a1hYrdWbUKhtyZ272Scsd3PG1kDqboanVp0ziIXgB4OWHefTeYGo84x4rDGU8Ttf
nB2sSxalTjSWHvmywLG0iHWdaGkXKqvXS1pomvHDCNnabBCXKxgpXFuUNbrE+Nre
5FTwveJ4CrSZbKdXcLDtXwx9Z8f+7PmROm+1E0XT7ohZXSezrxTCfYyVFyOlv3Zm
315FnazzXw==
=+2r/
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIc2b0ACgkQmmx57+YA
GNkFnBAAtnETyanWN205FGTIYpP0Up8Vj+4q1fultPqzcZ3bK0uo2PNl7iS3FyUW
ix75d8onM/dakkjIRAUTsnv6oK+9LrmsPUBg4zac9AbEUo8w3sGlTeQwAHQ5kuDS
WlZHHzkB2GFeZzwlKCYMuCgWFyOzizl9kTQmRxRcJYYd5/VzpdlcCJwwdlN5Rcvn
4v3Mtr0Mz4YyS8Ij9EKX/xJ18S6VRU6tbHhlU5EVW4QpUbqAd3kUh2IbUO+PuFjk
rs2kicGOP3BcmIPDa8ABscf//50NLIAHBFvl55MzL6Z+NPWdfg7EhlUGIXIs786p
XDEUMNzwPGmba4gyDYLp5/bYe94+x0dnmFk7+i3kymHLh6xCfEE8HA8f5qAGIz1W
GKuNUeKsh0nQNBEHW8Y4KbJIjz5/Q09wWF8iA2WliL40iktos6CcpDU+mjE57Z2T
GCO/4dh3gYDz/+jLhBrrQrBIvt4i3xTnlnQ0yboyb20urXbHoJ6nqma+NKVvtkID
5YhZHMFEPhJ5J6NBEJJ1OHXkJV1hR+EjP5kW3zvla5pkSfdYzTkZ6FmwovG13Nk/
D9MG6r0NQMUfw+8OxoD4Qo5Mv2bNZemya3JjhAYvA9MJLgKDvY4DONaVVlW4ym0A
/VdR7vN40aNHb8Ahr+3AKYLc4j4ldSGNAhTRJZMd6Hlxe8za14U=
=efOO
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.18, part two
1. Minor fixes and cleanups in newly introduced support for Exynos850.
2. Add basic support for Exynos7885 and Samsung Galaxy A8 (2018):
SM-A530F.
* tag 'samsung-dt64-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC
arm64: dts: exynos: use dedicated wake-up pinctrl compatible in Exynos850
arm64: dts: exynos: align pinctrl with dtschema in Exynos850
arm64: dts: exynos: drop incorrectly placed wakeup interrupts in Exynos850
Link: https://lore.kernel.org/r/20220226220116.13452-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Based on the for-5.18/dt-bindings changes, this adds various new
features on Tegra234 such as IOMMU, audio, gpio-keys, I2C and PWM
support.
Device trees for 64-bit Tegra boards are now also built with overlay
support enabled, which allows firmware to apply overlays and customize
the DTB that is passed to the kernel.
There are also a couple of cleanups and additions for older devices,
such as USB device mode support on Jetson Xavier NX.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmIZBv4THHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoQCxD/91Rrrx6YerbjauJbX8on8yFhRGQUuf
MNvOkfyzI3fSZjJyfZxR13gcJp0gh8oaFBEoBnIaSUEN+lLtlWZl4oQOU+Y1ZE1x
vXiResOWGJaugKcRsR1CiGPnsWUDBiJtnRqoRdZSWUDHKno2ekqMS9lhMp+PmMY0
8U/m3VV4C6JvNe9gO5kwo0egYRe9jFuncwtepi/YFUpMkGQ6P5WC1PjrLH3xJm3i
609zobLbbOreV/ZN3W3x3uUgh49bm9FORwRSHrlmv79rlnBLMEXDEbWP4GHuDSUR
jVFu9tghxv6PGy6JxkNomdv9EYOjrLa8NgmXKkfbLEIZf4jT1cNXrtSufhyj4GXC
5KKkPB19fMtv/t53EzDjkDLfVAuCb/yBO62rtj28DLsR30ubhlVBK4GcHIsAcmot
wz0mE7+NkBsr3X2qCUr0JBC6thFv6X8E5bXTc/zsGDfVNnKl8k+zXejiZDh68aVN
EHYgQLneAWIQ2Af1nK6gQjs3pMdiqtAUZlCVFL0vM6VgT9hGi1N8l1DeHZa7elJw
WHUrSFr/56WBdC0eKT2nxDzhygEGxkjkI2HKI/7hVrsRaOOC4rY4PDat0VwWyUIN
JYPjTKqVcvYa+rNuAr7P4/EMl4kglB6dBTQFyeT446ff9R5Umxpvv+CaPD0aDz0o
8TzA9Gc89MiH2Q==
=ZfCL
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIc2QUACgkQmmx57+YA
GNm8RxAAn4b8uK0TQ/AMvgdFabENBfsNGm6cYVIUp28SW1PBwacSzXRJYLypVXqv
HWb6GmWoDqgvCHPFYtUF68IvC1SY3pgT517UFSXucnfqXw17Ew9rY45lNkW4rEI3
jEmaTGNdqon33KTNQyH6r8m4qL8lKOAdU7TO4UjvcAK41eHL2r4uTLe2hNW+etqR
/3Vbc5aVY6gq89hQh00KNjd6RSaLC/axJCBd2fMEwGFYHajk8IEldKe2bTPU/hWZ
egNEmWjRPy3SvJ+zKl8irbaEIvgGv59gE9mTiqDfgTHXI3FPe8I3DwqYo0a9Wmjb
6ACU9NfO6pyXgfaPtiqtQRN/QHhJngc/pZLX7x0GdszSDGff44Z/GY6Sowi3Y56i
h8H+bYXZouCqH8Sb850fO+Bxlrl5TuwCQ8CwVzwlKgkbnmfVMPk6pmdSuLRJGcpr
d+Tor0jbZWF4OO1vNcJ9YmA+/CVWmOuDDJU40IwuQldHwAZsVcAt2J88FkteYn28
seVQOkfbXIhR8r80aUU+E9yTgYAr7k9wJU+B4qB2HLZM6CxEkfRk82BpJODTakD8
42CvZIZXBCQ+ulTUTxz0nmHCjipJPOIxJ83eYEwuCZkgM79b0APiSVjw0htPmCzD
znh6zecOBtxr1ftNnZPi+aVfyuJDpmnkpuw+netaDms3gRqFpxE=
=l0Ys
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.18-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.18-rc1
Based on the for-5.18/dt-bindings changes, this adds various new
features on Tegra234 such as IOMMU, audio, gpio-keys, I2C and PWM
support.
Device trees for 64-bit Tegra boards are now also built with overlay
support enabled, which allows firmware to apply overlays and customize
the DTB that is passed to the kernel.
There are also a couple of cleanups and additions for older devices,
such as USB device mode support on Jetson Xavier NX.
* tag 'tegra-for-5.18-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Drop arm,armv8-pmuv3 compatible string
arm64: tegra: Enable Jetson Xavier NX USB device mode
arm64: tegra: Enable UART instance on 40-pin header
arm64: tegra: Add HDA device tree node for Tegra234
arm64: tegra: Enable device-tree overlay support
arm64: tegra: APE sound card for Jetson AGX Orin
arm64: tegra: Add audio devices on Tegra234
arm64: tegra: Move audio IOMMU properties to ADMAIF node
arm64: tegra: Add Tegra234 IOMMUs
arm64: tegra: Enable gpio-keys on Jetson AGX Orin Developer Kit
arm64: tegra: Add GPCDMA node for tegra186 and tegra194
arm64: tegra: Add Tegra234 PWM devicetree nodes
arm64: tegra: Add Tegra234 I2C devicetree nodes
Link: https://lore.kernel.org/r/20220225164741.1064416-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
insn_to_jit_off passed to bpf_prog_fill_jited_linfo() is calculated in
instruction granularity instead of bytes granularity, but BPF line info
requires byte offset.
bpf_prog_fill_jited_linfo() will be the last user of ctx.offset before
it is freed, so convert the offset into byte-offset before calling into
bpf_prog_fill_jited_linfo() in order to fix the line info dump on arm64.
Fixes: 37ab566c17 ("bpf: arm64: Enable arm64 jit to provide bpf_line_info")
Suggested-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Hou Tao <houtao1@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20220226121906.5709-3-houtao1@huawei.com
BPF line info needs ctx->offset to be the instruction offset in the whole JITed
image instead of the body itself, so also call build_prologue() first in first
JIT pass.
Fixes: 37ab566c17 ("bpf: arm64: Enable arm64 jit to provide bpf_line_info")
Signed-off-by: Hou Tao <houtao1@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20220226121906.5709-2-houtao1@huawei.com
AM62 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM625 SoC. It supports the following interfaces:
* 2 GB DDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
* x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display
* x1 Headphone Jack
* x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x4 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin User Expansion Connector
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 20-pin header for Programmable Realtime Unit (PRU) IO pins
* 15-pin CSI header
Add basic support for AM62-SK.
Schematics: https://www.ti.com/lit/zip/sprr448
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20220225120239.1303821-6-vigneshr@ti.com
This add bare minimum DT for AM62 describing ARM compute clusters, Main,
MCU and Wakeup domain and interconnects, UARTs and I2Cs to enable
booting using ramdisk.
Hierarchy of dts files:
am62.dtsi:
base SoC skeleton which is common across am62xx family of SoCs,
includes am62-main.dtsi, am62-mcu.dtsi and am62-wakeup.dtsi
representing 3 domains and peripherals in each of these domain
am625.dtsi:
describes CPU cluster (Quad A53s). Since, am625 is a current superset
device with all peripherals, am625.dtsi includes am62.dtsi completing
SoC definition.
Individual EVMs using this SoC will just need to include am625.dtsi
thus making things easier for Board and SOM Vendors.
Future derivative SoCs will have their own am62{1-9}{1-9}.dtsi
overriding cluster / peripheral definitions with their own compatibles.
More details about the SoCs can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7
Co-developed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Co-developed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20220225120239.1303821-5-vigneshr@ti.com
mt8183-kukui-jacuzzi has an anx7625 bridge connected to the output of
its DSI host. However, after commit fd0310b6fe ("drm/bridge: anx7625:
add MIPI DPI input feature"), a bus-type property started being required
in the endpoint node by the driver to indicate whether it is DSI or DPI.
Add the missing bus-type property and set it to 5
(V4L2_FWNODE_BUS_TYPE_PARALLEL) so that the driver has its input
configured to DSI and the display pipeline can probe correctly.
While at it, also set the data-lanes property that was also introduced
in that same commit, so that we don't rely on the default value.
Fixes: fd0310b6fe ("drm/bridge: anx7625: add MIPI DPI input feature")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220214200507.2500693-1-nfraprado@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add watchdog device node to MT8192 SoC.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220207094024.22674-1-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
One of the things that CONFIG_HARDENED_USERCOPY sanity-checks is whether
an object that is about to be copied to/from userspace is overlapping
the stack at all. If it is, it performs a number of inexpensive
bounds checks. One of the finer-grained checks is whether an object
crosses stack frames within the stack region. Doing this on x86 with
CONFIG_FRAME_POINTER was cheap/easy. Doing it with ORC was deemed too
heavy, and was left out (a while ago), leaving the courser whole-stack
check.
The LKDTM tests USERCOPY_STACK_FRAME_TO and USERCOPY_STACK_FRAME_FROM
try to exercise these cross-frame cases to validate the defense is
working. They have been failing ever since ORC was added (which was
expected). While Muhammad was investigating various LKDTM failures[1],
he asked me for additional details on them, and I realized that when
exact stack frame boundary checking is not available (i.e. everything
except x86 with FRAME_POINTER), it could check if a stack object is at
least "current depth valid", in the sense that any object within the
stack region but not between start-of-stack and current_stack_pointer
should be considered unavailable (i.e. its lifetime is from a call no
longer present on the stack).
Introduce ARCH_HAS_CURRENT_STACK_POINTER to track which architectures
have actually implemented the common global register alias.
Additionally report usercopy bounds checking failures with an offset
from current_stack_pointer, which may assist with diagnosing failures.
The LKDTM USERCOPY_STACK_FRAME_TO and USERCOPY_STACK_FRAME_FROM tests
(once slightly adjusted in a separate patch) pass again with this fixed.
[1] https://github.com/kernelci/kernelci-project/issues/84
Cc: Matthew Wilcox (Oracle) <willy@infradead.org>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-mm@kvack.org
Reported-by: Muhammad Usama Anjum <usama.anjum@collabora.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
---
v1: https://lore.kernel.org/lkml/20220216201449.2087956-1-keescook@chromium.org
v2: https://lore.kernel.org/lkml/20220224060342.1855457-1-keescook@chromium.org
v3: https://lore.kernel.org/lkml/20220225173345.3358109-1-keescook@chromium.org
v4: - improve commit log (akpm)
- Enable the new Audio Graph Card2 driver which can handle sound cards
more flexibly in the arm64 defconfig,
- Disable unneeded 8250 serial options in shmobile_defconfig,
- Enable additional support for Renesas platforms in the arm64
defconfig.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYgZfpgAKCRCKwlD9ZEnx
cM5XAP4nyb1rxKQpDWbdozSOmItkytpfC2+NTS9+Ul0mAVz98QD/YfuW1awSR8EE
6iyGVM2WqFbaKKGNEqogHI2eNGvbyAk=
=HkeI
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIZLs0ACgkQmmx57+YA
GNnkeRAAsmvm8kbzQwA3yC+hPKAC+DmizTvdmTs5KO4Vrb9i036KMfjRxzBKKFVO
VZzUIIQG75sJ6gGHMYxdYH4K/frkwzE+iDQcQTjNQovUilyqfjiGiJbiPONL47QT
G8dm6UhZ/tdnatDVRdWWmhmrXOuu/Jg7Gn9KLcDxzSdZ/bGhy2GdbwXLHvlvmD4n
xGO2Oh4ZAp6QDngdppD2Cs5DjwqlqnpxqKjW+H6kuOI2f7wIoTkLMrfiwcNnB2Ei
53EnBphPlCLvMzM5HZgBjOWb+xUiVTQvDiaQ1IlgCZMKI22XKExvUrLnoO9PzhRE
IuTXo/bLPWkN9iiR4nvE7rsW47xU4e2BPX4614Lzg4agzIlKKh1q28wka1rirfU9
9vQRAfItZhU29TRURzrDyZOfbZ8rQmHLxff89V79ki5B+FkegopUP6im8ZmyNkhV
8+ucoBi0QHqus6IvSzWvYzVSBk6oK6+/EsHTVve+CTRLfzeoGaiHUgxeODEw5vlI
fePQOORMPMbhg6oTkokL3BVi0ZfvBItzR6Sb7pHsdjwZaexVYDk/ssWiQyrRPFjz
LuPPG7qQpysCiINbHZmK511MDCVlyu5hQiWTA4Njq7qtjZxrVH8sBehKox8XkqUI
8t9GIx619GKDIH7Uw9nGlYD5gPwxiDr57lv1RU9SXnanTdL24g0=
=G8H0
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-defconfig-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/defconfig
Renesas ARM defconfig updates for v5.18
- Enable the new Audio Graph Card2 driver which can handle sound cards
more flexibly in the arm64 defconfig,
- Disable unneeded 8250 serial options in shmobile_defconfig,
- Enable additional support for Renesas platforms in the arm64
defconfig.
* tag 'renesas-arm-defconfig-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: defconfig: Enable additional support for Renesas platforms
ARM: shmobile: defconfig: Disable unneeded 8250 serial options
arm64: defconfig: Enable Audio Graph Card2 driver
Link: https://lore.kernel.org/r/cover.1644587198.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add a new defconfig for Cortex-M based i.MXRT family.
- A series from Marcel Ziswiler to rebuild arm64 defconfig with
'savedefconfig', and then enable various relevant options needed by
Toradex verdin-imx8mm device.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUkysUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7+rwgAh6O4IeWd9PFgNsocVV5gjJUSr3HE
N6kODKwbd6xbVt+JA6kAUfhqaDAOO5daicnB+BIjTxnttflZXxpER10G5HBZL1qH
ACglN1NQPzz38RzfeJd/PaNqixMFsOdn4RsHbwQicX8aHUBP7MpfFh0FT50/fpgo
nYeW5itpyvcSHzTrmgXNveriVz7/UiE5i/0FSvwEjjraD2hWVFI3nZgHFtzQcVhe
KLD8Q8f1bH40wEAH4KAlWY0m5VD5jmnAkeRMlvYzWnKaG1sl2gsZlGb1w1zOrC41
lD+mU/SvcNoe4Bupn3J6BjA1MISfaKClYWbJ0iOVj3S6RUQKC8ToUxHVJA==
=ozsC
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIZAdMACgkQmmx57+YA
GNkfIRAAuxlkBlz8iIL2dh0Y7BB3NaKhwkWJxw9h5vT0/UE8QmGOFytvyA1VUcHM
KkF33OI6ua/ge6uWh3n/ehIx2qMsi47bMCt29PBa06UEBii4h/B8/mL+A368H/Pt
cpUDndCLiSRoA+FAlrWgykBh1xAKAaUeZR43IMJpzwR5IaW2wW2anDZ+JRRb1bFO
E3keZOIGey6HwSwsjZILJ5yg9RoUcPunXsmxobfAQfDu+I4BZiE3f2H1gYMp9+Jk
hTtxBeBUXR3T6MERT4RLNNr85NC9vMtxPDMSWE6JqV/TKF/+TvWZPyRmY/J0JJlM
mh1RAsWvglpO4rRu08SN8AsUdl63CTMmie+5VFnzOBx7bJiPxlGlEA2ib/YstMtP
ETRqXsg/Mghce+Xo8JMKhszsQU/V8jWBFWRrjyZEiVOt44BuOH4kfqkjBQ/fuGH6
Wq+G/diIcKH675elakze17GGoS6pOqK3Po83G18W48DzNee8m8WYiCWVN7qQNWe5
3DZnW1E1SILZAZMQNsDqWN9VBXr6OiDA/mz4ypiCQo/sIGBYVjXX77XTo7L9h6S2
zLm6OGwVjNQqsFG5KXbfxZGOXGXJpJjhsDBfRRAYbpqNKbrANv/Fs07khpQXQMBc
b7a3JZMijOIqSOZ9aIjeSocuQ5IUtuSec2L2e0oqYf5WA0r2euc=
=Ce1L
-----END PGP SIGNATURE-----
Merge tag 'imx-defconfig-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig
i.MX defconfig change for 5.18:
- Add a new defconfig for Cortex-M based i.MXRT family.
- A series from Marcel Ziswiler to rebuild arm64 defconfig with
'savedefconfig', and then enable various relevant options needed by
Toradex verdin-imx8mm device.
* tag 'imx-defconfig-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: defconfig: enable verdin-imx8mm relevant drivers as modules
arm64: defconfig: build r8169 as a module
arm64: defconfig: build imx-sdma as a module
arm64: defconfig: enable imx8m pcie phy driver
arm64: defconfig: enable bpf/cgroup firewalling
arm64: defconfig: rebuild default configuration
arm64: defconfig: re-order default configuration
arm64: defconfig: enable pcieaer configuration
arm64: defconfig: enable taskstats configuration
ARM: imxrt_defconfig: Add i.MXRT family defconfig
Link: https://lore.kernel.org/r/20220222075226.160187-6-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable drivers for USB and SERDES IPs on TI K3 SoC
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmHEEI0QHHZpZ25lc2hy
QHRpLmNvbQAKCRDERh5FfJEW4+qvB/9bn7oXiHF0tdkgeFu1naq0gIBXbcbH6xxU
O9EAbRlVn3NC6XApDx/KuKaIHtogjV4n+PkLaStLcyBd3SYEB2k/VvnKI0IFlhPG
L8u+t6O5/pNUK9MZzT6+VsY67CAOHjdy/kU83UboD4EsgXn2NS0EosGTQFs/RCVt
0LQONv5+6Tu8UaBg0tt3r6Q6THMcSsLzqCVfMZgehhCOJmk1yQ/7VeiFZtJr0RX5
M1G+IWYhgaWNpzO3AAxkM3iWXo3xL7vDi8eNhMX1nSLygfkQ4TSyoYHxo32VfoWH
U9js6HwDj7+KaPDfvGlkGW/4vjGgPiFN/iJXTGEeFZdap41jc9aN
=L/gY
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIZAb0ACgkQmmx57+YA
GNncsg/5ATuitQ1/ldRlL8sUNp+aaaLMsv2QYDSbFZbu+N2mcYp4YGk7/E6cJQwv
Y0556Uu9YGUwMqDw2KfHX/a0hXx0yM7GDvvG7F75axXaaJOQR/EvqmAwsyKK/z/Y
z5/P8n0a5N4lmzv20H4JRS2k0khBcat+z9oBRJMpv1iG8uo/f7oLzfQ5snxIhbvX
2DcYNG7fhIf2+6WL+xE8s9Sz0R7qZGR3IS0udcdTZFiwtQA+whfkUP+fSncgiFMB
VRipr3gafZ1P0qFWFRvFiWQT5XsYJErMZbP1qZizn8w4f3NiQK/1iGWiJ4KUeGG2
lFzQNFUFEpTaYJahg+Os3vTD+pntCoNwVtvr5Q8s+GkkZ/vbt8aeHDpzIMcMkIp6
E0YKT1ejw/tt65fVWCLIX4WExgMEmCgs3xv4Gqs5x7fhToy3NP0k8SSL/VBD0RLF
uM5Spoyc2K876qD7DHykCEFvhDLurS89RcDCzTmFe1MABne5J5DMOedBNUvuBAz2
gSHHNsJXHkZtHcBVUFw6Wvo0P0KKvh5Sl32rJpLjKw4H3R5TwC86gnhvz+iYzpE4
MQgj0KiwnDT1LDp0l8ncIVaEdeNlH+7OUxBm3ChyIg5JU3Kkmtf8dSN0EDMJwbo+
OMhK30EgzJYY62GKq0jr7NTz4djI8uWBKmL7MWqCHfUM2qKBjzA=
=OX1P
-----END PGP SIGNATURE-----
Merge tag 'ti-k3-config-for-v5.17-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/defconfig
ARM64 defconfig changes for TI K3 platforms for v5.17 merge window:
- Enable drivers for USB and SERDES IPs on TI K3 SoC
* tag 'ti-k3-config-for-v5.17-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
arm64: defconfig: Enable USB controller drivers for TI K3 SoC
Link: https://lore.kernel.org/r/20211223094040.15349-1-vigneshr@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Pin control support for the R-Car S4-8 SoC on the Spider development
board.
-----BEGIN PGP SIGNATURE-----
iHQEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYhjYwAAKCRCKwlD9ZEnx
cKSXAP0aBTnnmwZauIy0QIa2YGrGAqaiU1q++b0LV3iygbinSwD46Goz5adJeXrZ
+wta4wt82uakJRUdwouY+wBR4bPODw==
=kgbD
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8vEACgkQmmx57+YA
GNn3OQ/+IhJ3AtsNRjl2YK5jBsXggax+Af4lVyB9ihBDN1HyWa1y2QjMRFcBmviY
Q/F+OdkyXNi6bUESDC7oCeZRqrW7qcw8gjy6ItPPgQC7UfUeluBxVedxbw+y7Mvm
8zwca6UPjOw4IdJgwCMVslSvqZnoiuUjJFacYQ6k/l8JBeKiuPDytgwx9tG0BXkV
Dps71xdxScpp55KyLYqU7MR3j9f6VtnP/46rdTs+xecRoASElrsXxojt0R6NLufg
7rtKoFzLNXHDR9L4xJNNgWVoq50OCK4nsZSFk6LZVQmMgpwTzA2V4zGEeWqLZsMw
Mey/RV7rG1T1YR3BY038BIaqJ+TnCbLXgp2TaEa6vgE4P8FyswobPRDZrzaVPSIc
gY2GrpmtonuIol7Ew8NSe9Mj8EbxPva95S3zK/XFdjHvb/9nG5hRaoN6dDEiF9ln
JTD0eWL5j9cPuzUtann49lbPhljnRjwRLWu42Sz1LQvpyHbNQPr+B6jehhJj7Flp
XVvSM3kczoEXEz4dzSqAo7SRMC2QC06luv5KO8J2uxwz3QYQo/1FEDxzM9Y11mZx
8nEeh4c/bWJ9b1Ob+PkD8P63uzizEYXeaMq7MrBXhNRoZGthga6QbiSlt0bv8B7m
iYCsEnzueJTz5X/70P5uYGltiQtQ5k2HHvFwA/jf1YrNEM4JIT8=
=61Bh
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.18-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.18 (take three)
- Pin control support for the R-Car S4-8 SoC on the Spider development
board.
* tag 'renesas-arm-dt-for-v5.18-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: spider: Complete SCIF3 description
arm64: dts: renesas: r8a779f0: Add pinctrl device node
Link: https://lore.kernel.org/r/cover.1645795643.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Document the use of the renesas-soc IRC channel,
- Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the
Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYhiomwAKCRCKwlD9ZEnx
cHPXAQDNxh5Fr/t8POQlZRhXr/qw9vSkP/bslbLBXIxQmtTuiAD/QOwd02UBun5Q
ei27RcXBOmzpxJBD281LL2fF560h9Ak=
=gcXB
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8lYACgkQmmx57+YA
GNnvkQ/+KA3wN4WIuWG1DfkRh3wOL06EtIlbMTomH7IGvPkPVI6s5lYgPN85pWOb
Sq50/TRTX+Lo3wU7bHWm6D4uik2i7haeFLXLnMm4p020OggqZlFlIStIg2AcZ4Mb
Xu4NFHKlBEelNW4r5lgWpVwpfX37NJb5dY/ZX/oW8fNzTGufGGN/QHLKXzyIpw09
gWTL6d9EIiY6up79mX48RHQ/lLjNLs/8Ae0nnmtHRp3268vGUaUhI1ybzKdAWfsg
0pgAk2bF5oPxpkMDe4/0cilB/BDHF2TRgt8/yXXJZ34EQTXciKu/Zi3n4CmViAHr
aPm9pF9SFFuiTS0PyeY9fyj3gjb3/vj0h6Slyr/U7b4YchdVJ+wLduued3hr0tJt
3LBKtAtxgc0EqOxf772UtWcd8ZPfDH0nJnAbEotZV7y03VRWK/eKgwIQ/j5kc9go
rSZ6Gc/2YeexK5nPSxir0XDelQjVDSRo/yDQmoSPvduUJrga1N4p1MVLSGvmWimB
o/oISmNVvl868/kMTmv9RwZlmULMAgjIqQ2yrwE1kCc2x0p04aWFRoYv7e++GG3M
tK/TvodD4BvjTDVPUMrG7Az5QPjMs8QbLIIGjulGcxwPlRW6tn09Eha+qTcA4X5o
tpyk5zPZDkw+MdixdjuBCkrD8Y6yFG7foRf6Rmnhqh9oClQmplk=
=WR66
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.18 (take two)
- Document the use of the renesas-soc IRC channel,
- Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the
Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: dts: renesas: Align GPIO hog names with dtschema
arm64: dts: renesas: Align GPIO hog names with dtschema
arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog
ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeout
ARM: dts: r9a06g032: Add the watchdog nodes
dt-bindings: clock: r9a06g032: Add the definition of the watchdog clock
arm64: dts: renesas: spider-cpu: Enable watchdog timer
arm64: dts: renesas: r8a779f0: Add RWDT node
MAINTAINERS: Specify IRC channel for Renesas ARM64 port
MAINTAINERS: Specify IRC channel for Renesas ARM32 port
arm64: dts: renesas: ulcb-kf: fix wrong comment
Link: https://lore.kernel.org/r/cover.1645784466.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
New peripherals for the rk356x-family (pdm-audio, gpu, another i2s, usb2)
A lot of additions to Quartz-A (connector-header, gpu, sdmmc1, io-domains,
usb2) and rk3568-evb1-v10 (rk809-audio, cpu-regulator, gpu, tsadc, led,
usb2, touchscreen).
Fixes for the pwm-regulators, that used wrong names for their supplies
as well adapting the cros-ec pwm nodes to a changed binding (going via
the pwm tree).
And as sort of misc-changes, defined the logic-regulator on rk3399-puma
as well as enabled the mali-gpu on the rk3399-firefly.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmIX+P8QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgfZLB/9DUe9pJWRo7zg3GENlp9d3slQBJkBWHF4h
SiYheGDbQyfWmPeH4PcvwfwsVmTdNewRTgmhEbNKyl64XEIEbIVi7GXEmfCaNipQ
zEfTN/m1hMl1kn9gey+0yJT9K3oAkA4UqBUbGmgP/UuYcztZvnhjnt9Np60gwBhf
l7de3OBFcxQUatq2Tfn+HbqiGA5aur/IfJzcrzK9kFXLi6Ox2nMZGN1U2CTmJEcT
ZLFQH1tKQ0doacaAUtRSSx3IbTVSoOjr2imSzsfPKCM691OwwGC4XeJLVTn3QmVF
4WhDQsH+ufluG/dFHPA7Nqa1IVp9IX/QhOW1ZAgmODNVR37EkXGp
=cIwM
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8fUACgkQmmx57+YA
GNnjPw/+LYwi3YXP4izmG0u6y/Jfmy1J6T37FCZJEo8C9I92USUU+S6z9pEG5yrn
LhmXogJj3zB6dGUcq7nFUXIUA5YMVGxofnFRbyxbGPUmRnQSfpOB2/g4aSEYf2U8
0OwD/4ajxVOP2mSimQ7gXnwpzfeUvNrml81VJ76OHZnVtEqt81l/vIyWpd3Dro00
EQN+THTAV4G2M6XhshILt5QTLdsWHwPoCaZAg0PwmIJDU/3NeBH92rXIQiWkE33R
zmPJyOZ2ih3D2ceyVVdNp9uIvLcXeIpsXqIQv2dN0D5iXjviyBqfX787S4PFLlLO
ibsYyB+JUkciwzHyRrKHRYlOXuZmhYDYcL1M+6STSMtmZfS3Kno6V9kOdPYWpTZ8
SluJYqdkED0NMggegunGj67qbe902hX9vuL3vISaZUll3Au48YGSEoEcpghf8kuE
E2Uo4pnEkhN/1sSeZFyINUstKtqpa/XMAS2sK/CJQ09HjQfqvFnifjUxhjqYoAM6
ylhjDymjH11h3jWDmiJUpYfPxa4u/j598UI4ajvKgwPhd0ZxLug43d9IQBpFxux6
qXCWQrgUe39L5o8hfgQSXb58g72uGBXMRd8m7F3G52teGkFz+xentxHbJEZlX8oZ
UQJXCDHhkFpGkD3TNOc4YbQW/ydDZo+OCzWopP3iU6oG2X3FPQY=
=yqpJ
-----END PGP SIGNATURE-----
Merge tag 'v5.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New boards: Pine64 PineNote ereader tablet and Bananapi-R2-Pro (both rk356x)
New peripherals for the rk356x-family (pdm-audio, gpu, another i2s, usb2)
A lot of additions to Quartz-A (connector-header, gpu, sdmmc1, io-domains,
usb2) and rk3568-evb1-v10 (rk809-audio, cpu-regulator, gpu, tsadc, led,
usb2, touchscreen).
Fixes for the pwm-regulators, that used wrong names for their supplies
as well adapting the cros-ec pwm nodes to a changed binding (going via
the pwm tree).
And as sort of misc-changes, defined the logic-regulator on rk3399-puma
as well as enabled the mali-gpu on the rk3399-firefly.
* tag 'v5.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (28 commits)
arm64: dts: rockchip: align Google CROS EC PWM node name with dtschema
arm64: dts: rockchip: enable rk809 audio codec on the rk3568 evb1-v10
arm64: dts: rockchip: set vdd_gpu regulator on rk3568-evb1-v10 to always on
arm64: dts: rockchip: add the vdd_cpu regulator to rk3568-evb1-v10
arm64: dts: rockchip: enable work led on rk3568-evb1-v10
arm64: dts: rockchip: fix supplies for pwm regulators
arm64: dts: rockchip: define vdd_log on rk3399-puma
arm64: dts: rockchip: Add Pine64 PineNote board
arm64: dts: rockchip: Add pdm node to rk356x
dt-bindings: arm: rockchip: Add Pine64 PineNote board
arm64: dts: rockchip: enable the tsadc on rk3568-evb1-v10
arm64: dts: rockchip: enable the gpu on rk3568-evb1-v10
arm64: dts: rockchip: enable the gpu on quartz64-a
arm64: dts: rockchip: add cooling map and trip points for gpu to rk356x
arm64: dts: rockchip: add gpu node to rk356x
arm64: dts: rockchip: add usb2 support to rk3568-evb1-v10
arm64: dts: rockchip: rename and sort the rk356x usb2 phy handles
arm64: dts: rockchip: add the i2s3_2ch node to rk356x
arm64: dts: rockchip: Add Bananapi R2 Pro
dt-bindings: rockchip: Add BananaPi R2 Pro Board
...
Link: https://lore.kernel.org/r/6456947.djgVdjDsCv@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Just a single update adding long waited support for SCMI firmware variant
as separate devicetrees. I wanted to deal with this differences in the
firmware interface within the bootloader for long time. But with variety
of bootloaders (u-boot, UEFI, ..etc) and need to add SCMI and SCPI
support for sake of discovery with discrepancies in shared memory layout,
it turned out difficult.
So, finally we are adding it as separate files so that we don't break
support for older SCPI firmware interface.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmIVQ7YACgkQAEG6vDF+
4piUsg/7B/d8NBgfXQ4WSVCDw7D5ekkTVSA8I1jOu084UCUCoQjJ6h9I0sMc8ALo
ikYRgF34evJP78xl+AGsU7iQfeja4i4j+5frUt9pseiQ3XW7i+kFmp/bjX9XlYFQ
HsGJ+F7oUp70W5YxfF+Ay1I9avbA6hDWqSE6gsFNVPRnVpphBzF7MvBBsTdl9CE8
ip/gTg2WEnjzdvCHyCQ9wGV8HozTtcR2Fz1WB3LaIpqToIui7gQ2KEazqTH5cJcS
xovUdM5eMdvMHsblnLDn/ET6gvFlV1AeRxUQXQTDm8tqk/3cpRzZj0EcWJy2A6OE
0BQ63bw8bwqR+JW/vbhW01PdaA6uuKhKNINuP/RtCv++/UimDyI4QgRs8MzLFUYH
2JKptVQpaeracUElKNBkOGZGhzS9p8I9smzhFyZVHucBQA0vDzOX7e2BJpLyhTJV
tnRMc+mUH6KHr97eEJxFiEVC6aI3UiaVgTjaMnEB7ED8yWa6x0bLbgX9RRhXj9W9
hNOuCMBuDhQZD86wVwUXAi2yB0UHlCNbmhEoegxaL0h7o1G0GyNB5crLMZwck4sy
CCaLUZbUaJrsFaVpv5C6/M2xhwUtf/yKDlW65EduBc6KFKiZa4c1mrE+Ft2ZqD79
bVVLlzW/lz+2YdITrbyCCbzgNyQhwp4aNqHLwlwuDsSzhSD5uZ0=
=g/zs
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8SUACgkQmmx57+YA
GNmySg//WaF+/WTHSYleBvknbsmMQjvYz9LqpQmAXlJkxqnrbORgiBVByQ9SNgKg
Pkz6j6Ex4se8KfzZUwMmdGhuN+pOWQKi3hd2YZtt4W5koTuVw9pDberafiskC7fV
IGqdYvJtDBWZdlFfE9RZAYEvFt2cAHQJEBQQiNX3cgRl+RgqZpHC8Umm/1mLAo2a
MgLRVVRkONxQN6DPtb6KOrLqWGmVo9+wDhDXHLqBQIMyHHj/fMuNOc/c98ePPUPI
Z/0Rk/z8+Bt+6lc0FtLSjljSuSphkm//5IVle8v1KKAH3Iq0cmnjFAaXRH168naa
oR4vyRFG7i+2syFHrSt5wRmsqQab99lyqwGUgNsD7+Fl+uxt53T0z2ijIDzP3aZE
SyaQxwLUMyinPhppGNG7KoK7VEMqBpYJnhrtbDO8knrQK8SjFQY0t378lUvOFGPE
orAGkNX5P8FH22zq/qsJT/ls8qQ6nC/fe/5g8tNcLqbO88hSmLd2yacRp9U1UOST
ekVZZjQeDoWukPN11fSwSvKzrzx76xohtrN4NPzH+civuwr+J36PNz6R0nI7FDp4
ngs06jZztgNs4fItCmUhVgz2cgk96VDr8AZ2Fzt9+A4sPUcZWqy1yr5aip4/vVTE
LwTvzPIiL4zWBosx0J2XaYMIPwUGtY35bYmHxavYeNPLMEgSS00=
=D501
-----END PGP SIGNATURE-----
Merge tag 'juno-update-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
Arm Juno update for v5.18
Just a single update adding long waited support for SCMI firmware variant
as separate devicetrees. I wanted to deal with this differences in the
firmware interface within the bootloader for long time. But with variety
of bootloaders (u-boot, UEFI, ..etc) and need to add SCMI and SCPI
support for sake of discovery with discrepancies in shared memory layout,
it turned out difficult.
So, finally we are adding it as separate files so that we don't break
support for older SCPI firmware interface.
* tag 'juno-update-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Add separate SCMI variants
arm64: dts: juno: Remove GICv2m dma-range
Link: https://lore.kernel.org/r/20220222201812.3338619-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New support for a number of i.MX8M Mini based boards: Protonic PRT8MM,
emCON-MX8M Mini, Toradex Verdin, Gateworks GW7903.
- A series from Adam Ford to enable GPC, USB and display support for
i.MX8M Nano.
- Enable G1 and G2 video decoder devices for i.MX8MM and i.MX8MQ.
- Enable PCIe support on imx8mm-beacon, tqma8mqml, imx8mm-evk,
imx8mq-evk and imx8mm-venice board.
- A series from Hugo Villeneuve to add PCA6416 interrupt controller
configuration, GPIO line names and i2C5 support for imx8mp-evk board.
- Correct I2C3 pad-ctrl and add internal display support for mnt-reform2
board.
- Improve fsl-ls1028a-qds overlay support by dropping syntax hard coding
and using overlay target for build.
- Add overlay support for serial modes and imx219 rpi v2 camera on
Gateworks imx8mm-venice devices.
- A set of patches from Teresa Remmet to update phyCORE-i.MX8MP SoM
device tree, including drive strength updates of different interfaces
and PMIC configuration changes.
- Device additions on various boards and some small random changes.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUi64UHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7s3Qf/TtDGP7UBFb0nnqNgNzkiQfnxsRog
iGcwwalE/Qn4Tq5ED/Sf34FOJut70fJ8chvbhqvCGkEOQPdgYOrFC8PmZw1VbKeX
5xNDihh3DAIEcGmJ89dDD5bkCepKOkyahm5c25RLzkUCOcKndoeWkzvU5bbMTs2w
8AJCrDmJ1+k5zyUXcKZlq3ySNhS4KQFD25dYGMvLy70oYhxCRtY/HLECLEStXVXs
UJ5tdwPeb4jSLi5EM9oupy4V3IGfgBSSdFCLdpXtlOTmGg5Y5rHeO1E8mFRXvigO
tCYo70SdzjLZPPxl9SUX6Ql7ShMYNZLtzmIVRn7Be2jRQ4xld9bXE4jFJw==
=iEe4
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8JAACgkQmmx57+YA
GNkUDRAAlwe2qrtugN8jUbnUIN41La5QiXOCAJYOQCosyCgAVb70ZGTIBJvOucyj
bpwU3n4hN/nppMF47jct+RRE5UcPWNF4oB7LxgEe2SdqrkUmF9/moK5XjfipCTgr
gvGln28un3mR7KS9cah3YFM/tTf749CeL5GiGx0veew39LxlYZMGA7wXIl1hJ1Tt
Vl9jzfxsrVh+lzexQBJfAbWQAE4wM5WPwDl3H/o6xZGRZPCJkuNzdmZBvnZaC5WM
ZT/R7CoeimHOV2936993MXjWkZqqZMaUBvrMGcoLYReq+0Qnht2hcETW/rHUa1+M
5nsPWSBfN8uN7jGP+qpz71eJbc8BQ/XKyximoJph9m3M1VbTNKjY1Lhq6dX2Fmyt
cutVy70TGvOEjXJOctnWf973ABBhr+NnF5m0NAJ9XGsKEGI3j3tjgYO8rpcCVnm4
AdAqSv6/HF6PQkLuT/oJu8SfHzykvZDwkh+lAP2Hfnd+Y8DEkez+c96VkvW0lqzf
TxrZIWQqrYGFPahB8rWjGzRPoLjJW6pfBEg/1iRmStMb2O+VQKzndf0DcYarrPjY
1ecrpGssvI701PP3ofwFoiOS4tGU/G955Lq8uKoT2DUVAXMOaaiGKUdxJyaMcfEr
F4BK4eLvyn/t6XDzM+7Tfj1e054bbi9GO9JZFNbGwFLCOkzHurA=
=atxP
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree change for 5.18:
- New support for a number of i.MX8M Mini based boards: Protonic PRT8MM,
emCON-MX8M Mini, Toradex Verdin, Gateworks GW7903.
- A series from Adam Ford to enable GPC, USB and display support for
i.MX8M Nano.
- Enable G1 and G2 video decoder devices for i.MX8MM and i.MX8MQ.
- Enable PCIe support on imx8mm-beacon, tqma8mqml, imx8mm-evk,
imx8mq-evk and imx8mm-venice board.
- A series from Hugo Villeneuve to add PCA6416 interrupt controller
configuration, GPIO line names and i2C5 support for imx8mp-evk board.
- Correct I2C3 pad-ctrl and add internal display support for mnt-reform2
board.
- Improve fsl-ls1028a-qds overlay support by dropping syntax hard coding
and using overlay target for build.
- Add overlay support for serial modes and imx219 rpi v2 camera on
Gateworks imx8mm-venice devices.
- A set of patches from Teresa Remmet to update phyCORE-i.MX8MP SoM
device tree, including drive strength updates of different interfaces
and PMIC configuration changes.
- Device additions on various boards and some small random changes.
* tag 'imx-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits)
arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC
arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4
arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage
arm64: dts: imx8mp-phycore-som: Update WDOG muxing
arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines
arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy
arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 camera
arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 camera
arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modes
arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modes
arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts support
arm64: dts: ls1028a: add efuse node
arm64: dts: imx8mp-evk: add support for I2C5
arm64: dts: imx8mp-evk: add PCA6416 gpio line names
arm64: dts: imx8qm: added more serial alias to dts
arm64: dts: imx8qm: add compatible string for usdhc3
arm64: dts: imx8mq-evk: Add second PCIe port support
arm64: dts: imx8mm-beacon: Enable PCIe
arm64: dts: freescale: add initial support for verdin imx8m mini
...
Link: https://lore.kernel.org/r/20220222075226.160187-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Correctly synchronise PMR and co on PSCI CPU_SUSPEND
- Skip tests that depend on GICv3 when the HW isn't available
-----BEGIN PGP SIGNATURE-----
iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAmIY1HMPHG1hekBrZXJu
ZWwub3JnAAoJECPQ0LrRPXpD4LEP/R2R5nvZwaiJIcVopzJd4ayN16bBL6qCxXWm
XsuMqdE8g/Rju3sxR/qtomDgB3GJoYpCyY28rrmVli0WBZRt9icFE1cnqUMbv5g0
Iyd+RS79LcKU6OMakAyjYX0NNwhGHr1mdD+gP8NSMny+2XWQSVcUtTVZOjSprI9L
zFNtJxPs1wfCp3WOWF668dgrBi8TsPHte2y0110+BcrY1rzJF0HXZm8YimlLakOG
Pk98dbpGMV1aKog5p9YgE3tP0oMjUcf7h+EZxuQmKF7WeFCfVg1M1xlovxRq/oEg
6KDUwUnNcDOtjUQ0pmCIPwm+rHJjlkEd+1MjZPf9L6fU0lPXmFN/DEawTh3iAsB+
xAaijEb5ImtgQgyhnDYwr5g307iXmrgSwGZKue0WOA2CTtryIXqdE02TqwZZHprm
MmAaUBUKbLGVMxd0sImsnrHUM1nNOHnD0IDEUwRLbAHOjm0u8rRK6ewV/A2O66Zz
A+AVpBZ3wd4jKkrN509d4TqomegXZQDL7hDHSgWPJDWQvOe0dFdWPJtjtamOg9Bq
+DVdXfwhQR7pHQIQbufIL+80Pgv7oBdEVSbtOJL+O+xkiSiDwHwkPdJwkB/01QMm
/f6oytJ/Kkhs+G+W6rn/bo/W1thgCBSnXntUz4qs+Cfpl4QDOIFvqMmwDdOHOzcN
9WrR6DZg
=Nyln
-----END PGP SIGNATURE-----
Merge tag 'kvmarm-fixes-5.17-4' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/arm64 fixes for 5.17, take #4
- Correctly synchronise PMR and co on PSCI CPU_SUSPEND
- Skip tests that depend on GICv3 when the HW isn't available
The architecture provides an asymmetric mode for MTE where tag mismatches
are checked asynchronously for stores but synchronously for loads. Allow
userspace processes to select this and make it available as a default mode
via the existing per-CPU sysfs interface.
Since there PR_MTE_TCF_ values are a bitmask (allowing the kernel to choose
between the multiple modes) and there are no free bits adjacent to the
existing PR_MTE_TCF_ bits the set of bits used to specify the mode becomes
disjoint. Programs using the new interface should be aware of this and
programs that do not use it will not see any change in behaviour.
When userspace requests two possible modes but the system default for the
CPU is the third mode (eg, default is synchronous but userspace requests
either asynchronous or asymmetric) the preference order is:
ASYMM > ASYNC > SYNC
This situation is not currently possible since there are only two modes and
it is mandatory to have a system default so there could be no ambiguity and
there is no ABI change. The chosen order is basically arbitrary as we do not
have a clear metric for what is better here.
If userspace requests specifically asymmetric mode via the prctl() and the
system does not support it then we will return an error, this mirrors
how we handle the case where userspace enables MTE on a system that does
not support MTE at all and the behaviour that will be seen if running on
an older kernel that does not support userspace use of asymmetric mode.
Attempts to set asymmetric mode as the default mode will result in an error
if the system does not support it.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Tested-by: Branislav Rankov <branislav.rankov@arm.com>
Link: https://lore.kernel.org/r/20220216173224.2342152-5-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Allow userspace to detect support for asymmetric mode by providing a hwcap
for it, using the official feature name FEAT_MTE3.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Tested-by: Branislav Rankov <branislav.rankov@arm.com>
Link: https://lore.kernel.org/r/20220216173224.2342152-4-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
The code isn't that obscure but it probably won't hurt to have a little
bit more documentation for anyone trying to find out where everything
actually takes effect.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Tested-by: Branislav Rankov <branislav.rankov@arm.com>
Link: https://lore.kernel.org/r/20220216173224.2342152-3-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Since all the fields in the main ID registers are 4 bits wide we have up
until now not bothered specifying the width in the code. Since we now
wish to use this mechanism to enumerate features from the floating point
feature registers which do not follow this pattern add a width to the
table. This means updating all the existing table entries but makes it
less likely that we run into issues in future due to implicitly assuming
a 4 bit width.
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220207152109.197566-4-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
CPACR_EL1 has several bitfields for controlling traps for floating point
features to EL1, each of which has a separate bits for EL0 and EL1. Marc
Zyngier noted that we are not consistent in our use of defines to
manipulate these, sometimes using a define covering the whole field and
sometimes using defines for the individual bits. Make this consistent by
expanding the whole field defines where they are used (currently only in
the KVM code) and deleting them so that no further uses can be
introduced.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220207152109.197566-3-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
The base floating point, SVE and SME all have enable controls for EL0 and
EL1 in CPACR_EL1 which have a similar layout and function. Currently the
basic floating point enable FPEN is defined differently to the SVE control,
specified as a single define in kvm_arm.h rather than in sysreg.h. Move the
define to sysreg.h and provide separate EL0 and EL1 control bits so code
managing the different floating point enables can look consistent.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220207152109.197566-2-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
- External interrupt (INTC-EX) support for the R-Car V3U SoC,
- Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and
RZ/V2L SMARC EVK development boards,
- Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle
and Condor development boards,
- NAND support for the RZ/N1D SoC,
- DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC,
- LVDS support for the R-Car M3-W+ SoC,
- HDMI output and 9-axis sensor support for the Kingfisher (ULCB
extension) board,
- MAX96712 GMSL serializer support for the Falcon development board,
- MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3
SoCs,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYgZjowAKCRCKwlD9ZEnx
cIq5AP4gwBDY8UmVVcKj9CWl+feTrHYxjFCrs/ALVcjS1EphmQEAwpK4TaqElJwb
pO2PuhfgYlCl0QwkkzYygxKFAlutjQg=
=24DK
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY5lAACgkQmmx57+YA
GNnYOg/7BXiOalLktvKGNDMKREiJ9zJXMc55NNeQzw3ne2AN6M4nuOcBiGkQiHHP
NkvQwGruOXctTJtCnk4fCTd4cu1EhSIWBUyyk4t9sBLTLm+rG9a+tGyeFKj+opjF
MvdK+EqCAeZfF/zrwvIFBSz0rbhNKje6OT8iDU1Xha2YmabXJy5T0QXerDguF1P0
jJxrENPlhEVGFyh+9ObqgGCsMdRAnNeHyIgrg+nqdys7k4+PKtwopdyC6sb8cH6t
ok2zPAJuStGsW8USA5afhLU4qrL9kCEMH0tDWq2RdN27EYVJGAnp0O2Yxa20cxLh
pMNZ70KfvkbQkv2nf+ZyMEB5z27JR6hk9GJcKit3y4VCa6gIQfBxlVFBHqJD1q4f
ugQDV/pRH/KSktd/9XHcPf6yD8njpfqpZtBLFY5AlG6xns6oImHmwM+3Dp4Glsh5
5oAh8fp6BOKiqZt7lc24h1HJZB6G8FyWhhuRaTNYfLdX66GTrAkq5BvclKvLzbsj
SbW7o8zKNLeYPbNyC4jYt6/e5MWGhg2SFHv3Aa8N919n1MjfRumn1KbjrAeMU1zu
fYh3EzMclBKKL+cOwVfb14tbE0OnpB8XJ6ipPWiCIQ9E8WeGhEsyDoFUivNt0IPN
t3dGAuTUqKC0PRF2kJ1ct5pni03G2B0iiQopTQxB8Ca5dMUQ0S8=
=YRMA
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.18
- External interrupt (INTC-EX) support for the R-Car V3U SoC,
- Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and
RZ/V2L SMARC EVK development boards,
- Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle
and Condor development boards,
- NAND support for the RZ/N1D SoC,
- DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC,
- LVDS support for the R-Car M3-W+ SoC,
- HDMI output and 9-axis sensor support for the Kingfisher (ULCB
extension) board,
- MAX96712 GMSL serializer support for the Falcon development board,
- MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3
SoCs,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits)
arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection
arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1
arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board
arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings
arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform
arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform
arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
arm64: dts: renesas: ulcb/ulcb-kf: switch to use audio-graph-card2 for sound
arm64: dts: renesas: rcar-gen3: Add MOST devices
arm64: dts: renesas: Miscellaneous whitespace fixes
arm64: dts: renesas: falcon-csi-dsi: Add and connect MAX96712
arm64: dts: renesas: ulcb-kf: Add 9-asix sensor device
arm64: dts: renesas: ulcb-kf: Add KF HDMI output
arm64: dts: renesas: r8a77961: Add lvds0 device node
arm64: dts: renesas: r8a779f0: Add sys-dmac nodes
ARM: dts: r9a06g032: Describe the NAND controller
arm64: dts: renesas: Add GMSL cameras .dtsi
...
Link: https://lore.kernel.org/r/cover.1644587200.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Conversion of Samsung pinctrl bindings to dtschema followed up with
alignment of DTS files to the dtschema.
The entire work consists of three parts but everything should be merged
at once to avoid dtschema check errors:
1. Samsung pinctrl driver change necessary to accept new DTS (driver
depends on node names and this has to be adjusted because of dtschema).
2. Conversion to dtschema which brings requirement of different naming
of the GPIO nodes.
3. DTS commits depending on driver (1) above, which convert all GPIO pin
bank names to new naming, required by dtschema.
This also includes few cleanups around DTS which are here to avoid
any merge conflicts.
The Samsung pinctrl driver changes are backwards compatible. However
the DTS changes (renaming nodes) could cause problems in out-of-tree or
other project implementations of the driver.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmH1KTEQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD11PfD/4tFiY40inEHZIjWSrIB/D3RZhVzslSeT2d
bABVtync3w0gTQZpT/E06XtSGrxLFh0hEa9ZJp94whiSFQ8xO8ziJONdp7T0zkzM
cJNufT5bsROGIhlnqX7FjZVyuqTKla1Uch5BwLbC1+0jeNFeic6tUXyWgk+ds0Dh
mmyKNNNpPW0kU5PTmk2rHxK171JCS7id4mpGCujqvMaBPB4RXHQJ/qjV/3e0QvmY
eReX+QVeMyeGg0UcFvxaVVT1Nw5TgFRzA9cOaIJ/JXbi/Jp7PagkvB6ZHk7smR7V
dxnPyQoASx41NPNRifVLUFmsGfrBzMO22JYHEzu0P7effbMLxDZoTU1lsBXWLDad
q7zWf9OpEK3hEwVM7vSwPZpLH14P7MqKvaDYEW1OdbC2zW3wT5McodUhCAdHsCxx
0iCmWxoOV8JyP8MbmW2I5o5Nw7lUW8hKg5KGYnUK6DLFDCkn8OP1XA+pnwr50H4t
FqGjKdLAjddId8KIEI+FO5O59kpPm082B71rpR/97D4nOaPOWfvv9NDRcwXbmkOv
nUPM/By6XwXo8NfdU/rcwJDGwDv1fe+nNVDU0aKXNLVhpGO3dkR6l14VQsQrsH2E
Dd4Hmio3HBClLGREkCbl0+5H9+a+ACOQ11XJlXmmHJkwb5SzmM2CYQRNxE6NxArd
3s63FKVA1w==
=aFcq
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY5fwACgkQmmx57+YA
GNn37xAAiwrsEdyqDFerNB/JVUJRLlw93TY6PojPnsj60x98UfeJbcgPeEUjYNPk
hl3HIOtpyrHom1UmqJXFROKSNq+S/rwfOJS67uwtYBgM7YwU3KCHVIeJbT1Pzwzm
dE80TSX1nolTFctCsI90mQzN72tRJbQZhvz8vP7FlkOLDe7YFIjy1j5gGify+d4J
M1YnMRVSCEA4Ba7bggQL7RWfhLzwkT4lEYLRkSGpH0kGmnW/2s+4iCxDMTqfjufF
NYP+3ctDmXfReDInkvdVHHT/F5f04C0r6JO+S7+Hvo0SJAE1zPAsNcST/dkE9hsQ
0W8VP3+EviU/k9Gmd3fPBfzX0zWzeEIaQwn3i9XVkIE4QGgXcwNOTksWgBAqyRj7
Bc6qNLmFK79dLIavRp1jmZzdDpK8yLHrVhcQjppmBBHcjW6BdBf7LN6ZYjr65qlo
ecITWLzkVLOL7iTGlLvgU1NYKUKpOJ98w2a86DbX3iAg1m1o0i0pABGCQurpUdKJ
od1y8o+xMT3+zEyK+K/Rx+ugXny1nm08qbkaApJu0yKaS5c0UhTQWPqrqvZfe+Jp
Am2KPG4EM+dDaUOj5MSItt4DeyBWQqmdLGiPJbxrVK9rmYW7CO3CotwOJU2E3St7
0dv7wRkfmuwbEt9BF9ITuNjLUXM60eR94IJV345QVxi6lVYg6ho=
=CjdH
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung pinctrl DTS and driver changes for v5.18
Conversion of Samsung pinctrl bindings to dtschema followed up with
alignment of DTS files to the dtschema.
The entire work consists of three parts but everything should be merged
at once to avoid dtschema check errors:
1. Samsung pinctrl driver change necessary to accept new DTS (driver
depends on node names and this has to be adjusted because of dtschema).
2. Conversion to dtschema which brings requirement of different naming
of the GPIO nodes.
3. DTS commits depending on driver (1) above, which convert all GPIO pin
bank names to new naming, required by dtschema.
This also includes few cleanups around DTS which are here to avoid
any merge conflicts.
The Samsung pinctrl driver changes are backwards compatible. However
the DTS changes (renaming nodes) could cause problems in out-of-tree or
other project implementations of the driver.
* tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits)
arm64: dts: exynos: use dedicated wake-up pinctrl compatible in ExynosAutov9
ARM: dts: s5pv210: align pinctrl with dtschema
ARM: dts: s3c64xx: align pinctrl with dtschema
ARM: dts: s3c24xx: align pinctrl with dtschema
arm64: dts: exynos: align pinctrl with dtschema in ExynosAutov9
arm64: dts: exynos: align pinctrl with dtschema in Exynos7
arm64: dts: exynos: align pinctrl with dtschema in Exynos5433
ARM: dts: exynos: align pinctrl with dtschema in Exynos542x/5800
ARM: dts: exynos: align pinctrl with dtschema in Exynos5410
ARM: dts: exynos: align pinctrl with dtschema in Exynos5260
ARM: dts: exynos: align pinctrl with dtschema in Exynos5250
ARM: dts: exynos: align pinctrl with dtschema in Exynos4412
ARM: dts: exynos: align pinctrl with dtschema in Exynos4210
ARM: dts: exynos: align pinctrl with dtschema in Exynos3250
ARM: dts: s3c64xx: drop unneeded pinctrl wake-up interrupt mapping
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pi
ARM: dts: exynos: override pins by label in Peach Pi
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pit
ARM: dts: exynos: override pins by label in Peach Pit
ARM: dts: exynos: simplify PMIC DVS pin configuration in Odroid XU
...
Link: https://lore.kernel.org/r/20220129115352.13274-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry
and defconfig change. This brings and enables this new platform.
This includes clock controller bindings (header files with clock IDs)
which are shared also with Tesla FSD SoC clock controller pull request.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmH9SB0QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1zpnD/9xV+X85LiKRWWuYeDtLBOzwuqCKAEVBX+U
ZVGEuS675Ha4RrskEOWHBqxBePV7dposFaBWv59wGlnTESrz4N5jtdQu8WJYatp0
WzTTpgdmQBldKHjS1xtEBK7aZ3UOfvGEEGh+dkIX8U+DxdSzfil10XpnLeplOLUs
pzpb8YdwSKX4VwRTRNuZpthN/VKTcIykANvm+DbKEl8F5kFjHWrlPFgU11XmLzZp
ngzB2AeNHWqSjDJR/JZjbjlF7SsFCbfVTYBVLVoiiHKDVgpds6rM1LiR9OjY9skp
W8egM8q2tO7mVNdFnNEK1k/CaioJUgBhEFUdxycR8Q0YoJP2dRnvQ3kEEI30suGY
EoNULUyLLa61yMIgzQ8RF8RBo/Pb9lJDvr4DyG8InDANr9Y9bLHqi4Rmm4h6BJYb
Y5cEhorY8qCmxBvllj9PdjCO0e1FanxO+RsVBgzDw3iBo6mrGXdFy1CppZ3BUSI1
NcNc5D5TRIkSo8JU9gFe+bVCjI2h1QQkZFERraH2f801wKQi7kD7/c8TE2KQR6Ej
uz7BRA9cIlE2tDqzWVtmSM+ida5c8CsTGknk1aWKM6cwGB5wM6JhHnJfg4mBUGZj
BCdUmRfqRYX4+2E01YyUjbqjbSGxYkvyPPw9LBr2ii3di4G7FInwfyrvD4O7IBBL
UUn0MFjD3w==
=tXfh
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY47wACgkQmmx57+YA
GNnklg/8CNnZyxSIOo258Bixbpf7ArNIVXuwd2mDUQO5w/dt6/y1HPErk1x/FJO5
u4x3ugyCOJOPXnZy/We38M1NXJI7+RWfkvnHObGGLqsHf6YPICEUZqAlVuAT0fJn
eWGTD1XOmf3m7r6xpSn8W6dxZ31tU/ST3WcecSBEcX4URJULdtF5Umqyh7RXTjYL
HX3QvJwKxeNCnIUbsPJK7Iq0Y77AFgzPpn7iSO4qiP5lAK+YWRuT8jQKaIOGKJxz
lw5rkYhq8pQD0Amlm/DYxrvfJJZEU83FEzMxx9ZmeeU3LoixVvWgA2H0phjZP03k
0sbshjOhUSLFIfduk1oZSbkYxQAsDsF8r1Jvrbr5LrVI+2C7vQoqTwG+neaqksnp
CmNYDvAhugdVGHBGZTeQzeVMq8swV5o+3DJtlnKPp6gXlrJjFOECE63F4f1Pc+Fi
CE9KRBLqFSrdHyAfi3bwAcS8tTnhRYx6I6NYjCp+qa4wEREw8X8HBLDRemWsoqB2
T19W864mkGPPbkmxaf5/F9LcJNU8tSd86E3hSIn1fgusEKTkv50KaEZ0GrLV45ou
GYTAYfIVRG+9RZpQOlmHPMAJ2DIoHB1EXrvPmD73Tyrgo3sZhftClNkikZKbDGDp
XplUjSnClvsUBe4cbO4zVw/s7wQwIe8x+CEl/3Ry2L6MV/fysMY=
=l8Oq
-----END PGP SIGNATURE-----
Merge tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Tesla FSD ARM64 changes for v5.18
Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry
and defconfig change. This brings and enables this new platform.
This includes clock controller bindings (header files with clock IDs)
which are shared also with Tesla FSD SoC clock controller pull request.
* tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: fsd: Add SPI device nodes
arm64: defconfig: Enable Tesla FSD SoC
arm64: dts: fsd: Add initial pinctrl support
arm64: dts: fsd: Add initial device tree support
dt-bindings: clock: Document FSD CMU bindings
dt-bindings: clock: Add bindings definitions for FSD CMU blocks
dt-bindings: arm: add Tesla FSD ARM SoC
dt-bindings: add vendor prefix for Tesla
Link: https://lore.kernel.org/r/20220204154112.133723-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
On ELF, (NOLOAD) sets the section type to SHT_NOBITS[1]. It is conceptually
inappropriate for .plt and .text.* sections which are always
SHT_PROGBITS.
In GNU ld, if PLT entries are needed, .plt will be SHT_PROGBITS anyway
and (NOLOAD) will be essentially ignored. In ld.lld, since
https://reviews.llvm.org/D118840 ("[ELF] Support (TYPE=<value>) to
customize the output section type"), ld.lld will report a `section type
mismatch` error. Just remove (NOLOAD) to fix the error.
[1] https://lld.llvm.org/ELF/linker_script.html As of today, "The
section should be marked as not loadable" on
https://sourceware.org/binutils/docs/ld/Output-Section-Type.html is
outdated for ELF.
Tested-by: Nathan Chancellor <nathan@kernel.org>
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Fangrui Song <maskray@google.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20220218081209.354383-1-maskray@google.com
Signed-off-by: Will Deacon <will@kernel.org>
cpu_has_fwb() is supposed to warn user is following architectural
requirement is not valid:
LoUU, bits [29:27] - Level of Unification Uniprocessor for the cache
hierarchy.
Note
When FEAT_S2FWB is implemented, the architecture requires that
this field is zero so that no levels of data cache need to be
cleaned in order to manage coherency with instruction fetches.
LoUIS, bits [23:21] - Level of Unification Inner Shareable for the
cache hierarchy.
Note
When FEAT_S2FWB is implemented, the architecture requires that
this field is zero so that no levels of data cache need to be
cleaned in order to manage coherency with instruction fetches.
It is not really clear what user have to do if assertion fires. Having
assertions about the CPU design like this inspire even more assertions
to be added and the kernel definitely is not the right place for that,
so let's remove cpu_has_fwb() altogether.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Link: https://lore.kernel.org/r/20220224164739.119168-1-vladimir.murzin@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
* kvm-arm64/psci-1.1:
: .
: Limited PSCI-1.1 support from Will Deacon:
:
: This small series exposes the PSCI SYSTEM_RESET2 call to guests, which
: allows the propagation of a "reset_type" and a "cookie" back to the VMM.
: Although Linux guests only ever pass 0 for the type ("SYSTEM_WARM_RESET"),
: the vendor-defined range can be used by a bootloader to provide additional
: information about the reset, such as an error code.
: .
KVM: arm64: Remove unneeded semicolons
KVM: arm64: Indicate SYSTEM_RESET2 in kvm_run::system_event flags field
KVM: arm64: Expose PSCI SYSTEM_RESET2 call to the guest
KVM: arm64: Bump guest PSCI version to 1.1
Signed-off-by: Marc Zyngier <maz@kernel.org>
The arm,armv8-pmuv3 compatible string is meant to be used only for
software models and not silicon chips. Drop them and use silicon-
specific compatible strings instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
QARMA3 is relaxed version of the QARMA5 algorithm which expected to
reduce the latency of calculation while still delivering a suitable
level of security.
Support for QARMA3 can be discovered via ID_AA64ISAR2_EL1
APA3, bits [15:12] Indicates whether the QARMA3 algorithm is
implemented in the PE for address
authentication in AArch64 state.
GPA3, bits [11:8] Indicates whether the QARMA3 algorithm is
implemented in the PE for generic code
authentication in AArch64 state.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220224124952.119612-4-vladimir.murzin@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
In preparation of supporting PAuth QARMA3 architected algorithm mark
existing one as QARMA5, so we can distingwish between two.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220224124952.119612-3-vladimir.murzin@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
In case, both boot_val and sec_val have value below min_field_value we
would wrongly report that address authentication is supported. It is
not a big issue because we enable address authentication based on boot
cpu (and check there is correct).
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220224124952.119612-2-vladimir.murzin@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Add a device node for the Pin Function Controller on the Renesas R-Car
S4-8 (R8A779F0) SoC.
Note that the register block does not include registers for banks 4-7,
as they can only be accessed from the Control Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/cf4d261ba1253879e117f1598b9f47798cbda635.1645458249.git.geert+renesas@glider.be
Rework for_each_mte_vma() to use a VMA iterator instead of an explicit
linked-list. This will allow easy integration with the maple tree work
which removes the VMA list altogether.
Signed-off-by: Liam R. Howlett <Liam.Howlett@oracle.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220218023650.672072-1-Liam.Howlett@oracle.com
[will: Folded in fix from Catalin]
Link: https://lore.kernel.org/r/YhUcywqIhmHvX6dG@arm.com
Signed-off--by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Define DT node for UART clock "marvell,armada-3700-uart-clock" and use
this UART clock as a base clock for all UART devices.
Reviewed-by: Marek Behún <kabel@kernel.org>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Link: https://lore.kernel.org/r/20220219152818.4319-7-kabel@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
There are no remaining callers of set_fs(), so CONFIG_SET_FS
can be removed globally, along with the thread_info field and
any references to it.
This turns access_ok() into a cheaper check against TASK_SIZE_MAX.
As CONFIG_SET_FS is now gone, drop all remaining references to
set_fs()/get_fs(), mm_segment_t, user_addr_max() and uaccess_kernel().
Acked-by: Sam Ravnborg <sam@ravnborg.org> # for sparc32 changes
Acked-by: "Eric W. Biederman" <ebiederm@xmission.com>
Tested-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com> # for arc changes
Acked-by: Stafford Horne <shorne@gmail.com> # [openrisc, asm-generic]
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
There are many different ways that access_ok() is defined across
architectures, but in the end, they all just compare against the
user_addr_max() value or they accept anything.
Provide one definition that works for most architectures, checking
against TASK_SIZE_MAX for user processes or skipping the check inside
of uaccess_kernel() sections.
For architectures without CONFIG_SET_FS(), this should be the fastest
check, as it comes down to a single comparison of a pointer against a
compile-time constant, while the architecture specific versions tend to
do something more complex for historic reasons or get something wrong.
Type checking for __user annotations is handled inconsistently across
architectures, but this is easily simplified as well by using an inline
function that takes a 'const void __user *' argument. A handful of
callers need an extra __user annotation for this.
Some architectures had trick to use 33-bit or 65-bit arithmetic on the
addresses to calculate the overflow, however this simpler version uses
fewer registers, which means it can produce better object code in the
end despite needing a second (statically predicted) branch.
Reviewed-by: Christoph Hellwig <hch@lst.de>
Acked-by: Mark Rutland <mark.rutland@arm.com> [arm64, asm-generic]
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Stafford Horne <shorne@gmail.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64 has an inline asm implementation of access_ok() that is derived from
the 32-bit arm version and optimized for the case that both the limit and
the size are variable. With set_fs() gone, the limit is always constant,
and the size usually is as well, so just using the default implementation
reduces the check into a comparison against a constant that can be
scheduled by the compiler.
On a defconfig build, this saves over 28KB of .text.
Acked-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Nine architectures are still missing __{get,put}_kernel_nofault:
alpha, ia64, microblaze, nds32, nios2, openrisc, sh, sparc32, xtensa.
Add a generic version that lets everything use the normal
copy_{from,to}_kernel_nofault() code based on these, removing the last
use of get_fs()/set_fs() from architecture-independent code.
Reviewed-by: Christoph Hellwig <hch@lst.de>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Drop reset signal from i.MX8MM vpumix power domain to fix a system
hang.
- Fix a dtbs_check warning caused by #thermal-sensor-cells in i.MX8ULP
device tree.
- Fix a clock disabling imbalance in gpcv2 driver.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmITP40UHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7nFggAgiDRNWaiDNZMbWBEGLWyd+TGWuMi
JiXF4h3Ic1UwOPzxcuNkpXGlwdiGdEISf5favuJmVuounlphgWDZaiy7odMyIOFV
/3NXpzSowJJYgZMOLxySiOdIVdCU0R8VsyjzWNqsv7ICCosPKOVNa8FjhjjP1XS7
eiyGcrqw675GZNS7HqOwuOrY/F9jbx1h2uUpea14iaOulqVHAPawSvg93Y6YjMJ7
WWcIUELeyOfcx3cDlmyeLEDDMi8gXdx4rvvtjmgn6w+nBAwGwgRjisReEvdJfK7u
hpyTubCilsrIDC/zsV0iIfrKOVoM66jVjSCSho7KZI2OVVtsneVLmjYXkw==
=I6Wh
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIX/aQACgkQmmx57+YA
GNmf0w/9Hptkyce9hHHbGz/kxmBnUmRPZNqUd8mlzeESr7MjTP7XyI7CnHEWj/LR
/vUgs91/HZDIQWa0U/VZAHidCygJImoNENHuzJekimxJ9hdzM6BC7BY2qGtqAl3w
WgvbJ0H0zvZTLDQotlz+KwiS8R+m6QEbIeIOuL49CLL4N23jkym+IDU3YlPbhJkr
91hXDREymLKL26Iv3kb7VXyfpmwU1dZk633uDnMCQUtiSgTV22QRPMxr1bhKVi10
UuUDYrfoTYv5i7660UFbkwu509uh4zwWgONuDYO+nUocu+NJAFA76Y/Z7QQkiPg8
3J0Y22b8AK5WVrCpv9YAbQKTjMSYYY+Muwhu4+D9cLORVOD5VVK7ZLxG/iUnItsB
JGUxx8ZZkDBQnexnmbkjDfJprVXrV7tAQcZfehk7Sf8wNUyYTKDuCnj3+gag7teU
qVEBXe3M7np+YsdnY70UvNKGcTmUoQzx+rdFHH5S/67kgegR1Zxle6ynn1Cmtrs/
zOTZI01YGMZZWr8Iaa7rvzila0AKR0c0CgqEnTVg5p4/iLWaRmzDrOJk7pJjFso1
a3vmjsCvTyVRqYoddB2iqwKRqXdUr7djTvlHkI7hrX25BoKW0NaH36RBW8tUrSJt
Pe6OjJ68NcqblbK2DNgMUSvSigjcWFk8Y3lAYKeGBHVJUYqP7Uo=
=i8PD
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.17, round 2:
- Drop reset signal from i.MX8MM vpumix power domain to fix a system
hang.
- Fix a dtbs_check warning caused by #thermal-sensor-cells in i.MX8ULP
device tree.
- Fix a clock disabling imbalance in gpcv2 driver.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
board, fix emmc signal-integrity and usb OTG mode on rk3399-puma as well
as a number of dtschema fixes to make the reduce the number of errors.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmIUy+0QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgR7lB/4yyzzeEiUrQg4ffNVFX8OJ/97ExE2C+7SX
/dHtlHZ5W7XMRx7gL/6hXne2rXWYW8BTk0nA0Hn0vuvbV96kfwbydb2I76aNrAkB
eT/wGaTFhnT5v+Cmx3krrk9vxDL2kRli2A5/SefJUvnUGufS294OAgkLspa9hfMf
QsBd0hGjt4WC/OIZYCukvhmaco9K0wGoUxrcuRRVY0lBuxvUZ4sjpZTiHNfeYhE1
zRA7OsH4KdW3wd3VvC2GnVfJQLpThKw+FuolHF4XIYpqegXxddYbXZAlysk0zyxS
Hz2XnO84xP8AnXCBo++VYU4EhjJOwGQO5rjZXpP2Dk5A21/nKux0
=9LO/
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIX/NQACgkQmmx57+YA
GNnR4xAAu9BxCqmCpFIiPm3hL6zutuJc0xMm8L3CPkDFBLSNvFBD8xNZbpbAdaGJ
U3DBtyWZ8nrQ4jQvx54SGPHKOe4vma4CuwYNwSwGX6z4XJxhdP36tjph9xsdwWH4
QFS07001kIDI/FNreurMunWWrgkkeD2cr+D/jGYLLrkTIuBqZG2OFAuARrChRElI
f4ZAWowCAOEYgKQqh/ofKber1w6DcyCw0Y3Ze4Ud3Tuk81PISLiSE4enD4DRjtxg
Lxbin0akbNM38nq6AXzsiZ38LhNjUq1pgSNyVj9ZReGcPbpHAqYMOENTrlGZrJGc
wjbPzpvDHt0kbG88f63PZcDk9HHnRTyX0I/PjG3heYjb+2xaChOZABypEv7CPPMH
hxm7Pgq8H6Y8VQymD7WmKssMyQgl81Evj0GHS+DJ6DXSln4AssWH2eKpavAfcuyF
W1afdoYWzOH2B9aw6MEaUBeUOsZ0DVqYWEnX5kZVfn5fdlcp0gGjWSZzH+VmwgT8
efUGz9ffapfMmKA6Vt7Ls8B31bSmLzBA/qmCpQ1Sk1MNQxa/md2i8U0d3NU1wqr3
8MNJkMLAD38fAiVaQ+1sNXzI69Ud5BlVY/+UAfBcv58VyEILFiNH1V9FgcR1HzkF
j9n8Bdo9X4HY33xfQGgnp8+9g6QwoVxIycpjjbXPBVGTkFoN7tQ=
=0DE7
-----END PGP SIGNATURE-----
Merge tag 'v5.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Fix the display-port-sound on Gru devices, DDR voltage on the Quartz-A
board, fix emmc signal-integrity and usb OTG mode on rk3399-puma as well
as a number of dtschema fixes to make the reduce the number of errors.
* tag 'v5.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: fix a typo on rk3288 crypto-controller
ARM: dts: rockchip: reorder rk322x hmdi clocks
arm64: dts: rockchip: reorder rk3399 hdmi clocks
arm64: dts: rockchip: align pl330 node name with dtschema
arm64: dts: rockchip: fix rk3399-puma eMMC HS400 signal integrity
arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage
arm64: dts: rockchip: Switch RK3399-Gru DP to SPDIF output
arm64: dts: rockchip: fix rk3399-puma-haikou USB OTG mode
arm64: dts: rockchip: drop pclk_xpcs from gmac0 on rk3568
arm64: dts: rockchip: fix dma-controller node names on rk356x
Link: https://lore.kernel.org/r/1973741.CViHJPHrxy@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add device tree for the Fairphone 3 smartphone which is based on
Snapdragon 632 (sdm632).
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-11-luca@z3ntu.xyz
Snapdragon 632 is based on msm8953 with some minor differences, mostly
in the CPUs.
SDM632 is using Kryo 250 instead of ARM Cortex A53 and has some
differences in the thermal zones, mainly there being only one thermal
zones for the first 4 cores (efficiency cores) but keeps one thermal
zone per core for the remaining 4 cores (performance cores).
Co-developed-by: Gabriel David <ultracoolguy@disroot.org>
Signed-off-by: Gabriel David <ultracoolguy@disroot.org>
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-9-luca@z3ntu.xyz
Add a base DT for PM8953 PMIC, commonly used with MSM8953.
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Rayyan Ansari <rayyan@ansari.sh>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220220201909.445468-8-luca@z3ntu.xyz
L8150 uses LTR559 as a light and proximity sensor. Add it to the
devicetree.
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220219145140.84712-1-nikita@trvn.ru
dtschema expects PWM node name to be a generic "pwm". This also matches
Devicetree specification requirements about generic node names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220214081916.162014-4-krzysztof.kozlowski@canonical.com
This commit enables USB device mode at J5 micro-B USB port of Jetson
Xavier NX.
Signed-off-by: Wayne Chang <waynec@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
On P3737 board, UART-A is available on 40-pin header. Enable UART-A for
P3737 and change the compatible string to "nvidia,tegra194-hsuart". This
allows supporting HW flow control and is the preferred choice for higher
baud rates.
Signed-off-by: kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add HDA device tree node for Tegra234 chip and for Jetson AGX Orin
platform.
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the '-@' DTC option for the Jetson TX1, Jetson Nano, Jetson TX2,
Jetson TX2 NX, Jetson AGX Xavier, Jetson Xavier NX and Jetson AGX Orin
platforms. This option populates the '__symbols__' node that contains
all the necessary symbols for supporting device-tree overlays on these
platforms. These Jetson platforms have various expansion headers,
including a 40-pin GPIO header, that allow various add-on modules to be
connected and this permits users to create device-tree overlays for
these modules.
Please note that this change does increase the size of the resulting DTB
from between 30-50%. For example, with v5.17-rc1 increase in size is as
follows:
tegra210-p2371-2180.dtb: 79580 -> 105744 bytes
tegra210-p3450-0000.dtb: 57465 -> 81357 bytes
tegra186-p2771-0000.dtb: 64763 -> 99553 bytes
tegra186-p3509-0000+p3636-0001.dtb: 48078 -> 62464 bytes
tegra194-p2972-0000.dtb: 75303 -> 111545 bytes
tegra194-p3509-0000+p3668-0000.dtb: 74762 -> 111995 bytes
tegra194-p3509-0000+p3668-0001.dtb: 74578 -> 111748 bytes
tegra234-p3737-0000+p3701-0000.dtb: 11229 -> 12917 bytes
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add audio-graph based sound card support on Jetson AGX Orin
platform. The sound card binds following modules:
* I/O interfaces such as I2S and DMIC (to be specific I2S1,
I2S2, I2S4, I2S6 and DMIC3 instances).
* HW accelerators such as MVC, SFC, AMX, ADX and Mixer (all
the available instances).
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add following devices which are part of APE subsystem
* ACONNECT, AGIC and ADMA
* AHUB and children (ADMAIF, I2S, DMIC, DSPK, MVC, SFC,
AMX, ADX and Mixer)
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The ADMAIF node represents the device that accesses memory in the Tegra
audio subsystem, so that's where the iommus and interconnects properties
should reside. Move them out of the sound card node and into the ADMAIF
node to properly reflect the memory data path.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA Tegra234 SoC comes with one single-instance ARM SMMU used by
isochronous memory clients and two dual-instance ARM SMMUs used by non-
isochronous memory clients.
Add the corresponding device tree nodes and hook up existing memory
clients (SDHCI and BPMP).
Signed-off-by: Thierry Reding <treding@nvidia.com>
Expose power, force-recovery and sleep buttons via a gpio-keys device so
that userspace can receive events from them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Future CPUs may implement a clearbhb instruction that is sufficient
to mitigate SpectreBHB. CPUs that implement this instruction, but
not CSV2.3 must be affected by Spectre-BHB.
Add support to use this instruction as the BHB mitigation on CPUs
that support it. The instruction is in the hint space, so it will
be treated by a NOP as older CPUs.
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
KVM allows the guest to discover whether the ARCH_WORKAROUND SMCCC are
implemented, and to preserve that state during migration through its
firmware register interface.
Add the necessary boiler plate for SMCCC_ARCH_WORKAROUND_3.
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Speculation attacks against some high-performance processors can
make use of branch history to influence future speculation.
When taking an exception from user-space, a sequence of branches
or a firmware call overwrites or invalidates the branch history.
The sequence of branches is added to the vectors, and should appear
before the first indirect branch. For systems using KPTI the sequence
is added to the kpti trampoline where it has a free register as the exit
from the trampoline is via a 'ret'. For systems not using KPTI, the same
register tricks are used to free up a register in the vectors.
For the firmware call, arch-workaround-3 clobbers 4 registers, so
there is no choice but to save them to the EL1 stack. This only happens
for entry from EL0, so if we take an exception due to the stack access,
it will not become re-entrant.
For KVM, the existing branch-predictor-hardening vectors are used.
When a spectre version of these vectors is in use, the firmware call
is sufficient to mitigate against Spectre-BHB. For the non-spectre
versions, the sequence of branches is added to the indirect vector.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Convert all device tree xo_board users to the RPM_SMD_BB_CLK1 clock.
Note, that xo_board can not be removed (yet), as clk-smd-rpm uses
xo_board internally as the parent for all the clocks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220215201539.3970459-6-dmitry.baryshkov@linaro.org
Add dmas property for spi@880000 and pinconf setting so that we can use
dma for this spi device. Also, add iommu properties for qup and spi.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220222041951.1185186-2-vkoul@kernel.org
dtschema expects PWM node name to be a generic "pwm". This also matches
Devicetree specification requirements about generic node names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20220214081916.162014-5-krzysztof.kozlowski@canonical.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Michael Walle