* Fix HOSTSW_OWN offset and unhide SPI group of pins on Jasper Lake
* Fix debounce configuration on Baytrail when it's turned off
* Fix default bias setting on Merrifield
The following is an automated git shortlog grouped by driver:
baytrail:
- Avoid clearing debounce value when turning it off
jasperlake:
- Fix HOSTSW_OWN offset
- Unhide SPI group of pins
merrifield:
- Set default bias in case no particular value given
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Merge tag 'intel-pinctrl-v5.10-3' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes
intel-pinctrl for v5.10-3
* Fix HOSTSW_OWN offset and unhide SPI group of pins on Jasper Lake
* Fix debounce configuration on Baytrail when it's turned off
* Fix default bias setting on Merrifield
The following is an automated git shortlog grouped by driver:
baytrail:
- Avoid clearing debounce value when turning it off
jasperlake:
- Fix HOSTSW_OWN offset
- Unhide SPI group of pins
merrifield:
- Set default bias in case no particular value given
Since commit 4b563a0666 ("ARM: imx: Remove imx21 support") the imx21
SoC is no longer supported.
Get rid of its pinctrl driver too, which is now unused.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Link: https://lore.kernel.org/r/20201110190210.29376-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H,
- Image size optimizations and code consolidations,
- Minor fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.11
- Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H,
- Image size optimizations and code consolidations,
- Minor fixes and improvements.
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.
Fixes: 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
Depends-on: 04ff5a095d ("pinctrl: baytrail: Rectify debounce support")
Depends-on: 827e1579e1 ("pinctrl: baytrail: Rectify debounce support (part 2)")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.
In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible
because it gives a good trade off between weakness and minimization of leakage
current (will be only 50 uA with the above choice).
Fixes: 4e80c8f505 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Depends-on: 2956b5d94a ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Cc: stable@vger.kernel.org
Signed-off-by: Evan Green <evgreen@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.
Fixes: 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
Depends-on: 04ff5a095d ("pinctrl: baytrail: Rectify debounce support")
Depends-on: 827e1579e1 ("pinctrl: baytrail: Rectify debounce support (part 2)")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
The only usage of sh73a0_vccq_mc0_ops is to assign its address to the
ops field in the regulator_desc struct, which is a const pointer. Make
it const to allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20201109221012.177478-1-rikard.falkeborn@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles
GPIOs, too. To reduce code size when compiling a kernel supporting only
modern SoCs, most, but not all, of the GPIO functionality is protected
by checks for CONFIG_PINCTRL_SH_FUNC_GPIO.
Factor out the remaining parts when not needed:
1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input
resp. output capabilities (SuperH and SH/R-Mobile).
2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO
pins to interrupt numbers (SH/R-Mobile).
3. sh_pfc_gpio_set_direction() configures GPIO direction, called from
the GPIO driver through pinctrl_gpio_direction_{in,out}put()
(SH/R-Mobile). Unfortunately this function cannot just be moved to
drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of
sh_pfc_pinctrl, which is internal to
drivers/pinctrl/renesas/pinctrl.c.
While code size reduction is minimal, this does help in documenting
depencies.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that
have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD)
registers, like R-Car Gen3 and RZ/G2. Update the function to handle
SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car
Gen1/Gen2 and RZ/G1.
Reduce code duplication by converting the R-Car M1A pin control driver
to use the common handler.
Note that this changes behavior in case the (invalid!) option
"bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored
silently; after this change, it is considered the same as
"bias-pull-up".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-8-geert+renesas@glider.be
The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car
M1A uses register offsets instead of register physical addresses.
This is different from the handling on other R-Car parts.
Convert the bias handling from register offsets to physical addresses.
This increases uniformity, and prepares for consolidation of the bias
handling.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-7-geert+renesas@glider.be
Shrink sh_pfc_pin_config from 8 to 2 bytes:
- The mux_set flag can be removed, as a non-zero mark value means the
same (zero = PINMUX_RESERVED is an invalid mark value),
- The gpio_enabled flag needs only a single bit,
- Mark values are small integers, and can easily fit in a 15-bit
bitfield.
This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs
array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-5-geert+renesas@glider.be
On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is
present in between the enum_id and name members of the sh_pfc_pin
structure. Get rid of this hole by sorting the structure's members by
decreasing size.
This saves up to 1.5 KiB per enabled SoC, and reduces the size of a
kernel including support for all R-Car Gen3 SoCs by more than 10 KiB.
This has no size impact on SH and arm32.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-4-geert+renesas@glider.be
This driver supports both RZ/G1[MN] and R-Car M2-W/M2-N SoCs.
Optimize pinctrl image size for RZ/G1[MN], when support for R-Car
M2-W/M2-N (R8A779[13]) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G1H and R-Car H2 SoCs.
Optimize pinctrl image size for RZ/G1H, when support for R-Car H2
(R8A7790) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G2E and R-Car E3 SoCs.
Optimize pinctrl image size for RZ/G2E, when support for R-Car E3
(R8A77990) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G2N and R-Car M3-N SoCs.
Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N
(R8A77965) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs.
Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+
(R8A7796[01]) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019132805.5996-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver supports both RZ/G2H and R-Car H3 ES2 SoCs.
Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 ES2
(R8A77951) is not enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.
In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible
because it gives a good trade off between weakness and minimization of leakage
current (will be only 50 uA with the above choice).
Fixes: 4e80c8f505 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Depends-on: 2956b5d94a ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Cc: stable@vger.kernel.org
Signed-off-by: Evan Green <evgreen@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
It appears that pin configuration for GPIO chip hasn't been enabled yet
due to absence of ->set_config() callback.
Enable it here for Intel Lynxpoint PCH.
Depends-on: 2956b5d94a ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
We have a specific constant to describe a disabled bias,
i.e. GPIWP_NONE. Use it explicitly instead of making
an assumption about its value.
While at it, move argument assignment to the switch-case
in lp_pin_config_get().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Replace the two separate calls for setting the irq handler and data with a
single irq_set_chained_handler_and_data() call.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Link: https://lore.kernel.org/r/20201108180144.28594-1-martin@kaiser.cx
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit be117ca322 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a
dependency rather then a selected config") moved the qcom pinctrl drivers
to have PINCTRL_MSM as dependency rather then a selected config, so do
this change for SDX55 pinctrl driver as well.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201111043610.177168-1-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We need a more granular distribution among funcion A
and function B for the LCD pins for the Samsung
GT-I9070. Provide some new pin groups so we can
configure this phone properly.
Link: https://lore.kernel.org/r/20201110232330.2242167-1-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Respect bias setting when comes from ACPI
The following is an automated git shortlog grouped by driver:
intel:
- Set default bias in case no particular value given
- Fix 2 kOhm bias which is 833 Ohm
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Merge tag 'intel-pinctrl-v5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes
intel-pinctrl for v5.10-2
* Respect bias setting when comes from ACPI
The following is an automated git shortlog grouped by driver:
intel:
- Set default bias in case no particular value given
- Fix 2 kOhm bias which is 833 Ohm
This patch adds support for Serval pinctrl, using the ocelot driver as
basis. It adds pinconfig support as well, as supported by the
platform.
gclement: Split from a larger patch adding support all platforms in
the same time.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/r/20201106093118.965152-5-gregory.clement@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds support for Luton pinctrl, using the ocelot driver as
basis. It adds pinconfig support as well, as supported by the
platform.
gclement: Split from a larger patch adding support all platforms in
the same time.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/r/20201106093118.965152-4-gregory.clement@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tweaks to allow pinctrl-msm code to be loadable as a module.
This is needed in order to support having the qcom-scm driver,
which pinctrl-msm calls into, configured as a module.
This requires that we tweak Kconfigs selecting PINCTRL_MSM to
also depend on QCOM_SCM || QCOM_SCM=n so that we match the
module setting of QCOM_SCM.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Kalle Valo <kvalo@codeaurora.org>
Cc: Maulik Shah <mkshah@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Saravana Kannan <saravanak@google.com>
Cc: Todd Kjos <tkjos@google.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: linux-gpio@vger.kernel.org
Link: https://lore.kernel.org/r/20201106042710.55979-2-john.stultz@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch reworks PINCTRL_MSM to be a visible option, and
instead of having the various SoC specific drivers select
PINCTRL_MSM, this switches those configs to depend on
PINCTRL_MSM.
This is useful, as it will be needed in order to cleanly support
having the qcom-scm driver, which pinctrl-msm calls into,
configured as a module. Without this change, we would eventually
have to add dependency lines to every config that selects
PINCTRL_MSM, and that would becomes a maintenance headache.
We also add PINCTRL_MSM to the arm64 defconfig to avoid
surprises as otherwise PINCTRL_MSM/IPQ* options previously
enabled, will be off.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Kalle Valo <kvalo@codeaurora.org>
Cc: Maulik Shah <mkshah@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Saravana Kannan <saravanak@google.com>
Cc: Todd Kjos <tkjos@google.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: linux-gpio@vger.kernel.org
Link: https://lore.kernel.org/r/20201106042710.55979-1-john.stultz@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Print the status of debounce filter as follows,
$ cat /sys/kernel/debug/gpio
pin129 interrupt is disabled | interrupt is masked |
disable wakeup in S0i3 state | disable wakeup in S3 state |
disable wakeup in S4/S5 state| input is high | pull-up is disabled |
Pull-down is disabled | output is disabled |
debouncing filter disabled | 0x50000
pin130 interrupt is disabled | interrupt is masked |
disable wakeup in S0i3 state | disable wakeup in S3 state |
disable wakeup in S4/S5 state | input is high | pull-up is disabled |
Pull-down is disabled | output is disabled |
debouncing filter (high) enabled |
debouncing timeout is 124800 (us)| 0x503c8
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20201105231912.69527-4-coiby.xu@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the "lcd-8bit" group to the "lcd" function.
As "lcd-24bit" is a superset of "lcd-8bit", in theory the former could
be modified to only contain the pins not already included in "lcd-8bit",
just like how it's done for the JZ4740 and JZ4725B platforms. However,
we can't do that without breaking Device Tree ABI, so in that case we
have no choice but to have two groups containing the same pins.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20201101090104.5088-3-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Abuse the pin function pointer to store the pin function value directly,
when all the pins of a group have the same function value. Now when the
pointer value is <= 3 (unsigned), the pointer value is used as the pin
function; otherwise it is used as a regular pointer.
This drastically reduces the number of pin function tables needed, and
drops .data usage by about 2 KiB. Additionally, the few pin function
tables that are still around now contain u8 instead of int, since the
largest number that will be stored is 3.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20201101090104.5088-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
mt7622 is reported by mediatek to have only 6 pwm channels
so drop pindefines for 7th channel
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/20201016204019.2606-4-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Specify the PDC mapping for SM8250, so that gpio interrupts are
propertly mapped to the wakeup IRQs of the PDC.
Fixes: 4e3ec9e407 ("pinctrl: qcom: Add sm8250 pinctrl driver.")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201028043642.1141723-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When GPIOs that are routed to PDC are used as output they can still latch
the IRQ pending at GIC. As a result the spurious IRQ was handled when the
client driver change the direction to input to starts using it as IRQ.
Currently such erroneous latched IRQ are cleared with .irq_enable callback
however if the driver continue to use GPIO as interrupt and invokes
disable_irq() followed by enable_irq() then everytime during enable_irq()
previously latched interrupt gets cleared.
This can make edge IRQs not seen after enable_irq() if they had arrived
after the driver has invoked disable_irq() and were pending at GIC.
Move clearing erroneous IRQ to .irq_request_resources callback as this is
the place where GPIO direction is changed as input and its locked as IRQ.
While at this add a missing check to invoke msm_gpio_irq_clear_unmask()
from .irq_enable callback only when GPIO is not routed to PDC.
Fixes: e35a6ae0eb ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Link: https://lore.kernel.org/r/1604561884-10166-1-git-send-email-mkshah@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
RTC is 32.768kHz thus 512 RtcClk equals 15625 usec. The documentation
likely has dropped precision and that's why the driver mistakenly took
the slightly deviated value.
Cc: stable@vger.kernel.org
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Suggested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/linux-gpio/2f4706a1-502f-75f0-9596-cc25b4933b6c@redhat.com/
Link: https://lore.kernel.org/r/20201105231912.69527-3-coiby.xu@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some gpio pin at aspeed soc is input only and the prefix name of these
pin is "GPI" only.
This patch fine-tune the condition of GPIO check from "GPIO" to "GPI"
and it will fix the usage error of banks D and E in the AST2400/AST2500
and banks T and U in the AST2600.
Fixes: 4d3d0e4272 ("pinctrl: Add core support for Aspeed SoCs")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20201030055450.29613-1-billy_tsai@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Enable pinctrl drivers for 64-bit Amlogic SoCs to be built as modules.
The default is still built-in, this only adds the option of building
as modules.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201026183025.31768-1-khilman@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It is useful for debugging to have the error message printed
when regmap initialisation fails. Add it to the driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Martin Hundebøll <martin@geanix.com>
Link: https://lore.kernel.org/r/20201009180856.4738-2-andriy.shevchenko@linux.intel.com
Tested-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It appears that simplification of mcp23s08_spi_regmap_init() made
a regression due to wrong size calculation for dev_kmemdup() call.
It misses the fact that config variable is already a pointer, thus
the sizeof() calculation is wrong and only 4 or 8 bytes were copied.
Fix the parameters to devm_kmemdup() to copy a full chunk of memory.
Fixes: 0874758ecb ("pinctrl: mcp23s08: Refactor mcp23s08_spi_regmap_init()")
Reported-by: Martin Hundebøll <martin@geanix.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Martin Hundebøll <martin@geanix.com>
Link: https://lore.kernel.org/r/20201009180856.4738-1-andriy.shevchenko@linux.intel.com
Tested-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mapping
This patch can speed up system boot on, also abandon many unused irq
mappings' create.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Link: https://lore.kernel.org/r/20201013063731.3618-4-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Link: https://lore.kernel.org/r/20201013063731.3618-3-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Like in the other Intel pin control drivers, attach initcalls
to the corresponding functions. No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This driver adds pinctrl/GPIO support for Intel Alder Lake-S SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This driver adds pinctrl/GPIO support for Intel Elkhart Lake SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Add a blank line before endif directive in Kconfig for better readability.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This driver adds pinctrl/GPIO support for Intel Lakefield SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Cc: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
The values for the SSI pins on GPIO chips D and E were off by 0x20.
Fixes: d3ef8c6b22 ("pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780.")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reported-by: Artur Rojek <contact@artur-rojek.eu>
Link: https://lore.kernel.org/r/20201010192509.9098-1-paul@crapouillou.net
Reviewed-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.
In case of Intel pin control hardware the 5 kOhm sounds plausible
because on one hand it's a minimum of resistors present in all
hardware generations and at the same time it's high enough to minimize
leakage current (will be only 200 uA with the above choice).
Fixes: e57725eabf ("pinctrl: intel: Add support for hardware debouncer")
Reported-by: Jamie McClymont <jamie@kwiius.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2 kOhm bias was never an option in Intel GPIO hardware, the available
matrix is:
000 none
001 1 kOhm (if available)
010 5 kOhm
100 20 kOhm
As easy to get the 3 resistors are gated separately and according to
parallel circuits calculations we may get combinations of the above where
the result is always strictly less than minimal resistance. Hence,
additional values can be:
011 ~833.3 Ohm
101 ~952.4 Ohm
110 ~4 kOhm
111 ~800 Ohm
That said, convert TERM definitions to be the bit masks to reflect the above.
While at it, enable the same setting for pull down case.
Fixes: 7981c0015a ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
Cc: Jamie McClymont <jamie@kwiius.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Add pins, groups and functions for the VIN1-B [data/sync/field/clkenb/clk]
and VIN2-G8.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200917195924.20384-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Core changes:
- NONE whatsoever, we don't even touch the core files this
time around.
New drivers:
- New driver for the Toshiba Visconti SoC.
- New subdriver for the Qualcomm MSM8226 SoC.
- New subdriver for the Actions Semiconductor S500 SoC.
- New subdriver for the Mediatek MT8192 SoC.
- New subdriver for the Microchip SAMA7G5 SoC.
Driver enhancements:
- Intel Cherryview and Baytrail cleanups and refactorings.
- Enhanced support for the Renesas R8A7790, more pins and
groups.
- Some optimizations for the MCP23S08 MCP23x17 variant.
- Some cleanups around the Actions Semiconductor subdrivers.
- A bunch of cleanups around the SH-PFC and Emma Mobile
drivers.
- The "SH-PFC" (literally SuperH pin function controller, I
think) subdirectory is now renamed to the more neutral
"renesas", as these are not very much centered around
SuperH anymore.
- Non-critical fixes for the Aspeed driver.
- Non-critical fixes for the Ingenic (MIPS!) driver.
- Fix a bunch of missing pins on the AMD pinctrl driver.
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Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- NONE whatsoever, we don't even touch the core files this time
around.
New drivers:
- New driver for the Toshiba Visconti SoC.
- New subdriver for the Qualcomm MSM8226 SoC.
- New subdriver for the Actions Semiconductor S500 SoC.
- New subdriver for the Mediatek MT8192 SoC.
- New subdriver for the Microchip SAMA7G5 SoC.
Driver enhancements:
- Intel Cherryview and Baytrail cleanups and refactorings.
- Enhanced support for the Renesas R8A7790, more pins and groups.
- Some optimizations for the MCP23S08 MCP23x17 variant.
- Some cleanups around the Actions Semiconductor subdrivers.
- A bunch of cleanups around the SH-PFC and Emma Mobile drivers.
- The "SH-PFC" (literally SuperH pin function controller, I think)
subdirectory is now renamed to the more neutral "renesas", as these
are not very much centered around SuperH anymore.
- Non-critical fixes for the Aspeed driver.
- Non-critical fixes for the Ingenic (MIPS!) driver.
- Fix a bunch of missing pins on the AMD pinctrl driver"
* tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits)
pinctrl: amd: Add missing pins to the pin group list
dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks
pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI
pinctrl: mediatek: Free eint data on failure
pinctrl: single: fix debug output when #pinctrl-cells = 2
pinctrl: single: fix pinctrl_spec.args_count bounds check
pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
pinctrl: tigerlake: Fix register offsets for TGL-H variant
pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2
pinctrl: mediatek: use devm_platform_ioremap_resource_byname()
pinctrl: nuvoton: npcm7xx: Constify static ops structs
pinctrl: mediatek: mt7622: add antsel pins/groups
pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register()
pinctrl: at91-pio4: add support for sama7g5 SoC
dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5
pinctrl: spear: simplify the return expression of tvc_connect()
pinctrl: spear: simplify the return expression of spear310_pinctrl_probe
pinctrl: sprd: use module_platform_driver to simplify the code
pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs.
...
Core changes:
- The big core change is the updated (v2) userspace character
device API. This corrects badly designed 64-bit alignment around
the line events. We also add the debounce request feature.
This echoes the often quotes passage from Frederick Brooks
"The mythical man-month" to always throw one away, which we
have seen before in things such as V4L2. So we put in a new
one and deprecate and obsolete the old one.
- All example tools in tools/gpio/* are migrated to the new API
to set a good example. The libgpiod userspace library has been
augmented to use this new API pretty much from day 1.
- Some misc API hardening by using strn* function calls has been
added as well.
- Use the simpler IDA interface for GPIO chip instance enumeration.
- Add device core function for counting string arrays in
device properties.
- Provide a generic library function kfree_strarray() that can
be used throughout the kernel.
Driver enhancements:
- The DesignWare dwapb-gpio driver has been enhanced and now
uses the IRQ handling in the gpiolib core.
- The mockup and aggregator drivers have seen some substantial
code clean-up and now use more of the core kernel
inftrastructure.
- Misc cleanups using dev_err_probe().
- The MXC drivers (Freescale/NXP) can now be built modularized,
which makes modularized GKI Android kernels happy.
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Merge tag 'gpio-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This time very little driver changes but lots of core changes.
We have some interesting cooperative work for ARM and Intel alike,
making the GPIO subsystem more and more suitable for industrial
systems and the like, in addition to the in-kernel users.
We touch driver core (device properties) and lib/* by adding one
simple string array free function, these are authored by Andy
Shevchenko who is a well known and recognized core helpers maintainers
so this should be fine.
We also see some Android GKI-related modularization in the MXC
drivers.
Core changes:
- The big core change is the updated (v2) userspace character device
API.
This corrects badly designed 64-bit alignment around the line
events. We also add the debounce request feature. This echoes the
often quotes passage from Frederick Brooks "The mythical man-month"
to always throw one away, which we have seen before in things such
as V4L2. So we put in a new one and deprecate and obsolete the old
one.
- All example tools in tools/gpio/* are migrated to the new API to
set a good example. The libgpiod userspace library has been
augmented to use this new API pretty much from day 1.
- Some misc API hardening by using strn* function calls has been
added as well.
- Use the simpler IDA interface for GPIO chip instance enumeration.
- Add device core function for counting string arrays in device
properties.
- Provide a generic library function kfree_strarray() that can be
used throughout the kernel.
Driver enhancements:
- The DesignWare dwapb-gpio driver has been enhanced and now uses the
IRQ handling in the gpiolib core.
- The mockup and aggregator drivers have seen some substantial code
clean-up and now use more of the core kernel inftrastructure.
- Misc cleanups using dev_err_probe().
- The MXC drivers (Freescale/NXP) can now be built modularized, which
makes modularized GKI Android kernels happy"
* tag 'gpio-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (73 commits)
gpiolib: Update header block in gpiolib-cdev.h
gpiolib: cdev: switch from kstrdup() to kstrndup()
docs: gpio: add a new document to its index.rst
gpio: pca953x: Add support for the NXP PCAL9554B/C
tools: gpio: add debounce support to gpio-event-mon
tools: gpio: add multi-line monitoring to gpio-event-mon
tools: gpio: port gpio-event-mon to v2 uAPI
tools: gpio: port gpio-hammer to v2 uAPI
tools: gpio: rename nlines to num_lines
tools: gpio: port gpio-watch to v2 uAPI
tools: gpio: port lsgpio to v2 uAPI
gpio: uapi: document uAPI v1 as deprecated
gpiolib: cdev: support setting debounce
gpiolib: cdev: support GPIO_V2_LINE_SET_VALUES_IOCTL
gpiolib: cdev: support GPIO_V2_LINE_SET_CONFIG_IOCTL
gpiolib: cdev: support edge detection for uAPI v2
gpiolib: cdev: support GPIO_V2_GET_LINEINFO_IOCTL and GPIO_V2_GET_LINEINFO_WATCH_IOCTL
gpiolib: cdev: support GPIO_V2_GET_LINE_IOCTL and GPIO_V2_LINE_GET_VALUES_IOCTL
gpiolib: add build option for CDEV v1 ABI
gpiolib: make cdev a build option
...
Core:
- Allow trimming of interrupt hierarchy to support odd hardware setups
where only a subset of the interrupts requires the full hierarchy.
- Allow the retrigger mechanism to follow a hierarchy to simplify
driver code.
- Provide a mechanism to force enable wakeup interrrupts on suspend.
- More infrastructure to handle IPIs in the core code
Architectures:
- Convert ARM/ARM64 IPI handling to utilize the interrupt core code.
Drivers:
- The usual pile of new interrupt chips (MStar, Actions Owl, TI PRUSS,
Designware ICTL)
- ARM(64) IPI related conversions
- Wakeup support for Qualcom PDC
- Prevent hierarchy corruption in the NVIDIA Tegra driver
- The usual small fixes, improvements and cleanups all over the place.
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Merge tag 'irq-core-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"Updates for the interrupt subsystem:
Core:
- Allow trimming of interrupt hierarchy to support odd hardware
setups where only a subset of the interrupts requires the full
hierarchy.
- Allow the retrigger mechanism to follow a hierarchy to simplify
driver code.
- Provide a mechanism to force enable wakeup interrrupts on suspend.
- More infrastructure to handle IPIs in the core code
Architectures:
- Convert ARM/ARM64 IPI handling to utilize the interrupt core code.
Drivers:
- The usual pile of new interrupt chips (MStar, Actions Owl, TI
PRUSS, Designware ICTL)
- ARM(64) IPI related conversions
- Wakeup support for Qualcom PDC
- Prevent hierarchy corruption in the NVIDIA Tegra driver
- The usual small fixes, improvements and cleanups all over the
place"
* tag 'irq-core-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits)
dt-bindings: interrupt-controller: Add MStar interrupt controller
irqchip/irq-mst: Add MStar interrupt controller support
soc/tegra: pmc: Don't create fake interrupt hierarchy levels
soc/tegra: pmc: Allow optional irq parent callbacks
gpio: tegra186: Allow optional irq parent callbacks
genirq/irqdomain: Allow partial trimming of irq_data hierarchy
irqchip/qcom-pdc: Reset PDC interrupts during init
irqchip/qcom-pdc: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
pinctrl: qcom: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
genirq/PM: Introduce IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
pinctrl: qcom: Use return value from irq_set_wake() call
pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags
ARM: Handle no IPI being registered in show_ipi_list()
MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller
irqchip: Add Actions Semi Owl SIRQ controller
dt-bindings: interrupt-controller: Add Actions SIRQ controller binding
dt-bindings: dw-apb-ictl: Update binding to describe use as primary interrupt controller
irqchip/dw-apb-ictl: Add primary interrupt controller support
irqchip/dw-apb-ictl: Refactor priot to introducing hierarchical irq domains
genirq: Add stub for set_handle_irq() when !GENERIC_IRQ_MULTI_HANDLER
...
Some of the pins were not exposed in the initial driver or kept as
reserved. Exposing all of them now.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20201007111220.744348-1-Shyam-sundar.S-k@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Toshiba Visconti TMPV7700 series pin controller is only present on
Visconti SoCs. Hence add a dependency on ARCH_VISCONTI, to prevent
asking the user about this driver when configuring a kernel without
Visconti platform support.
Fixes: a68a784426 ("pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Link: https://lore.kernel.org/r/20201005125049.26926-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the
wakeirqs during suspend entry.
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/1601267524-20199-5-git-send-email-mkshah@codeaurora.org
msmgpio irqchip was not using return value of irq_set_irq_wake() callback
since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor
it implemented .irq_set_wake callback. This lead to irq_set_irq_wake()
return error -ENXIO.
However from 'commit 4110b5cbb0 ("irqchip/gic-v3: Allow interrupt to be
configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE
flag.
Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent()
instead of always returning success.
Fixes: e35a6ae0eb ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/1601267524-20199-3-git-send-email-mkshah@codeaurora.org
Both IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags are already
set for msmgpio's parent PDC irqchip but GPIO interrupts do not get masked
during suspend or during setting irq type since genirq checks irqchip flag
of msmgpio irqchip which forwards these calls to its parent PDC irqchip.
Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs during
suspend and mask before setting irq type. Masking before changing type make
sures any spurious interrupt is not detected during this operation.
Fixes: e35a6ae0eb ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/1601267524-20199-2-git-send-email-mkshah@codeaurora.org
The property #pinctrl-cells can either be 1 or 2:
- if #pinctrl-cells = <1>, then pinctrl_spec.args_count = 2
- if #pinctrl-cells = <2>, then pinctrl_spec.args_count = 3
All other values of pinctrl_spec.args_count are incorrect. This fix
checks the upper bound instead of just the lower bound.
Fixes: a133954188 ("pinctrl: single: parse #pinctrl-cells = 2")
Reported-by: Trent Piepho <tpiepho@gmail.com>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/
Link: https://lore.kernel.org/r/20200930174839.1308344-1-drew@beagleboard.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
check mtk_is_virt_gpio input parameter,
virtual gpio need to support eint mode.
add error handler for the ko case
to fix this boot fail:
pc : mtk_is_virt_gpio+0x20/0x38 [pinctrl_mtk_common_v2]
lr : mtk_gpio_get_direction+0x44/0xb0 [pinctrl_paris]
Fixes: edd5464650 ("pinctrl: mediatek: avoid virtual gpio trying to set reg")
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Singed-off-by: Jie Yang <sin_jieyang@mediatek.com>
Link: https://lore.kernel.org/r/1597922546-29633-1-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Modify COMMUNITY macros to be consistent with Tiger Lake and others.
No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20200929110306.40852-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Modify COMMUNITY macros to be consistent with Tiger Lake and others.
No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20200929110306.40852-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It appears that almost traditionally the H variants have some deviations
in the register offsets in comparison to LP ones. This is the case for
Intel Tiger Lake as well. Fix register offsets for TGL-H variant.
Fixes: 653d96455e ("pinctrl: tigerlake: Add support for Tiger Lake-H")
Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20200929110306.40852-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the devm_platform_ioremap_resource_byname() helper instead of
calling platform_get_resource_byname() and devm_ioremap_resource()
separately.
Signed-off-by: Wang Xiaojun <wangxiaojun11@huawei.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/20200917064151.2184010-1-wangxiaojun11@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The only usage of these structs is to assign their address to various
ops fields in the pinctrl_desc struct, which are const pointers. Make
them const to allow the compiler to put them in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200926202342.31014-1-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for sama7g5 pinctrl block, which has 5 PIO banks.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20200917131257.273882-2-eugen.hristev@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When PINCTRL_BCM2835 is enabled and GPIOLIB is disabled, it results in the
following Kbuild warning:
WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP
Depends on [n]: GPIOLIB [=n]
Selected by [y]:
- PINCTRL_BCM2835 [=y] && PINCTRL [=y] && OF [=y] && (ARCH_BCM2835 [=n] || ARCH_BRCMSTB [=n] || COMPILE_TEST [=y])
The reason is that PINCTRL_BCM2835 selects GPIOLIB_IRQCHIP without
depending on or selecting GPIOLIB while GPIOLIB_IRQCHIP is subordinate to
GPIOLIB.
Honor the kconfig menu hierarchy to remove kconfig dependency warnings.
Fixes: 85ae9e512f ("pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP")
Signed-off-by: Necip Fazil Yildiran <fazilyildiran@gmail.com>
Link: https://lore.kernel.org/r/20200914144025.371370-1-fazilyildiran@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1.Add I2S pins support for the JZ4780 SoC.
2.Add I2S pins support for the X1000 SoC.
3.Add I2S pins support for the X1500 SoC.
4.Add I2S pins support for the X1830 SoC.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200913065836.12156-4-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Correct the pullup and pulldown parameters of JZ4780 to make them
consistent with the parameters on the datasheet.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200913065836.12156-3-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add SSI pins support for the JZ4770 SoC and the
JZ4780 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200913065836.12156-2-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These were skipped in the original patches adding pinconf support for
the AST2600.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Link: https://lore.kernel.org/r/20200910025631.2996342-4-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Aspeed pinconf data structures are split into 'conf' and 'map'
types, where the 'conf' struct defines which register and bitfield to
manipulate, while the 'map' struct defines what value to write to
the register and bitfield.
Both structs have a mask member, and the wrong mask was being used to
tell the regmap which bits to update.
A todo is to look at whether we can remove the mask from the 'map'
struct.
Fixes: 5f52c85384 ("pinctrl: aspeed: Use masks to describe pinconf bitfields")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Link: https://lore.kernel.org/r/20200910025631.2996342-3-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When displaying which pinconf register and field is being touched,
format the field mask so that it's consistent with the way the pinmux
portion formats the mask.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20200910025631.2996342-2-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Change PINCTRL_IMX to tristate to support loadable module build.
And i.MX common pinctrl driver should depend on CONFIG_OF to make sure
no build error when i.MX common pinctrl driver is enabled for different
architectures without CONFIG_OF.
Also add module author, description and license.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/1599552721-24872-3-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use function callbacks for SCU related functions in pinctrl-imx.c
in order to support the scenario of PINCTRL_IMX is built in while
PINCTRL_IMX_SCU is built as module, all drivers using SCU pinctrl
driver need to initialize the SCU related function callback, and
no need to check CONFIG_PINCTRL_IMX_SCU anymore, hence stub functions
also can be removed.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/1599552721-24872-1-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Add last part of cleanup Cherryview driver to align with other drivers
* Due to above clean up Cherryview and Baytrail drivers to use common API
The following is an automated git shortlog grouped by driver:
baytrail:
- Switch to use intel_pinctrl_get_soc_data()
cherryview:
- Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs
- Switch to use intel_pinctrl_get_soc_data()
- Utilize temporary variable to hold device pointer
- Switch to use struct intel_pinctrl
- Move custom community members to separate data struct
- Drop stale comment
intel:
- Update header block to reflect direct dependencies
- Extract intel_pinctrl_get_soc_data() helper for wider use
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Merge tag 'intel-pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.10-1
* Add last part of cleanup Cherryview driver to align with other drivers
* Due to above clean up Cherryview and Baytrail drivers to use common API
The following is an automated git shortlog grouped by driver:
baytrail:
- Switch to use intel_pinctrl_get_soc_data()
cherryview:
- Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs
- Switch to use intel_pinctrl_get_soc_data()
- Utilize temporary variable to hold device pointer
- Switch to use struct intel_pinctrl
- Move custom community members to separate data struct
- Drop stale comment
intel:
- Update header block to reflect direct dependencies
- Extract intel_pinctrl_get_soc_data() helper for wider use
- Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1,
- Three more conversion of DT bindings to json-schema,
- Group all Renesas pinctrl drivers and improve visual Kconfig
structure,
- Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas,
- Minor fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.10
- Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1,
- Three more conversion of DT bindings to json-schema,
- Group all Renesas pinctrl drivers and improve visual Kconfig
structure,
- Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas,
- Minor fixes and improvements.
One some devices the GPIO should output the inverted value from what
device-drivers / ACPI code expects. The reason for this is unknown,
perhaps these systems use an external buffer chip on the GPIO which
inverts the signal. The BIOS makes this work by setting the
CHV_PADCTRL1_INVRXTX_TXDATA flag.
Before this commit we would unconditionally clear all INVRXTX flags,
including the CHV_PADCTRL1_INVRXTX_TXDATA flag when a GPIO is requested
by a driver (from chv_gpio_request_enable()).
This breaks systems using this setup. Specifically it is causing
problems for systems with a goodix touchscreen, where the BIOS sets the
INVRXTX_TXDATA flag on the GPIO used for the touchscreen's reset pin.
The goodix touchscreen driver by defaults configures this pin as input
(relying on the pull-up to keep it high), but the clearing of the
INVRXTX_TXDATA flag done by chv_gpio_request_enable() causes it to be
driven low for a brief time before the GPIO gets set to input mode.
This causes the touchscreen controller to get reset. On most CHT devs
with this touchscreen this leads to:
[ 31.596534] Goodix-TS i2c-GDIX1001:00: i2c test failed attempt 1: -121
The driver retries this though and then everything is fine. But during
reset the touchscreen uses its interrupt pin as bootstrap to determine
which i2c address to use and on the Acer One S1003 the spurious reset
caused by the clearing of the INVRXTX_TXDATA flag causes the controller
to come back up again on the wrong i2c address, breaking things.
This commit fixes both the -121 errors, as well as the total breakage
on the Acer One S1003, by making chv_gpio_clear_triggering() not clear
the INVRXTX_TXDATA flag if the pin is already configured as a GPIO.
Note that chv_pinmux_set_mux() does still unconditionally clear the
flag, so this only affects GPIO usage.
Fixes: a7d4b17166 ("Input: goodix - add support for getting IRQ + reset GPIOs on Cherry Trail devices")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin
control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc:
Collect Renesas related CONFIGs in one place"), the code for this
framework is always built when Renesas SoC pin control support is
enabled, regardless of whether the enabled pin control drivers need it
or not.
Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion
of the "sh-pfc" framework and its dependencies, and selecting it when
needed.
This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than
6 resp. 11 KiB.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be
The drivers/pinctrl/sh-pfc subdirectory was originally created to group
pin control drivers for various Renesas SuperH and SH-Mobile platforms.
However, the name "sh-pfc" no longer reflects its contents, as the
directory now contains pin control drivers for Renesas SuperH, ARM32,
and ARM64 SoCs.
Hence rename the subdirectory from drivers/pinctrl/sh-pfc to
drivers/pinctrl/renesas, and the related Kconfig symbol from
PINCTRL_SH_PFC to PINCTRL_RENESAS.
Rename the git branch in MAINTAINERS, too, for consistency.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
The RZ/N1 pin control driver does not use pin groups or pin functions,
so there is no need to select GENERIC_PINCTRL_GROUPS or
GENERIC_PINMUX_FUNCTIONS.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200909131534.12897-2-geert+renesas@glider.be
For pins requiring software driven IO output operations, the RZ/A1 Pin
Controller uses either the "output-high" or "output-low" DT property to
enable the corresponding output buffer. The actual line value doesn't
matter, as it is ignored.
Commit 425562429d ("pinctrl: generic: Add output-enable property")
introduced a new DT property for this specific use case.
Update the RZ/A1 Pin Controller DT bindings and driver to use this new
property instead. Preserve backwards compatibility with old DTBs in the
driver, as this comes at a very small cost.
Notes:
- The DT binding examples already used the new property,
- There are no upstream users of the old properties.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Jacopo Mondi <jacopo@jmondi.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200821111401.4021-1-geert+renesas@glider.be
Now, Renesas Pin Control drivers are under menu, but current
descriptions are not aligned.
This patch aligns them.
- RZ/A2 gpio and pinctrl driver
- RZ/N1 pinctrl driver
- Emma Mobile EV2 pin control support
- R-Mobile APE6 pin control support
- R-Mobile A1 pin control support
- RZ/G1H pin control support
- RZ/G1M pin control support
+ pin control support for RZ/A2
+ pin control support for RZ/N1
+ pin control support for Emma Mobile EV2
+ pin control support for R-Mobile APE6
+ pin control support for R-Mobile A1
+ pin control support for RZ/G1H
+ pin control support for RZ/G1M
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87imd8y4r2.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Renesas related pinctrl CONFIGs are located in many places, which is
confusing.
This patch collects them into the same place, grouped in a new "Renesas
pinctrl drivers" menu.
This patch also moves pinctrl-rz{a1,a2,n1}.c into the sh-pfc folder.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87k0xoy4r7.wl-kuninori.morimoto.gx@renesas.com
[geert: Update path in MAINTAINERS]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
It is "Emma Mobile EV2" not "AV2".
This patch tidies it up.
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87lfi4y4re.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
driver_deferred_probe_check_state() may return -ETIMEDOUT instead of
-EPROBE_DEFER after all built-in drivers have been probed. This can
cause issues for built-in drivers that depend on resources provided by
loadable modules.
One such case happens on Tegra where I2C controllers are used during
early boot to set up the system PMIC, so the I2C driver needs to be a
built-in driver. At the same time, some instances of the I2C controller
depend on the DPAUX hardware for pinmuxing. Since the DPAUX is handled
by the display driver, which is usually not built-in, the pin control
states will not become available until after the root filesystem has
been mounted and the display driver loaded from it.
Fixes: bec6c0ecb2 ("pinctrl: Remove use of driver_deferred_probe_check_state_continue()")
Suggested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200825143348.1358679-1-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Per the datasheet the i2c functions use MPP_Sel=0x1. They are documented
as using MPP_Sel=0x4 as well but mixing 0x1 and 0x4 is clearly wrong. On
the board tested 0x4 resulted in a non-functioning i2c bus so stick with
0x1 which works.
Fixes: d7ae8f8dee ("pinctrl: mvebu: pinctrl driver for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20200907211712.9697-2-chris.packham@alliedtelesis.co.nz
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I encountered bug in SX1502 expander driver in 5.7.7. Here is relevant
DTS part:
compatible = "semtech,sx1502q";
gpio4_cfg_pins: gpio2-cfg {
pins = "gpio5";
output-high;
};
And part of OOPS:
[ 0.673996] [<c023cfa6>] (gpiochip_get_data) from [<c023b235>]
(sx150x_gpio_direction_output+0xd)
[ 0.683259] [<c023b235>] (sx150x_gpio_direction_output) from
[<c023b363>] (sx150x_pinconf_set+0x)
[ 0.692796] [<c023b363>] (sx150x_pinconf_set) from [<c0238fef>]
(pinconf_apply_setting+0x39/0x7e)
[ 0.701635] [<c0238fef>] (pinconf_apply_setting) from [<c0236c77>]
(pinctrl_commit_state+0xa5/0x)
[ 0.710648] [<c0236c77>] (pinctrl_commit_state) from [<c0237e03>]
(pinctrl_enable+0xff/0x1d4)
[ 0.719139] [<c0237e03>] (pinctrl_enable) from [<c023b791>]
(sx150x_probe+0x1a3/0x358)
[ 0.727027] [<c023b791>] (sx150x_probe) from [<c02c38bf>]
(i2c_device_probe+0x1bb/0x1dc)
The problem is that sx150x_pinconf_set uses sx150x_gpio_direction_output
but gpio is not setup yet. Patch below fixes it but I'm not sure whether
is it correct.
Link: https://lore.kernel.org/r/f32130bf-cfd4-b1bf-538c-dbc9ee2d947a@eaxlabs.cz
Signed-off-by: Martin DEVERA <devik@eaxlabs.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Rockchip pinctrl driver needs to handle information from Devicetree
so only makes sense getting compiled on systems with CONFIG_OF enabled.
This also fixes a problem found by the "kernel-test-robot" when compiling
the driver on test-builds that do not have CONFIG_OF enabled:
drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_pinctrl_parse_groups':
>> drivers/pinctrl/pinctrl-rockchip.c:2881:9: error: implicit declaration of function 'pinconf_generic_parse_dt_config'; did you mean 'pinconf_generic_dump_config'? [-Werror=implicit-function-declaration]
2881 | ret = pinconf_generic_parse_dt_config(np_config, NULL,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinconf_generic_dump_config
drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_gpiolib_register':
>> drivers/pinctrl/pinctrl-rockchip.c:3473:5: error: 'struct gpio_chip' has no member named 'of_node'
3473 | gc->of_node = bank->of_node;
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20200905214955.907950-1-heiko@sntech.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The only usage of s900_padinfo[] is to assign it to the padinfo field in
the owl_pinctrl_soc_data struct, which is a const pointer. Make it const
to allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200830224311.36994-4-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The only usage of s700_padinfo[] is to assign it to the padinfo field in
the owl_pinctrl_soc_data struct, which is a const pointer. Make it const
to allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200830224311.36994-3-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The only usage of owl_pinctrl_ops and owl_pinmux_ops is to assign their
addresses to the pctlops and the pmxops fields in the pinctrl_desc struct,
which are const pointers. Make them const to allow the compiler to put them
in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200830224311.36994-2-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On page 23 of the datasheet [0] it says "The register remains unchanged
until the interrupt is cleared via a read of INTCAP or GPIO." Include
INTCAPA and INTCAPB registers in precious range, so that they aren't
accidentally cleared when we read via debugfs.
[0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf
Fixes: 8f38910ba4 ("pinctrl: mcp23s08: switch to regmap caching")
Signed-off-by: Thomas Preston <thomas.preston@codethink.co.uk>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20200828213226.1734264-3-thomas.preston@codethink.co.uk
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The mcp23x17_regmap is initialised with structs named "mcp23x16".
However, the mcp23s08 driver doesn't support the MCP23016 device yet, so
this appears to be a typo.
Fixes: 8f38910ba4 ("pinctrl: mcp23s08: switch to regmap caching")
Signed-off-by: Thomas Preston <thomas.preston@codethink.co.uk>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20200828213226.1734264-2-thomas.preston@codethink.co.uk
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
One some devices the GPIO should output the inverted value from what
device-drivers / ACPI code expects. The reason for this is unknown,
perhaps these systems use an external buffer chip on the GPIO which
inverts the signal. The BIOS makes this work by setting the
CHV_PADCTRL1_INVRXTX_TXDATA flag.
Before this commit we would unconditionally clear all INVRXTX flags,
including the CHV_PADCTRL1_INVRXTX_TXDATA flag when a GPIO is requested
by a driver (from chv_gpio_request_enable()).
This breaks systems using this setup. Specifically it is causing
problems for systems with a goodix touchscreen, where the BIOS sets the
INVRXTX_TXDATA flag on the GPIO used for the touchscreen's reset pin.
The goodix touchscreen driver by defaults configures this pin as input
(relying on the pull-up to keep it high), but the clearing of the
INVRXTX_TXDATA flag done by chv_gpio_request_enable() causes it to be
driven low for a brief time before the GPIO gets set to input mode.
This causes the touchscreen controller to get reset. On most CHT devs
with this touchscreen this leads to:
[ 31.596534] Goodix-TS i2c-GDIX1001:00: i2c test failed attempt 1: -121
The driver retries this though and then everything is fine. But during
reset the touchscreen uses its interrupt pin as bootstrap to determine
which i2c address to use and on the Acer One S1003 the spurious reset
caused by the clearing of the INVRXTX_TXDATA flag causes the controller
to come back up again on the wrong i2c address, breaking things.
This commit fixes both the -121 errors, as well as the total breakage
on the Acer One S1003, by making chv_gpio_clear_triggering() not clear
the INVRXTX_TXDATA flag if the pin is already configured as a GPIO.
Note that chv_pinmux_set_mux() does still unconditionally clear the
flag, so this only affects GPIO usage.
Fixes: a7d4b17166 ("Input: goodix - add support for getting IRQ + reset GPIOs on Cherry Trail devices")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Print particular message in each of error case in the ->probe().
While here, use dev_err_probe() for that.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200828103235.78380-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add initial Qualcomm msm8226 pinctrl driver to support pin configuration
with pinctrl framework for msm8226 SoC.
- Initial formatting and style was taken from the msm8x74 pinctrl driver
added by Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20200716205530.22910-3-bartosz.dudziak@snejp.pl
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Group name 'pcie1' is misleading as it controls only PCIe reset pin. Like
other PCIe groups it should have been called 'pcie1_reset'. But due to
backward compatibility it is not possible to change existing group name.
So just add comment describing this PCIe reset functionality.
Signed-off-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20200724132457.7094-1-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The nomadik pinctrl hardware doesn't have any way to
determine if the active pull is up or down. Reading
the bit currently used to report if the pull is up/down
indicates if the gpio input is reading high or low, it
doesn't reflect the pull state.
For this reason change the output from "pull up"/"pull down" to
"pull enabled". This avoids confusing developers who were using
the output to determine what the pull state is.
Signed-off-by: Andrew Halaney <ajhalaney@gmail.com>
Link: https://lore.kernel.org/r/20200806155322.GA25523@ola-jn9phv2.ad.garmin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update header inclusion block to reflect all direct dependencies
that are being involved in pinctrl-intel.h.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since we have common helper to retrieve SoC data from driver data
we may switch to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since we have common helper to retrieve SoC data from driver data
we may switch to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
intel_pinctrl_get_soc_data() helper can be used in few driver instead of
open-coded variants. Thus, extract it as a standalone API.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
By one of the previous clean up change we got a temporary variable to hold
a device pointer. It can be utilized in other calls in the ->probe() and
save a bit of LOCs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Now when all preparations are done we may easily switch to use
struct intel_pinctrl instead of custom one.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This is a preparatory patch for bigger clean up pending for Cherryview driver.
There is no functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
There is no more .groups member in struct chv_pinctrl,
drop associated comment because it's not applicable anymore.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
kernel series:
Core changes:
- The GPIO patch "gpiolib: Introduce
for_each_requested_gpio_in_range() macro" was put in an
immutable branch and merged into the pinctrl tree as well.
We see these changes also here.
- Improved debug output for pins used as GPIO.
New drivers:
- Ocelot Sparx5 SoC driver.
- Intel Emmitsburg SoC subdriver.
- Intel Tiger Lake-H SoC subdriver.
- Qualcomm PM660 SoC subdriver.
- Renesas SH-PFC R8A774E1 subdriver.
Driver improvements:
- Linear improvement and cleanups of the Intel drivers for
Cherryview, Lynxpoint, Baytrail etc. Improved locking among
other things.
- Renesas SH-PFC has added support for RPC pins, groups, and
functions to r8a77970 and r8a77980.
- The newere Freescale (now NXP) i.MX8 pin controllers have
been modularized. This is driven by the Google Android
GKI initiative I think.
- Open drain support for pins on the Qualcomm IPQ4019.
- The Ingenic driver can handle both edges IRQ detection.
- A big slew of documentation fixes all over the place.
- A few irqchip template conversions by yours truly.
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Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of the pin control changes for the v5.9 kernel
series:
Core changes:
- The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range()
macro" was put in an immutable branch and merged into the pinctrl
tree as well. We see these changes also here.
- Improved debug output for pins used as GPIO.
New drivers:
- Ocelot Sparx5 SoC driver.
- Intel Emmitsburg SoC subdriver.
- Intel Tiger Lake-H SoC subdriver.
- Qualcomm PM660 SoC subdriver.
- Renesas SH-PFC R8A774E1 subdriver.
Driver improvements:
- Linear improvement and cleanups of the Intel drivers for
Cherryview, Lynxpoint, Baytrail etc. Improved locking among other
things.
- Renesas SH-PFC has added support for RPC pins, groups, and
functions to r8a77970 and r8a77980.
- The newere Freescale (now NXP) i.MX8 pin controllers have been
modularized. This is driven by the Google Android GKI initiative I
think.
- Open drain support for pins on the Qualcomm IPQ4019.
- The Ingenic driver can handle both edges IRQ detection.
- A big slew of documentation fixes all over the place.
- A few irqchip template conversions by yours truly.
* tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
pinctrl: stmfx: Use irqchip template
pinctrl: amd: Use irqchip template
pinctrl: mediatek: fix build for tristate changes
pinctrl: samsung: Use bank name as irqchip name
pinctrl: core: print gpio in pins debugfs file
pinctrl: mediatek: add mt6779 eint support
pinctrl: mediatek: add pinctrl support for MT6779 SoC
pinctrl: mediatek: avoid virtual gpio trying to set reg
pinctrl: mediatek: update pinmux definitions for mt6779
pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API
pinctrl: mcp23s08: Use irqchip template
pinctrl: sx150x: Use irqchip template
dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
pinctrl: intel: Add Intel Emmitsburg pin controller support
pinctl: ti: iodelay: Replace HTTP links with HTTPS ones
Revert "gpio: omap: handle pin config bias flags"
pinctrl: single: Use fallthrough pseudo-keyword
pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
pinctrl: baytrail: Use fallthrough pseudo-keyword
...
Core changes:
- Introduce the for_each_requested_gpio() macro to help in
dependent code all over the place. Also patch a few locations
to use it while we are at it.
- Split out the sysfs code into its own file.
- Split out the character device code into its own file, then
make a set of refactorings and improvements to this code.
We are setting the stage to revamp the userspace API a bit
in the next cycle.
- Fix a whole slew of kerneldoc that was wrong or missing.
New drivers:
- The PCA953x driver now supports the PCAL9535.
Driver improvements:
- A host of incremental modernizations and improvements to the
PCA953x driver.
- Incremental improvements to the Xilinx Zynq driver.
- Some improvements to the GPIO aggregator driver.
- I ran all over the place switching all threaded and other
drivers requesting their own IRQ while using the core
GPIO IRQ helpers to pass the GPIO irq chip as a template
instead of calling the explicit set-up functions. Next merge
window we may retire the old code altogether.
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Merge tag 'gpio-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v5.9 kernel cycle.
There is nothing too exciting in it, but a new macro that fixes a
build failure on a minor ARM32 platform that appeared yesterday is
part of it so we better merge it.
Core changes:
- Introduce the for_each_requested_gpio() macro to help in dependent
code all over the place. Also patch a few locations to use it while
we are at it.
- Split out the sysfs code into its own file.
- Split out the character device code into its own file, then make a
set of refactorings and improvements to this code. We are setting
the stage to revamp the userspace API a bit in the next cycle.
- Fix a whole slew of kerneldoc that was wrong or missing.
New drivers:
- The PCA953x driver now supports the PCAL9535.
Driver improvements:
- A host of incremental modernizations and improvements to the
PCA953x driver.
- Incremental improvements to the Xilinx Zynq driver.
- Some improvements to the GPIO aggregator driver.
- I ran all over the place switching all threaded and other drivers
requesting their own IRQ while using the core GPIO IRQ helpers to
pass the GPIO irq chip as a template instead of calling the
explicit set-up functions. Next merge window we may retire the old
code altogether"
* tag 'gpio-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (97 commits)
gpio: wcove: Request IRQ after all initialisation done
gpio: crystalcove: Free IRQ on error path
gpio: pca953x: Request IRQ after all initialisation done
gpio: don't use same lockdep class for all devm_gpiochip_add_data users
gpio: max732x: Use irqchip template
gpio: stmpe: Move chip registration
gpio: rcar: Use irqchip template
gpio: regmap: fix type clash
gpio: Correct kernel-doc inconsistency
gpio: pci-idio-16: Use irqchip template
gpio: pcie-idio-24: Use irqchip template
gpio: 104-idio-16: Use irqchip template
gpio: 104-idi-48: Use irqchip template
gpio: 104-dio-48e: Use irqchip template
gpio: ws16c48: Use irqchip template
gpio: omap: improve coding style for pin config flags
gpio: dln2: Use irqchip template
gpio: sch: Add a blank line between declaration and code
gpio: sch: changed every 'unsigned' to 'unsigned int'
gpio: ich: changed every 'unsigned' to 'unsigned int'
...
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Amelie Delaunay <amelie.delaunay@st.com>
Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Link: https://lore.kernel.org/r/20200721131814.357182-1-linus.walleij@linaro.org
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit call to gpiochip_irqchip_add().
The irqchip is instead added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Cc: Sandeep Singh <sandeep.singh@amd.com>
Link: https://lore.kernel.org/r/20200722101545.144373-1-linus.walleij@linaro.org
Export mtk_is_virt_gpio() for the case when
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_PARIS=m
to fix this build error:
ERROR: modpost: "mtk_is_virt_gpio" [drivers/pinctrl/mediatek/pinctrl-paris.ko] undefined!
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Sean Wang <sean.wang@kernel.org>
Cc: linux-mediatek@lists.infradead.org
Link: https://lore.kernel.org/r/d15827a3-d0c8-e231-9f61-8507b3d7be3a@infradead.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the bank name as the irqchip name. This name is later visible in
/proc/interrupts, what makes it possible to easily identify each
GPIO interrupt.
/proc/interrupts before this patch:
143: 0 exynos4210_wkup_irq_chip 7 Edge hdmi
144: 0 exynos4210_wkup_irq_chip 6 Level wm8994
145: 1 exynos4210_wkup_irq_chip 7 Edge max77686-pmic, max77686-rtc
146: 1 exynos_gpio_irq_chip 3 Edge 3-0048
/proc/interrupts after this patch:
143: 0 gpx3 7 Edge hdmi
144: 0 gpx3 6 Level wm8994
145: 1 gpx0 7 Edge max77686-pmic, max77686-rtc
146: 1 gpm2 3 Edge 3-0048
Handling of the eint_wake_mask_value has been reworked, because each bank
has now its own exynos_irq_chip structure allocated.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200720145412.24221-1-krzk@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
add driver setting to support mt6779 eint
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/1595503197-15246-6-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Andy Teng <andy.teng@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/1595503197-15246-5-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
for virtual gpios, they should not do reg setting and
should behave as expected for eint function.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/1595503197-15246-4-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the hwspin_lock_timeout_in_atomic() API which is the most appropriated
here. Indeed:
- hwspin_lock_() is called after spin_lock_irqsave()
- the hwspin_lock_timeout() API relies on jiffies count which won't work
if IRQs are disabled which is the case here.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615124456.27328-1-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Jan Kundrát <jan.kundrat@cesnet.cz>
Cc: Phil Reid <preid@electromag.com.au>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Jason Kridner <jkridner@gmail.com>
Link: https://lore.kernel.org/r/20200721125223.344411-1-linus.walleij@linaro.org
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Cc: Peter Rosin <peda@axentia.se>
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200721132537.362160-1-linus.walleij@linaro.org
* New driver for Emmitsburg
* New driver for Tiger Lake-H
* Part 3 of Cherryview driver clean up
* Fix a glitch on Baytrail platforms
The following is an automated git shortlog grouped by driver:
ARM/orion/gpio:
- Make use of for_each_requested_gpio()
at91:
- Make use of for_each_requested_gpio()
baytrail:
- Use fallthrough pseudo-keyword
- Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH)
- Drop no-op ACPI_PTR() call
cherryview:
- Re-use data structures from pinctrl-intel.h (part 3)
- Convert chv_writel() to use chv_padreg()
- Introduce helpers to IO with common registers
- Introduce chv_readl() helper
gpio:
- xra1403: Make use of for_each_requested_gpio()
- mvebu: Make use of for_each_requested_gpio()
gpiolib:
- Introduce for_each_requested_gpio_in_range() macro
intel:
- Add Intel Emmitsburg pin controller support
- Make use of for_each_requested_gpio_in_range()
- Protect IO in few call backs by lock
- Split intel_config_get() to three functions
- Drop the only label in the code for consistency
- Get rid of redundant 'else' in intel_config_set_debounce()
- Make use of IRQ_RETVAL()
- Reduce scope of the lock
- Disable input and output buffer when switching to GPIO
- Allow drivers to define ACPI address space ID
- Allow drivers to define total amount of IRQs per community
lynxpoint:
- Drop no-op ACPI_PTR() call
- Introduce helpers to enable or disable input
- Make use of for_each_requested_gpio()
merrifield:
- Add I²S bus 2 pins to groups and functions
- Update pin names in accordance with official list
tigerlake:
- Add support for Tiger Lake-H
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Merge tag 'intel-pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.9-1
* New driver for Emmitsburg
* New driver for Tiger Lake-H
* Part 3 of Cherryview driver clean up
* Fix a glitch on Baytrail platforms
The following is an automated git shortlog grouped by driver:
ARM/orion/gpio:
- Make use of for_each_requested_gpio()
at91:
- Make use of for_each_requested_gpio()
baytrail:
- Use fallthrough pseudo-keyword
- Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH)
- Drop no-op ACPI_PTR() call
cherryview:
- Re-use data structures from pinctrl-intel.h (part 3)
- Convert chv_writel() to use chv_padreg()
- Introduce helpers to IO with common registers
- Introduce chv_readl() helper
gpio:
- xra1403: Make use of for_each_requested_gpio()
- mvebu: Make use of for_each_requested_gpio()
gpiolib:
- Introduce for_each_requested_gpio_in_range() macro
intel:
- Add Intel Emmitsburg pin controller support
- Make use of for_each_requested_gpio_in_range()
- Protect IO in few call backs by lock
- Split intel_config_get() to three functions
- Drop the only label in the code for consistency
- Get rid of redundant 'else' in intel_config_set_debounce()
- Make use of IRQ_RETVAL()
- Reduce scope of the lock
- Disable input and output buffer when switching to GPIO
- Allow drivers to define ACPI address space ID
- Allow drivers to define total amount of IRQs per community
lynxpoint:
- Drop no-op ACPI_PTR() call
- Introduce helpers to enable or disable input
- Make use of for_each_requested_gpio()
merrifield:
- Add I²S bus 2 pins to groups and functions
- Update pin names in accordance with official list
tigerlake:
- Add support for Tiger Lake-H
This driver adds pinctrl/GPIO support for Intel Emmitsburg PCH. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200718120807.19714-1-grandmaster@al2klimov.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add support for the new RZ/G2H (R8A774E1) SoC,
- One more conversion of DT bindings to json-schema,
- Fix RZ/A1 kerneldoc.
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Merge tag 'sh-pfc-for-v5.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v5.9 (take two)
- Add support for the new RZ/G2H (R8A774E1) SoC,
- One more conversion of DT bindings to json-schema,
- Fix RZ/A1 kerneldoc.
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20200713183541.36963-1-grandmaster@al2klimov.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since ACPI_PTR() is used to NULLify the value when !CONFIG_ACPI,
'struct amd_gpio_acpi_match' becomes defined but unused.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinctrl-amd.c:959:36: warning: ‘amd_gpio_acpi_match’ defined but not used [-Wunused-const-variable=]
959 | static const struct acpi_device_id amd_gpio_acpi_match[] = {
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Ken Xue <Ken.Xue@amd.com>
Cc: "Wu, Jeff" <Jeff.Wu@amd.com>
Cc: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
Cc: Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20200713144930.1034632-26-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Correct misspellings and provide missing entries.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:68: warning: Function parameter or member 'start_pin' not described in 'armada_37xx_pin_group'
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:68: warning: Function parameter or member 'val' not described in 'armada_37xx_pin_group'
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:68: warning: Function parameter or member 'extra_pin' not described in 'armada_37xx_pin_group'
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:68: warning: Function parameter or member 'extra_npins' not described in 'armada_37xx_pin_group'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lore.kernel.org/r/20200713144930.1034632-25-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It has never been used.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/meson/pinctrl-meson-a1.c:749:27: warning: ‘i2c_slave_groups’ defined but not used [-Wunused-const-variable=]
749 | static const char const i2c_slave_groups[] = {
| ^~~~~~~~~~~~~~~~
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Qianggui Song <qianggui.song@amlogic.com>
Cc: linux-amlogic@lists.infradead.org
Link: https://lore.kernel.org/r/20200713144930.1034632-24-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add some missing attributes/parameter descriptions, remove other
superfluous ones, add struct header titles and fix misspellings.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinctrl-single.c:50: warning: Function parameter or member 'mask' not described in 'pcs_func_vals'
drivers/pinctrl/pinctrl-single.c:97: warning: Function parameter or member 'conf' not described in 'pcs_function'
drivers/pinctrl/pinctrl-single.c:97: warning: Function parameter or member 'nconfs' not described in 'pcs_function'
drivers/pinctrl/pinctrl-single.c:659: warning: Function parameter or member 'pin_pos' not described in 'pcs_add_pin'
drivers/pinctrl/pinctrl-single.c:985: warning: Excess function parameter 'pctldev' description in 'pcs_parse_one_pinctrl_entry'
drivers/pinctrl/pinctrl-single.c:1357: warning: Cannot understand * @reg: virtual address of interrupt register
drivers/pinctrl/pinctrl-single.c:1377: warning: Function parameter or member 'pcs_soc' not described in 'pcs_irq_set'
drivers/pinctrl/pinctrl-single.c:1377: warning: Function parameter or member 'irq' not described in 'pcs_irq_set'
drivers/pinctrl/pinctrl-single.c:1377: warning: Function parameter or member 'enable' not described in 'pcs_irq_set'
drivers/pinctrl/pinctrl-single.c:1458: warning: Function parameter or member 'pcs_soc' not described in 'pcs_irq_handle'
drivers/pinctrl/pinctrl-single.c:1458: warning: Excess function parameter 'pcs_irq' description in 'pcs_irq_handle'
drivers/pinctrl/pinctrl-single.c:1506: warning: Excess function parameter 'irq' description in 'pcs_irq_chain_handler'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: linux-omap@vger.kernel.org
Link: https://lore.kernel.org/r/20200713144930.1034632-22-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Depending on how you look at it, you can either say that:
a) There is a PDC hardware issue (with the specific IP rev that exists
on sc7180) that causes the PDC not to work properly when configured
to handle dual edges.
b) The dual edge feature of the PDC hardware was only added in later
HW revisions and thus isn't in all hardware.
Regardless of how you look at it, let's work around the lack of dual
edge support by only ever letting our parent see requests for single
edge interrupts on affected hardware.
NOTE: it's possible that a driver requesting a dual edge interrupt
might get several edges coalesced into a single IRQ. For instance if
a line starts low and then goes high and low again, the driver that
requested the IRQ is not guaranteed to be called twice. However, it
is guaranteed that once the driver's interrupt handler starts running
its first instruction that any new edges coming in will cause the
interrupt to fire again. This is relatively commonplace for dual-edge
gpio interrupts (many gpio controllers require software to emulate
dual edge with single edge) so client drivers should be setup to
handle it.
Fixes: e35a6ae0eb ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200714080254.v3.1.Ie0d730120b232a86a4eac1e2909bcbec844d1766@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Demote headers which are clearly not kerneldoc, provide titles for
struct definition blocks, fix API slip (bitrot) misspellings and
provide some missing entries.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinctrl-rockchip.c:82: warning: cannot understand function prototype: 'struct rockchip_iomux '
drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_DEFAULT' not described in enum 'rockchip_pin_drv_type'
drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_OR_3V0' not described in enum 'rockchip_pin_drv_type'
drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_ONLY' not described in enum 'rockchip_pin_drv_type'
drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_3V0_AUTO' not described in enum 'rockchip_pin_drv_type'
drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_3V3_ONLY' not described in enum 'rockchip_pin_drv_type'
drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_MAX' not described in enum 'rockchip_pin_drv_type'
drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_IO_DEFAULT' not described in enum 'rockchip_pin_pull_type'
drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_IO_1V8_ONLY' not described in enum 'rockchip_pin_pull_type'
drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_MAX' not described in enum 'rockchip_pin_pull_type'
drivers/pinctrl/pinctrl-rockchip.c:109: warning: Cannot understand * @drv_type: drive strength variant using rockchip_perpin_drv_type
on line 109 - I thought it was a doc line
drivers/pinctrl/pinctrl-rockchip.c:122: warning: Cannot understand * @reg_base: register base of the gpio bank
on line 109 - I thought it was a doc line
drivers/pinctrl/pinctrl-rockchip.c:325: warning: Function parameter or member 'route_location' not described in 'rockchip_mux_route_data'
drivers/pinctrl/pinctrl-rockchip.c:328: warning: Cannot understand */
on line 109 - I thought it was a doc line
drivers/pinctrl/pinctrl-rockchip.c:375: warning: Function parameter or member 'data' not described in 'rockchip_pin_group'
drivers/pinctrl/pinctrl-rockchip.c:387: warning: Function parameter or member 'ngroups' not described in 'rockchip_pmx_func'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: linux-rockchip@lists.infradead.org
Link: https://lore.kernel.org/r/20200713144930.1034632-20-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinctrl-bm1880.c:40: warning: Function parameter or member 'pctrldev' not described in 'bm1880_pinctrl'
drivers/pinctrl/pinctrl-bm1880.c:40: warning: Function parameter or member 'pinconf' not described in 'bm1880_pinctrl'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200713144930.1034632-19-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The documentation header for 'struct at91_pinctrl_mux_ops' was missing
entries for {g,s}et_drivestrength and {g,s}et_slewrate.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinctrl-at91.c:77: warning: cannot understand function prototype: 'enum drive_strength_bit '
drivers/pinctrl/pinctrl-at91.c:187: warning: Function parameter or member 'get_drivestrength' not described in 'at91_pinctrl_mux_ops'
drivers/pinctrl/pinctrl-at91.c:187: warning: Function parameter or member 'set_drivestrength' not described in 'at91_pinctrl_mux_ops'
drivers/pinctrl/pinctrl-at91.c:187: warning: Function parameter or member 'get_slewrate' not described in 'at91_pinctrl_mux_ops'
drivers/pinctrl/pinctrl-at91.c:187: warning: Function parameter or member 'set_slewrate' not described in 'at91_pinctrl_mux_ops'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Link: https://lore.kernel.org/r/20200713144930.1034632-18-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinctrl-at91-pio4.c:132: warning: Function parameter or member 'pm_wakeup_sources' not described in 'atmel_pioctrl'
drivers/pinctrl/pinctrl-at91-pio4.c:132: warning: Function parameter or member 'pm_suspend_backup' not described in 'atmel_pioctrl'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20200713144930.1034632-16-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix a spelling/typo while we're here.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinconf-generic.c:242: warning: Function parameter or member 'pctldev' not described in 'pinconf_generic_parse_dt_config'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20200713144930.1034632-15-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/devicetree.c:27: warning: Function parameter or member 'map' not described in 'pinctrl_dt_map'
drivers/pinctrl/devicetree.c:27: warning: Function parameter or member 'num_maps' not described in 'pinctrl_dt_map'
drivers/pinctrl/devicetree.c:409: warning: Function parameter or member 'out_args' not described in 'pinctrl_parse_index_with_args'
drivers/pinctrl/devicetree.c:409: warning: Excess function parameter 'out_arts' description in 'pinctrl_parse_index_with_args'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20200713144930.1034632-14-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
And rename another which has probably bitrotted.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinmux.c:83: warning: Function parameter or member 'pctldev' not described in 'pinmux_can_be_used_for_gpio'
drivers/pinctrl/pinmux.c:108: warning: Function parameter or member 'pctldev' not described in 'pin_request'
drivers/pinctrl/pinmux.c:261: warning: Function parameter or member 'gpio' not described in 'pinmux_request_gpio'
drivers/pinctrl/pinmux.c:751: warning: Function parameter or member 'selector' not described in 'pinmux_generic_get_function'
drivers/pinctrl/pinmux.c:751: warning: Excess function parameter 'group_selector' description in 'pinmux_generic_get_function'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20200713144930.1034632-13-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Most are likely due to bitrot/API slip. Some are formatting issues.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/core.c:167: warning: Function parameter or member 'pin' not described in 'pin_get_name'
drivers/pinctrl/core.c:167: warning: Excess function parameter 'name' description in 'pin_get_name'
drivers/pinctrl/core.c:584: warning: Function parameter or member 'selector' not described in 'pinctrl_generic_get_group'
drivers/pinctrl/core.c:584: warning: Excess function parameter 'gselector' description in 'pinctrl_generic_get_group'
drivers/pinctrl/core.c:1356: error: Cannot parse struct or union!
drivers/pinctrl/core.c:1458: warning: Function parameter or member 'map' not described in 'pinctrl_unregister_mappings'
drivers/pinctrl/core.c:1458: warning: Excess function parameter 'maps' description in 'pinctrl_unregister_mappings'
drivers/pinctrl/core.c:2239: warning: Function parameter or member 'pctldev' not described in 'devm_pinctrl_register_and_init'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20200713144930.1034632-12-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Not all sourcefiles which end up including pinctrl-mtk-common-v2.h make use
of 'mtk_default_register_base_names' and there is nowhere we can place the
definition to void the need for __maybe_unused except its own headerfile,
which seems like overkill. So instead we tell the compiler that it's okay
for it to be unused by some of the consumers.
Fixes the following W=1 kernel build warning(s):
In file included from drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:19:
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h:83:27: warning: ‘mtk_default_register_base_names’ defined but not used [-Wunused-const-variable=]
83 | static const char const mtk_default_register_base_names[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/mediatek/pinctrl-moore.h:25,
from drivers/pinctrl/mediatek/pinctrl-moore.c:12:
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h:83:27: warning: ‘mtk_default_register_base_names’ defined but not used [-Wunused-const-variable=]
83 | static const char const mtk_default_register_base_names[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/mediatek/pinctrl-paris.h:27,
from drivers/pinctrl/mediatek/pinctrl-paris.c:15:
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h:83:27: warning: ‘mtk_default_register_base_names’ defined but not used [-Wunused-const-variable=]
83 | static const char const mtk_default_register_base_names[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/mediatek/pinctrl-paris.h:27,
from drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h:15,
from drivers/pinctrl/mediatek/pinctrl-mt6797.c:13:
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h:83:27: warning: ‘mtk_default_register_base_names’ defined but not used [-Wunused-const-variable=]
83 | static const char const mtk_default_register_base_names[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/mediatek/pinctrl-paris.h:27,
from drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h:12,
from drivers/pinctrl/mediatek/pinctrl-mt8183.c:9:
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h:83:27: warning: ‘mtk_default_register_base_names’ defined but not used [-Wunused-const-variable=]
83 | static const char const mtk_default_register_base_names[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/pinctrl/mediatek/pinctrl-paris.h:27,
from drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h:12,
from drivers/pinctrl/mediatek/pinctrl-mt6765.c:10:
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h:83:27: warning: ‘mtk_default_register_base_names’ defined but not used [-Wunused-const-variable=]
83 | static const char const mtk_default_register_base_names[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Sean Wang <sean.wang@kernel.org>
Cc: Sean Wang <sean.wang@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-mediatek@lists.infradead.org
Link: https://lore.kernel.org/r/20200713144930.1034632-11-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/qcom/pinctrl-msm8976.c:802:27: warning: ‘nav_tsync_groups’ defined but not used [-Wunused-const-variable=]
802 | static const char
const nav_tsync_groups[] = {
| ^~~~~~~~~~~~~~~~
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Del Regno <kholk11@gmail.com>
Cc: linux-arm-msm@vger.kernel.org
Link: https://lore.kernel.org/r/20200713144930.1034632-10-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Kerneldoc struct titles must be followed by whitespace else the
checker gets confused.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/samsung/pinctrl-s3c64xx.c:212: warning: cannot understand function prototype: 'struct s3c64xx_eint0_domain_data '
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: linux-samsung-soc@vger.kernel.org
Link: https://lore.kernel.org/r/20200713144930.1034632-9-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Kerneldoc struct titles must be followed by whitespace. Also attributes
need to be in the format '@.*: ' else the checker gets confused.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/samsung/pinctrl-s3c24xx.c💯 warning: cannot understand function prototype: 'struct s3c24xx_eint_domain_data '
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-samsung-soc@vger.kernel.org
Link: https://lore.kernel.org/r/20200713144930.1034632-8-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
No attempt has been made to document either of the demoted functions here.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/samsung/pinctrl-samsung.c:1149: warning: Function parameter or member 'dev' not described in 'samsung_pinctrl_suspend'
drivers/pinctrl/samsung/pinctrl-samsung.c:1199: warning: Function parameter or member 'dev' not described in 'samsung_pinctrl_resume'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: linux-samsung-soc@vger.kernel.org
Link: https://lore.kernel.org/r/20200713144930.1034632-7-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add missing descriptions for attributes and fix 1 formatting issue.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'desc' not described in 'msm_pinctrl'
drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'irq_chip' not described in 'msm_pinctrl'
drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'intr_target_use_scm' not described in 'msm_pinctrl'
drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'soc' not described in 'msm_pinctrl'
drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'phys_base' not described in 'msm_pinctrl'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Link: https://lore.kernel.org/r/20200713144930.1034632-6-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:141: warning: Function parameter or member 'chip' not described in 'iproc_set_bit'
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:141: warning: Excess function parameter 'iproc_gpio' description in 'iproc_set_bit'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Link: https://lore.kernel.org/r/20200713144930.1034632-5-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There has been little to no attempt to document any of the demoted
structures here. These are obviously not kerneldoc headers.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/bcm/pinctrl-bcm281xx.c:65: warning: cannot understand function prototype: 'enum bcm281xx_pin_type '
drivers/pinctrl/bcm/pinctrl-bcm281xx.c:79: warning: cannot understand function prototype: 'struct bcm281xx_pin_function '
drivers/pinctrl/bcm/pinctrl-bcm281xx.c:89: warning: cannot understand function prototype: 'struct bcm281xx_pinctrl_data '
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20200713144930.1034632-4-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
>From ill formatted kerneldoc, to incomplete *and* incorrect struct headers,
through to formatting issues and missing attribute descriptions.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/sirf/pinctrl-atlas7.c:197: warning: Function parameter or member 'id' not described in 'atlas7_pad_config'
drivers/pinctrl/sirf/pinctrl-atlas7.c:221: warning: Function parameter or member 'func' not described in 'atlas7_pad_status'
drivers/pinctrl/sirf/pinctrl-atlas7.c:221: warning: Function parameter or member 'pull' not described in 'atlas7_pad_status'
drivers/pinctrl/sirf/pinctrl-atlas7.c:221: warning: Function parameter or member 'dstr' not described in 'atlas7_pad_status'
drivers/pinctrl/sirf/pinctrl-atlas7.c:221: warning: Function parameter or member 'reserved' not described in 'atlas7_pad_status'
drivers/pinctrl/sirf/pinctrl-atlas7.c:359: warning: Cannot understand * @dev: a pointer back to containing device
on line 359 - I thought it was a doc line
drivers/pinctrl/sirf/pinctrl-atlas7.c:4794: warning: Function parameter or member 'pad_type' not described in 'atlas7_pull_info'
drivers/pinctrl/sirf/pinctrl-atlas7.c:4917: warning: Function parameter or member 'reserved' not described in 'atlas7_ds_info'
drivers/pinctrl/sirf/pinctrl-atlas7.c:5617: warning: Function parameter or member 'a7gc' not described in 'atlas7_gpio_to_bank'
drivers/pinctrl/sirf/pinctrl-atlas7.c:5617: warning: Function parameter or member 'gpio' not described in 'atlas7_gpio_to_bank'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Barry Song <baohua@kernel.org>
Link: https://lore.kernel.org/r/20200713144930.1034632-3-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/actions/pinctrl-owl.c:52: warning: Function parameter or member 'clk' not described in 'owl_pinctrl'
drivers/pinctrl/actions/pinctrl-owl.c:52: warning: Function parameter or member 'irq_chip' not described in 'owl_pinctrl'
drivers/pinctrl/actions/pinctrl-owl.c:52: warning: Function parameter or member 'num_irq' not described in 'owl_pinctrl'
drivers/pinctrl/actions/pinctrl-owl.c:52: warning: Function parameter or member 'irq' not described in 'owl_pinctrl'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Andreas Färber" <afaerber@suse.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: David Liu <liuwei@actions-semi.com>
Link: https://lore.kernel.org/r/20200713144930.1034632-2-lee.jones@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based
WiFi APs. ]
Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Link: https://lore.kernel.org/r/20200703080646.23233-1-computersforpeace@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The default pinmux configuration for Y23 is to route a heartbeat to
drive a LED. Previous revisions of the AST2600 datasheet did not include
a description of this function.
Fixes: 2eda1cdec4 ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20200701030756.2834657-1-joel@jms.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We need to iterate over each pin in a group for a function and
disable higher priority mux configurations on the pin before finally
muxing the relevant function's signal. With the current debug output it
is hard to track what register output is relevant to which operation, so
break up the actions in the debug output by providing some more context.
Before:
[ 5.446656] aspeed-g6-pinctrl 1e6e2000.syscon:pinctrl: request pin 37 (B26) for 1e780000.gpio:341
[ 5.447377] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000
[ 5.447854] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000
[ 5.448340] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000
After:
[ 5.298053] Muxing pin 37 for GPIO
[ 5.298294] Disabling signal NRI4 for NRI4
[ 5.298593] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000
[ 5.298983] Disabling signal RGMII4RXD1 for RGMII4
[ 5.299309] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000
[ 5.299694] Disabling signal RMII4RXD1 for RMII4
[ 5.300014] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000
[ 5.300396] Enabling signal GPIOE5 for GPIOE5
[ 5.300687] Muxed pin 37 as GPIOE5
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20200701030039.2834418-1-joel@jms.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some description blocks are void of any description/documentation,
others are missing 'struct' identifiers, there are also a couple of
misspellings of function parameter names. Fix all of them.
Fixes the following W=1 kernel build warning(s):
drivers/pinctrl/pinctrl-rza1.c:81: warning: cannot understand function prototype: 'struct rza1_bidir_pin '
drivers/pinctrl/pinctrl-rza1.c:90: warning: cannot understand function prototype: 'struct rza1_bidir_entry '
drivers/pinctrl/pinctrl-rza1.c:98: warning: cannot understand function prototype: 'struct rza1_swio_pin '
drivers/pinctrl/pinctrl-rza1.c:108: warning: cannot understand function prototype: 'struct rza1_swio_entry '
drivers/pinctrl/pinctrl-rza1.c:116: warning: cannot understand function prototype: 'struct rza1_pinmux_conf '
drivers/pinctrl/pinctrl-rza1.c:443: warning: cannot understand function prototype: 'struct rza1_mux_conf '
drivers/pinctrl/pinctrl-rza1.c:462: warning: cannot understand function prototype: 'struct rza1_port '
drivers/pinctrl/pinctrl-rza1.c:482: warning: cannot understand function prototype: 'struct rza1_pinctrl '
drivers/pinctrl/pinctrl-rza1.c:546: warning: Function parameter or member 'port' not described in 'rza1_pinmux_get_flags'
drivers/pinctrl/pinctrl-rza1.c:546: warning: Function parameter or member 'pin' not described in 'rza1_pinmux_get_flags'
drivers/pinctrl/pinctrl-rza1.c:546: warning: Function parameter or member 'func' not described in 'rza1_pinmux_get_flags'
drivers/pinctrl/pinctrl-rza1.c:546: warning: Function parameter or member 'rza1_pctl' not described in 'rza1_pinmux_get_flags'
drivers/pinctrl/pinctrl-rza1.c:575: warning: Function parameter or member 'port' not described in 'rza1_set_bit'
drivers/pinctrl/pinctrl-rza1.c:575: warning: Function parameter or member 'reg' not described in 'rza1_set_bit'
drivers/pinctrl/pinctrl-rza1.c:575: warning: Function parameter or member 'bit' not described in 'rza1_set_bit'
drivers/pinctrl/pinctrl-rza1.c:575: warning: Function parameter or member 'set' not described in 'rza1_set_bit'
drivers/pinctrl/pinctrl-rza1.c:672: warning: Function parameter or member 'rza1_pctl' not described in 'rza1_pin_mux_single'
drivers/pinctrl/pinctrl-rza1.c:672: warning: Excess function parameter 'pinctrl' description in 'rza1_pin_mux_single'
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Jacopo Mondi <jacopo@jmondi.org>
Link: https://lore.kernel.org/r/20200713144930.1034632-21-lee.jones@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (R8A77951),
however it doesn't have several automotive specific peripherals. Add
automotive-specific pin groups/functions along with common pin
groups/functions for supporting both r8a77951 and r8a774e1 SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594138692-16816-13-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Rather than always using handle_simple_irq() as the gpio_irq_chip
handler, set a more appropriate handler based on the IRQ trigger type
requested. This is important for level triggered interrupts which need
to be masked during handling. Also, fix the interrupt acknowledge so
that it clears only one interrupt instead of all interrupts which are
currently active. Finally there is no need to clear the interrupt during
the interrupt handler, since the edge-triggered handler will do that for
us.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Link: https://lore.kernel.org/r/20200703011830.15655-1-mark.tomlinson@alliedtelesis.co.nz
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This change drops the override in `amd_gpio_irq_set_type()` that
ignores the IRQ trigger type settings from the caller. The device
driver (caller) is in a better position to identify the right trigger
type for the device based on the usage as well as the information
exposed by the BIOS. There are instances where the device driver might
want to configure the trigger type differently in different modes. An
example of this is gpio-keys driver which configures IRQ type as
trigger on both edges (to identify assert and deassert events) when in
S0 and reconfigures the trigger type using the information provided by
the BIOS when going into suspend to ensure that the wake happens on
the required edge.
This override in `amd_gpio_irq_set_type()` prevents the caller from
being able to reconfigure trigger type once it is set either based on
ACPI information or the type used by the first caller for IRQ on a
given GPIO line.
Without this change, pen-insert gpio key (used by garaged stylus on a
Chromebook) works fine in S0 (i.e. insert and eject events are
correctly identified), however, BIOS configuration for wake on only
pen eject i.e. only-rising edge or only-falling edge is not honored.
With this change, it was verified that pen-insert gpio key behavior is
correct in both S0 and for wakeup from S3.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Shyam Sundar S K<Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20200626211026.513520-1-furquan@google.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The PAT1 register contains information about the IRQ type (edge/level)
for input GPIOs with IRQ enabled, and the direction for non-IRQ GPIOs.
So it makes sense to read it only if the GPIO has no interrupt
configured, otherwise input GPIOs configured for level IRQs are
misdetected as output GPIOs.
Fixes: ebd6651418 ("pinctrl: ingenic: Implement .get_direction for GPIO chips")
Reported-by: João Henrique <johnnyonflame@hotmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200622214548.265417-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Ingenic SoCs don't natively support registering an interrupt for both
rising and falling edges. This has to be emulated in software.
Until now, this was emulated by switching back and forth between
IRQ_TYPE_EDGE_RISING and IRQ_TYPE_EDGE_FALLING according to the level of
the GPIO. While this worked most of the time, when used with GPIOs that
need debouncing, some events would be lost. For instance, between the
time a falling-edge interrupt happens and the interrupt handler
configures the hardware for rising-edge, the level of the pin may have
already risen, and the rising-edge event is lost.
To address that issue, instead of switching back and forth between
IRQ_TYPE_EDGE_RISING and IRQ_TYPE_EDGE_FALLING, we now switch back and
forth between IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_LEVEL_HIGH. Since we
always switch in the interrupt handler, they actually permit to detect
level changes. In the example above, if the pin level rises before
switching the IRQ type from IRQ_TYPE_LEVEL_LOW to IRQ_TYPE_LEVEL_HIGH,
a new interrupt will raise as soon as the handler exits, and the
rising-edge event will be properly detected.
Fixes: e72394e2ea ("pinctrl: ingenic: Merge GPIO functionality")
Reported-by: João Henrique <johnnyonflame@hotmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: João Henrique <johnnyonflame@hotmail.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200622214548.265417-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for pm660(l) SPMI GPIOs. The PMICs feature
13 and 12 GPIOs respectively, though with a lot of
holes inbetween.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200622192558.152828-2-konradybcio@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This add support for Sparx5 pinctrl, using the ocelot drives as
basis. It adds pinconfig support as well, as supported by the
platform.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20200615133242.24911-6-lars.povlsen@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two
or more registers. However, when register and bit were calculated, the
first register defined in the bank was used, and the bit was calculated
based on the first pin. This causes problems in setting the driving
strength.
The following method was used to solve this problem:
A bit is calculated first using predefined strides. Then, If the bit is
32 or more, the register is changed by the quotient of the bit divided
by 32. And the bit is set to the remainder.
Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
Link: https://lore.kernel.org/r/20200618025916.GA19368@home-desktop
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the correct the function name in the documentation for
"pcs_parse_one_pinctrl_entry()".
"smux_parse_one_pinctrl_entry()" appears to be an artifact from the
development of a prior patch series ("simple pinmux driver") which
transformed into pinctrl-single.
Fixes: 8b8b091bf0 ("pinctrl: Add one-register-per-pin type device tree based pinctrl driver")
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Link: https://lore.kernel.org/r/20200617180543.GA4186054@x1
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If "pinctrl-single,pins" has 3 arguments (offset, conf, mux), then
pcs_parse_one_pinctrl_entry() does an OR operation on conf and mux to
get the value to store in the register.
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Link: https://lore.kernel.org/r/20200701013320.130441-2-drew@beagleboard.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Export necessary APIs to support i.MX8 SCU SoCs pinctrl driver to be
built as module.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/1592979844-18833-3-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Export necessary APIs to support i.MX8 SoCs pinctrl driver to be
built as module.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/1592979844-18833-2-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add RPC (HyperFlash and Octal-SPI Flash) pin groups on R-Car V3H and
V3M.
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Merge tag 'sh-pfc-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v5.9
- Add RPC (HyperFlash and Octal-SPI Flash) pin groups on R-Car V3H and
V3M.
Intel Tiger Lake-H has different pin layout than the -LP variant
so add support for this to the existing Tiger Lake driver.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
It is useful to control I²S bus 2 pins if we would like to connect
an audio codec.
Reported-by: mouse <xllacyx@gmail.com>
Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* Fix output pin value handling on Intel Baytrail
The following is an automated git shortlog grouped by driver:
baytrail:
- Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH)
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Merge tag 'intel-pinctrl-v5.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes
intel-pinctrl for v5.8-2
* Fix output pin value handling on Intel Baytrail
The following is an automated git shortlog grouped by driver:
baytrail:
- Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH)
The pins on the Bay Trail SoC have separate input-buffer and output-buffer
enable bits and a read of the level bit of the value register will always
return the value from the input-buffer.
The BIOS of a device may configure a pin in output-only mode, only enabling
the output buffer, and write 1 to the level bit to drive the pin high.
This 1 written to the level bit will be stored inside the data-latch of the
output buffer.
But a subsequent read of the value register will return 0 for the level bit
because the input-buffer is disabled. This causes a read-modify-write as
done by byt_gpio_set_direction() to write 0 to the level bit, driving the
pin low!
Before this commit byt_gpio_direction_output() relied on
pinctrl_gpio_direction_output() to set the direction, followed by a call
to byt_gpio_set() to apply the selected value. This causes the pin to
go low between the pinctrl_gpio_direction_output() and byt_gpio_set()
calls.
Change byt_gpio_direction_output() to directly make the register
modifications itself instead. Replacing the 2 subsequent writes to the
value register with a single write.
Note that the pinctrl code does not keep track internally of the direction,
so not going through pinctrl_gpio_direction_output() is not an issue.
This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is
already on at boot (no external monitor connected), then the i915 driver
does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The
temporarily going low of that GPIO was causing the panel to reset itself
after which it would not show an image until it was turned off and back on
again (until a full modeset was done on it). This commit fixes this.
This commit also updates the byt_gpio_direction_input() to use direct
register accesses instead of going through pinctrl_gpio_direction_input(),
to keep it consistent with byt_gpio_direction_output().
Note for backporting, this commit depends on:
commit e2b74419e5 ("pinctrl: baytrail: Replace WARN with dev_info_once
when setting direct-irq pin to output")
Cc: stable@vger.kernel.org
Fixes: 86e3ef812f ("pinctrl: baytrail: Update gpio chip operations")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Some of the pin names were provided officially to the customers
in different spelling. We update pin names in accordance with
the official list.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Add the RPC pins/groups/functions to the R8A77970 PFC driver.
They can be used if an Octal-SPI flash or HyperFlash is connected.
Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/3982785f-4fca-96f9-2b6a-a0d1828cb0ad@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the RPC pins/groups/functions to the R8A77980 PFC driver.
They can be used if an Octal-SPI flash or HyperFlash is connected.
Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/fd089d37-95bb-4ec9-282f-e04d7e5195e4@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The pins on the Bay Trail SoC have separate input-buffer and output-buffer
enable bits and a read of the level bit of the value register will always
return the value from the input-buffer.
The BIOS of a device may configure a pin in output-only mode, only enabling
the output buffer, and write 1 to the level bit to drive the pin high.
This 1 written to the level bit will be stored inside the data-latch of the
output buffer.
But a subsequent read of the value register will return 0 for the level bit
because the input-buffer is disabled. This causes a read-modify-write as
done by byt_gpio_set_direction() to write 0 to the level bit, driving the
pin low!
Before this commit byt_gpio_direction_output() relied on
pinctrl_gpio_direction_output() to set the direction, followed by a call
to byt_gpio_set() to apply the selected value. This causes the pin to
go low between the pinctrl_gpio_direction_output() and byt_gpio_set()
calls.
Change byt_gpio_direction_output() to directly make the register
modifications itself instead. Replacing the 2 subsequent writes to the
value register with a single write.
Note that the pinctrl code does not keep track internally of the direction,
so not going through pinctrl_gpio_direction_output() is not an issue.
This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is
already on at boot (no external monitor connected), then the i915 driver
does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The
temporarily going low of that GPIO was causing the panel to reset itself
after which it would not show an image until it was turned off and back on
again (until a full modeset was done on it). This commit fixes this.
This commit also updates the byt_gpio_direction_input() to use direct
register accesses instead of going through pinctrl_gpio_direction_input(),
to keep it consistent with byt_gpio_direction_output().
Note for backporting, this commit depends on:
commit e2b74419e5 ("pinctrl: baytrail: Replace WARN with dev_info_once
when setting direct-irq pin to output")
Cc: stable@vger.kernel.org
Fixes: 86e3ef812f ("pinctrl: baytrail: Update gpio chip operations")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Since we dependent on ACPI, there is no need to use ACPI_PTR()
which is a no-op in this case.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since we dependent on ACPI, there is no need to use ACPI_PTR()
which is a no-op in this case.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Introduce couple of helpers to enable or disable input. i.e.
lp_gpio_enable_input() and lp_gpio_disable_input().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Make use of for_each_requested_gpio() instead of home grown analogue.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Make use of for_each_requested_gpio_in_range() instead of home grown analogue.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Protect IO in intel_gpio_get_direction(), intel_gpio_community_irq_handler(),
intel_config_get_debounce() and intel_config_get_pull() by lock. Even for
simple readl() we better serialize IO to avoid potential problems.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Split intel_config_get() to three functions, i.e. intel_config_get() and
two helpers intel_config_get_pull() and intel_config_get_debounce() to be
symmetrical with intel_config_set*().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Drop the only label in the code, i.e. in intel_config_set_debounce(),
for consistency with the rest. In entire driver we use multipoint
return.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
In a code like
if (...) {
...
goto label;
} else {
...
}
the 'else' keyword is redundant. Get rid of it for better readability.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Instead of using bitwise operations against returned values,
which is a bit fragile, convert IRQ handler to count amount of
GPIO groups, where at least one interrupt happened, and convert
it to returned value by IRQ_RETVAL() macro.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
In some cases lock covers unneeded calls and operations.
Reduce scope of the lock in such cases.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
It's possible scenario that pin has been in different mode, while
the respective GPIO register has a leftover output buffer enabled.
In such case when we request GPIO it will switch to GPIO mode, and
thus to output with unknown value, followed by switching to input
mode. This can produce a glitch on the pin.
Disable input and output buffer when switching to GPIO to avoid
potential glitches.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
We have some data structures duplicated across the drivers.
Let's deduplicate them by using struct intel_pinctrl_soc_data,
struct intel_community and struct intel_pinctrl_context that
are being provided by pinctrl-intel.h.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Individual drivers may install ACPI OpRegion handlers based on
address space ID which differs from community to community.
Add special field in the struct intel_community for that purpose.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Some of the pin control devices may not be capable to generate IRQ
per each pin in the community. Allow individual drivers to define
total amount of IRQs per community.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
chv_writel() is now solely used for cases where we write data
to the PAD registers. In order to simplify callers, calculate
register address inside chv_writel().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Pin control device and effectively the single community in it has
a set of common registers. It's good to have a helpers to IO on them.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
There are plenty of places where we call
readl(chv_padreg(pctrl, offset, ...));
Replace them with newly introduced chv_readl() helper
chv_readl(pctrl, offset, ...);
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
uart0_pins is defined as:
static const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
which npins is wronly specified as 9 later
{
.name = "uart0",
.pins = uart0_pins,
.npins = 9,
},
npins should be 5 instead of 9 according to the definition.
Signed-off-by: Jacky Hu <hengqing.hu@gmail.com>
Link: https://lore.kernel.org/r/20200616015024.287683-1-hengqing.hu@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make use of for_each_requested_gpio() instead of home grown analogue.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20200615150545.87964-6-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Adds the possibility to configure a single pin through the gpiolib (i.e:
to set PULL_UP/PULL_DOWN config).
Mutex behavior is slightly changed to avoid a deadlock when pin_config_set
is called (in this case pctldev->mutex is already taken).
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615125951.28008-3-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
".pin_config_set" or ".pin_config_group_set" can be called with a
configuration not supported (i.e. PIN_CONFIG_PERSIST_STATE). In this case,
it is more suitable to return -ENOTSUPP instead of -EINVAL.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615125951.28008-2-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Defer probe when pin controller reset is defined in the system resources
but not yet probed.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615125407.27632-3-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Change STM32 pinctrl driver to not print an error trace when probe is
deferred due to clock resource. Probe defer issue (for clocks) could
occur during bank registering when some banks have already been registered.
In this case banks already registered should be released. To not waste time
in this case, it is better to check first if all clocks are available
before registering banks.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615125407.27632-2-alexandre.torgue@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a compatible string to support the GPIO chips on the JZ4725B SoC.
There was already a compatible string for the pinctrl node, but not for
the individual GPIO chip nodes.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200612120609.12730-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the correct the function name in the documentation for
"pcs_parse_one_pinctrl_entry()".
"smux_parse_one_pinctrl_entry()" appears to be an artifact from the
development of a prior patch series ("simple pinmux driver") which
transformed into pinctrl-single.
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Link: https://lore.kernel.org/r/20200612112758.GA3407886@x1
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The patch adds missing qpic data pins to qpic pingroup. These pins are
necessary for the qpic nand to work.
Fixes: ef1ea54eab ("pinctrl: qcom: Add ipq6018 pinctrl driver")
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1592541089-17700-1-git-send-email-sivaprak@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This reverts commit ba40324261.
After commit 26d8cde526 ("pinctrl: freescale: imx: add shared
input select reg support"). i.MX7D has two iomux controllers
iomuxc and iomuxc-lpsr which share select_input register for
daisy chain settings.
If use 'devm_of_iomap()', when probe the iomuxc-lpsr, will call
devm_request_mem_region() for the region <0x30330000-0x3033ffff>
for the first time. Then, next time when probe the iomuxc, API
devm_platform_ioremap_resource() will also use the API
devm_request_mem_region() for the share region <0x30330000-0x3033ffff>
again, then cause issue, log like below:
[ 0.179561] imx7d-pinctrl 302c0000.iomuxc-lpsr: initialized IMX pinctrl driver
[ 0.191742] imx7d-pinctrl 30330000.pinctrl: can't request region for resource [mem 0x30330000-0x3033ffff]
[ 0.191842] imx7d-pinctrl: probe of 30330000.pinctrl failed with error -16
Fixes: ba40324261 ("pinctrl: freescale: imx: Use 'devm_of_iomap()' to avoid a resource leak in case of error in 'imx_pinctrl_probe()'")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/1591673223-1680-1-git-send-email-haibo.chen@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch causes pcs_parse_pinconf() to return -ENOTSUPP when no
pinctrl_map is added. The current behavior is to return 0 when
!PCS_HAS_PINCONF or !nconfs. Thus pcs_parse_one_pinctrl_entry()
incorrectly assumes that a map was added and sets num_maps = 2.
Analysis:
=========
The function pcs_parse_one_pinctrl_entry() calls pcs_parse_pinconf()
if PCS_HAS_PINCONF is enabled. The function pcs_parse_pinconf()
returns 0 to indicate there was no error and num_maps is then set to 2:
980 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
981 struct device_node *np,
982 struct pinctrl_map **map,
983 unsigned *num_maps,
984 const char **pgnames)
985 {
<snip>
1053 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1054 (*map)->data.mux.group = np->name;
1055 (*map)->data.mux.function = np->name;
1056
1057 if (PCS_HAS_PINCONF && function) {
1058 res = pcs_parse_pinconf(pcs, np, function, map);
1059 if (res)
1060 goto free_pingroups;
1061 *num_maps = 2;
1062 } else {
1063 *num_maps = 1;
1064 }
However, pcs_parse_pinconf() will also return 0 if !PCS_HAS_PINCONF or
!nconfs. I believe these conditions should indicate that no map was
added by returning -ENOTSUPP. Otherwise pcs_parse_one_pinctrl_entry()
will set num_maps = 2 even though no maps were successfully added, as
it does not reach "m++" on line 940:
895 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
896 struct pcs_function *func,
897 struct pinctrl_map **map)
898
899 {
900 struct pinctrl_map *m = *map;
<snip>
917 /* If pinconf isn't supported, don't parse properties in below. */
918 if (!PCS_HAS_PINCONF)
919 return 0;
920
921 /* cacluate how much properties are supported in current node */
922 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
923 if (of_find_property(np, prop2[i].name, NULL))
924 nconfs++;
925 }
926 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
927 if (of_find_property(np, prop4[i].name, NULL))
928 nconfs++;
929 }
930 if (!nconfs)
919 return 0;
932
933 func->conf = devm_kcalloc(pcs->dev,
934 nconfs, sizeof(struct pcs_conf_vals),
935 GFP_KERNEL);
936 if (!func->conf)
937 return -ENOMEM;
938 func->nconfs = nconfs;
939 conf = &(func->conf[0]);
940 m++;
This situtation will cause a boot failure [0] on the BeagleBone Black
(AM3358) when am33xx_pinmux node in arch/arm/boot/dts/am33xx-l4.dtsi
has compatible = "pinconf-single" instead of "pinctrl-single".
The patch fixes this issue by returning -ENOSUPP when !PCS_HAS_PINCONF
or !nconfs, so that pcs_parse_one_pinctrl_entry() will know that no
map was added.
Logic is also added to pcs_parse_one_pinctrl_entry() to distinguish
between -ENOSUPP and other errors. In the case of -ENOSUPP, num_maps
is set to 1 as it is valid for pinconf to be enabled and a given pin
group to not any pinconf properties.
[0] https://lore.kernel.org/linux-omap/20200529175544.GA3766151@x1/
Fixes: 9dddb4df90 ("pinctrl: single: support generic pinconf")
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20200608125143.GA2789203@x1
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Lad Prabhakar