Commit Graph

183 Commits

Author SHA1 Message Date
Ben Skeggs 35dde8d406 drm/nouveau/kms/nv50-: add some whitespace before debug message
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-09-03 15:32:23 +10:00
Ben Skeggs d9a91300ae drm/nouveau/fbcon: convert accel_init() to new push macros
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:56 +10:00
Ben Skeggs 0a96099691 drm/nouveau/kms/nv50-: implement proper push buffer control logic
We had a, what was supposed to be temporary, hack in the KMS code where we'd
completely drain an EVO/NVD channel's push buffer when wrapping to the start
again, instead of treating it as a ring buffer.

Let's fix that, finally.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-07-24 18:50:56 +10:00
Ben Skeggs 34cf8cae28 drm/nouveau/kms/nv50-: convert wndw sema_set() to new push macros
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:52 +10:00
Ben Skeggs bea8395ccf drm/nouveau/kms/nv50-: convert wimm point() to new push macros
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:51 +10:00
Ben Skeggs 2853ccf092 drm/nouveau/kms/nv50-: wrap existing command submission in nvif_push interface
This commit pulls in a bunch of new push buffer macros which are able to
support NVIDIA's class headers, and provide more useful debug output and
error checking (compile-time, where possible) than we had previously.

Will incrementally transition each function over to the unified interfaces.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:51 +10:00
Ben Skeggs 3e176fd060 drm/nouveau/nvif: add support for object-level debug output
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:51 +10:00
Ben Skeggs f7a7d22ad6 drm/nouveau/nvif: give every notify object a human-readable name
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:51 +10:00
Ben Skeggs 54d44bfc56 drm/nouveau/nvif: give every disp object a human-readable identifier
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:51 +10:00
Ben Skeggs 64a0f59ab1 drm/nouveau/nvif: give every usermode object a human-readable identifier
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:51 +10:00
Ben Skeggs 45faf3d7b6 drm/nouveau/nvif: give every vmm object a human-readable identifier
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:51 +10:00
Ben Skeggs e79c9a0ba5 drm/nouveau/nvif: give every mem object a human-readable identifier
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:51 +10:00
Ben Skeggs b495396cc9 drm/nouveau/nvif: give every mmu object a human-readable identifier
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:50 +10:00
Ben Skeggs bd21080eb6 drm/nouveau/nvif: give every device object a human-readable identifier
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:50 +10:00
Ben Skeggs 9ac596a4e8 drm/nouveau/nvif: give every object a human-readable identifier
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:50 +10:00
Ben Skeggs 6db25fb13a drm/nouveau/nvif: rename client ctor/dtor
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-07-24 18:50:50 +10:00
Ben Skeggs 6f8dbcf1c9 drm/nouveau/disp: provide hint to OR allocation about HDA requirements
Will be used by a subsequent commit to influence SOR allocation policy.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-06-04 14:23:20 +10:00
Ben Skeggs 9c1c08a68d drm/nouveau/disp/gv100-: expose capabilities class
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-05-22 11:13:49 +10:00
Ben Skeggs ed3d1489d2 drm/nouveau/nvif: protect waits against GPU falling off the bus
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-04-07 14:37:50 +10:00
Ben Skeggs 58e92b5ee8 drm/nouveau/nvif: access PTIMER through usermode class, if available
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-04-07 14:37:50 +10:00
Ben Skeggs afa3b96b05 drm/nouveau/gr/tu10x: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:50:30 +10:00
James Jones 176ada03e3 drm/nouveau/mmu: Add correct turing page kinds
Turing introduced a new simplified page kind
scheme, reducing the number of possible page
kinds from 256 to 16.  It also is the first
NVIDIA GPU in which the highest possible page
kind value is not reserved as an "invalid" page
kind.

To address this, the invalid page kind is made
an explicit property of the MMU HAL, and a new
table of page kinds is added to the tu102 MMU
HAL.

One hardware change not addressed here is that
0x00 is technically no longer a supported page
kind, and pitch surfaces are instead intended to
share the block-linear generic page kind 0x06.
However, because that will be a rather invasive
change to nouveau and 0x00 still works fine in
practice on Turing hardware, addressing this new
behavior is deferred.

Signed-off-by: James Jones <jajones@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:49:59 +10:00
Ilia Mirkin b7019ac550 drm/nouveau: fix bogus GPL-2 license header
The bulk SPDX addition made all these files into GPL-2.0 licensed files.
However the remainder of the project is MIT-licensed, these files
(primarily header files) were simply missing the boiler plate and got
caught up in the global update.

Fixes: b24413180f (License cleanup: add SPDX GPL-2.0 license identifier to files with no license)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-07-19 16:26:50 +10:00
Ben Skeggs a261a20c01 drm/nouveau/fault/gv100-: expose VoltaFaultBufferA
This nvclass exposes the replayable fault buffer, which will be used
by SVM to manage GPU page faults.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:01 +10:00
Ben Skeggs 13e9572906 drm/nouveau/fault/gp100: expose MaxwellFaultBufferA
This nvclass exposes the replayable fault buffer, which will be used
by SVM to manage GPU page faults.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs ab2ee9ffa3 drm/nouveau/mmu/gp100-: support vmms with gcc/tex replayable faults enabled
Some GPU units are capable of supporting "replayable" page faults, where
the execution unit will wait for SW to fixup GPU page tables rather than
triggering a channel-fatal fault.

This feature isn't useful (it's harmful, even) unless something like HMM
is being used to manage events appearing in the replayable fault buffer,
so, it's disabled by default.

This commit allows a client to request it be enabled.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs 71871aa6df drm/nouveau/mmu/gp100-: add privileged methods for fault replay/cancel
Host methods exist to do at least some of what we need, but we are not
currently pushing replay/cancels through a channel like UVM does as it's
not clear whether it's necessary in our case (UVM also updates PTEs with
the GPU).

UVM also pushes a software method for fault cancels on Pascal, seemingly
because the host methods don't appear to be sufficient.  If/when we want
to push the replay/cancel on the GPU, we can re-purpose the cancellation
code here to implement that swmthd.

Keep it simple for now, until we figure out exactly what we need here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs a5ff307fe1 drm/nouveau/mmu: add a privileged method to directly manage PTEs
This provides a somewhat more direct method of manipulating the GPU page
tables, which will be required to support SVM.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs 2606f29162 drm/nouveau/mmu: support initialisation of client-managed address-spaces
NVKM is currently responsible for managing the allocation of a client's
GPU address-space, but there's various use-cases (ie. HMM address-space
mirroring) where giving a client more direct control is desirable.

This commit allows for a VMM to be created where the area allocated for
NVKM is limited to a client-specified window, the remainder of address-
space is controlled directly by the client.

Leaving a window is necessary to support various internal requirements,
but also to support existing allocation interfaces as not all of the HW
is capable of working with a HMM allocation.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs 8603774233 drm/nouveau/disp/tu102: rename implementation from tu104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 08:59:58 +10:00
Ben Skeggs c36322d23d drm/nouveau/ce/tu104: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:55 +10:00
Ben Skeggs 641d0b3056 drm/nouveau/fifo/tu104: initial support
Various different bits and pieces vs GV100.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:55 +10:00
Ben Skeggs 114b6556db drm/nouveau/disp/tu104: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:54 +10:00
Ben Skeggs 344d9c8f35 drm/nouveau/core: recognise TU104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:50 +10:00
Ben Skeggs 9d24907ccf drm/nouveau/fifo/gv100: return work submission token in channel ctor args
The token will also contain runlist ID on Turing, so instead expose it as
an opaque value from NVKM so the client doesn't need to care.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:49 +10:00
Ben Skeggs 85532bd984 drm/nouveau/fifo/gk104-: support enabling privileged ce functions
Will be used by SVM code to allow direct (without going through MMU) memcpy
using the GPU copy engines.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:47 +10:00
Ben Skeggs 86b442d74c drm/nouveau/fifo/gk104-: return channel instance in ctor args
Will be used to match fault buffer entries with a channel.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:47 +10:00
Ilia Mirkin 4126b99e74 drm/nouveau/disp: add a way to configure scrambling/tmds for hdmi 2.0
High pixel clocks are required to use a 40 TMDS divider instead of 10,
and even low ones may optionally use scrambling depending on device
support.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-10-11 09:54:10 +10:00
Nick Desaulniers c9fb2cc84c drm/nouveau/nvif: remove const attribute from nvif_mclass
Similar to commit 0bf8bf50ed ("module: Remove
const attribute from alias for MODULE_DEVICE_TABLE")

Fixes many -Wduplicate-decl-specifier warnings due to the combination of
const typeof() of already const variables.

Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16 18:06:29 +10:00
Ben Skeggs d521097f58 drm/nouveau/gr/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:47 +10:00
Ben Skeggs 6e1f34e33c drm/nouveau/ce/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:46 +10:00
Ben Skeggs 37e1c45a58 drm/nouveau/fifo/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:46 +10:00
Ben Skeggs 290ffeafcc drm/nouveau/disp/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:43 +10:00
Ben Skeggs c1f856bb99 drm/nouveau/core: recognise gv100
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:31 +10:00
Ben Skeggs 0d4a2c5767 drm/nouveau/kms: move display class instantiation to library
This function is useful outside of DRM code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs a7cf01809b drm/nouveau/fifo/gk104-: require explicit runlist selection for channel allocation
We didn't used to be aware that runlist/engine IDs weren't the same thing,
or that there was such variability in configuration between GPUs.

By exposing this information to a client, and giving it explicit control
of which runlist it's allocating a channel on, we're able to make better
choices.

The immediate effect of this is that on GPUs where CE0 is the "GRCE", we
will now be allocating a copy engine running asynchronously to GR for BO
migrations - as intended.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs cc36205085 drm/nouveau/fifo/gk104-: support querying engines available on each runlist
Will be used to improve channel runlist selection.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs eb47db4f3b drm/nouveau/fifo: support channel count query
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 6eb01aa898 drm/nouveau/device: support querying available engines of a specific type
Will be used for fifo runlist selection.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs c5c9127b25 drm/nouveau/device: implement a generic method to query device-specific properties
We have a need to fetch data from GPU-specific sub-devices that is not
tied to any particular engine object.

This commit provides the framework to support such queries.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00