The contents of Config ROM in firewire device structure are already
aligned to CPU-endianness. Thus, no need to convert it again.
This commit removes needless conversions
Fixes: 9edf723fd858('ALSA: firewire-digi00x: add skeleton for Digi 002/003 family')
Fixes: c0949b278515('ALSA: firewire-tascam: add skeleton for TASCAM FireWire series')
Reported-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit adds MIDI functionality to capture/playback MIDI messages
from/to physical MIDI ports. These messages are transferred in isochronous
packets.
When no substreams request AMDTP streams to run, this driver starts the
streams at current sampling rate. When other substreams start at different
sampling rate, the streams are stopped temporarily, then start again at
requested sampling rate. This operation can generate missing MIDI bytes,
thus it's preferable to start PCM substreams at favorite sampling rate in
advance.
Digi 002/003 console also has a set of MIDI port for physical controls.
These ports are added in later commits.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Digi 002/003 family uses asynchronous transaction for messaging.
The address to transmit this message is stored on a certain register.
This commit allocates a range of address on OHCI 1394 host controller
to handle the messaging. As long as I know, the purpose of this message
seems to notify lost of synchronization. While, the meaning of content
of the message is not clear.
Actual examples of this messaging:
* When clock source is set as internal:
- 0x00007051
- 0x00007052
- 0x00007054
- 0x00007057
- 0x00007058
* When clock source is set as somewhat external:
- 0x00009000
- 0x00009010
- 0x00009020
- 0x00009021
- 0x00009022
The lost often occurs when using internal clock source. In this case,
users hear sounds with quite short gap every several minutes. In fact,
the lost is recovered temporarily.
When using with external clock source, the lost seems not to occur. The
mechanism is not clear yet.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit adds hwdep interface so as the other sound drivers for units
on IEEE 1394 bus have.
This interface is designed for mixer/control applications. By using this
interface, an application can get information about firewire node, can
lock/unlock kernel streaming and can get notification at starting/stopping
kernel streaming.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit adds PCM functionality to transmit/receive PCM samples.
Any PCM substreams are jointed because incoming/outgoing AMDTP streams
are bound. When one of PCM substream is running or external clock source
is selected, current sampling rate is used. Else, the sampling rate is
changed as an userspace application requests.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit adds proc node to show current clock status for debugging.
As long as testing Digi 002 rack, registers can show local clock rate,
local clock source. When external clock input such as S/PDIF is
connected, the registers show the detection and external clock rate.
Additionally, the registers show the mode of optical digital input
interface. Although, a tester with Digi 003 rack reports this makes no
sense. Further investigation is required for Digi 003 series.
Besides, in Digi 002 rack, the S/PDIF format must be IEC 60958-4,
so-called professional.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit adds a functionality to manage streaming.
The streaming is not controlled by CMP in IEC 61883-6. It's controlled by
IEEE 1394 write transaction to certain addresses.
Several clock sources are available, while there're no differences about
packet transmission. The value of SYT field in transmitted packets is
always zero. Thus, streams in both direction don't build synchronization.
And the device always requires received packets to transmit packets. This
driver keeps to transfer outgoing stream even if they're not required.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit adds a new driver for Digidesign 002/003 family. This commit
just creates/removes card instance according to bus event. More functions
will be added in following commits.
Digidesign 002/003 family consists of:
* Agere FW802B for IEEE 1394 PHY layer
* PDI 1394L40 for IEEE 1394 LINK layer and IEC 61883 interface
* ALTERA ACEX EP1K50 for IEC 61883 layer and DSP controller
* ADSP-21065L for signal processing
[minor cleanup using skip_spaces() by tiwai]
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Takashi Sakamoto