Commit Graph

9401 Commits

Author SHA1 Message Date
Sergio Paracuellos 4b77e4abb3 PCI: mt7621: Drop of_match_ptr() to avoid unused variable
We have stubs for most OF interfaces even when CONFIG_OF is not set, so we
allow building of pcie-mt7621.c in that case for compile testing.

When CONFIG_OF is not set, "of_match_ptr(mt7621_pcie_ids)" compiles to
NULL, which leaves mt7621_pcie_ids unused:

  $ make W=1
  drivers/pci/controller/pcie-mt7621.c:549:34: warning: unused variable 'mt7621_pcie_ids' [-Wunused-const-variable]

Drop of_match_ptr() to avoid the unused variable warning.

[bhelgaas: commit log]
Fixes: 2bdd5238e7 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver")
Link: https://lore.kernel.org/r/20220124113003.406224-2-sergio.paracuellos@gmail.com
Link: https://lore.kernel.org/r/202201241754.igtHzgHv-lkp@intel.com
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-25 17:11:48 -06:00
Linus Torvalds ac5a9bb6b4 - A single use-after-free fix in the PCI MSI irq domain allocation path
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Merge tag 'irq_urgent_for_v5.17_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fix from Borislav Petkov:
 "A single use-after-free fix in the PCI MSI irq domain allocation path"

* tag 'irq_urgent_for_v5.17_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  PCI/MSI: Prevent UAF in error path
2022-01-23 17:45:00 +02:00
Linus Torvalds 3689f9f8b0 bitmap patches for 5.17-rc1
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Merge tag 'bitmap-5.17-rc1' of git://github.com/norov/linux

Pull bitmap updates from Yury Norov:

 - introduce for_each_set_bitrange()

 - use find_first_*_bit() instead of find_next_*_bit() where possible

 - unify for_each_bit() macros

* tag 'bitmap-5.17-rc1' of git://github.com/norov/linux:
  vsprintf: rework bitmap_list_string
  lib: bitmap: add performance test for bitmap_print_to_pagebuf
  bitmap: unify find_bit operations
  mm/percpu: micro-optimize pcpu_is_populated()
  Replace for_each_*_bit_from() with for_each_*_bit() where appropriate
  find: micro-optimize for_each_{set,clear}_bit()
  include/linux: move for_each_bit() macros from bitops.h to find.h
  cpumask: replace cpumask_next_* with cpumask_first_* where appropriate
  tools: sync tools/bitmap with mother linux
  all: replace find_next{,_zero}_bit with find_first{,_zero}_bit where appropriate
  cpumask: use find_first_and_bit()
  lib: add find_first_and_bit()
  arch: remove GENERIC_FIND_FIRST_BIT entirely
  include: move find.h from asm_generic to linux
  bitops: move find_bit_*_le functions from le.h to find.h
  bitops: protect find_first_{,zero}_bit properly
2022-01-23 06:20:44 +02:00
Muchun Song 359745d783 proc: remove PDE_DATA() completely
Remove PDE_DATA() completely and replace it with pde_data().

[akpm@linux-foundation.org: fix naming clash in drivers/nubus/proc.c]
[akpm@linux-foundation.org: now fix it properly]

Link: https://lkml.kernel.org/r/20211124081956.87711-2-songmuchun@bytedance.com
Signed-off-by: Muchun Song <songmuchun@bytedance.com>
Acked-by: Christian Brauner <christian.brauner@ubuntu.com>
Cc: Alexey Dobriyan <adobriyan@gmail.com>
Cc: Alexey Gladkov <gladkov.alexey@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2022-01-22 08:33:37 +02:00
Thomas Gleixner a0af3d1104 PCI/MSI: Prevent UAF in error path
When the core MSI allocation fails, then the PCI/MSI code uses an already
freed MSI descriptor to unmask the MSI mask register in order to bring it back
into reset state.

Remove MSI_FLAG_FREE_MSI_DESCS from the PCI/MSI irqdomain flags and let the
PCI/MSI code free the MSI descriptors after usage.

Fixes: 0f62d941ac ("genirq/msi: Provide msi_domain_alloc/free_irqs_descs_locked()")
Reported-by: Tong Zhang <ztong0001@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Tong Zhang <ztong0001@gmail.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/87r1938vbn.ffs@tglx
2022-01-21 02:14:46 +01:00
Linus Torvalds d0a231f01e pci-v5.17-changes
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Merge tag 'pci-v5.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull pci updates from Bjorn Helgaas:
 "Enumeration:
   - Use pci_find_vsec_capability() instead of open-coding it (Andy
     Shevchenko)
   - Convert pci_dev_present() stub from macro to static inline to avoid
     'unused variable' errors (Hans de Goede)
   - Convert sysfs slot attributes from default_attrs to default_groups
     (Greg Kroah-Hartman)
   - Use DWORD accesses for LTR, L1 SS to avoid BayHub OZ711LV2 erratum
     (Rajat Jain)
   - Remove unnecessary initialization of static variables (Longji Guo)

  Resource management:
   - Always write Intel I210 ROM BAR on update to work around device
     defect (Bjorn Helgaas)

  PCIe native device hotplug:
   - Fix pciehp lockdep errors on Thunderbolt undock (Hans de Goede)
   - Fix infinite loop in pciehp IRQ handler on power fault (Lukas
     Wunner)

  Power management:
   - Convert amd64-agp, sis-agp, via-agp from legacy PCI power
     management to generic power management (Vaibhav Gupta)

  IOMMU:
   - Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller
     so it can work with an IOMMU (Yifeng Li)

  Error handling:
   - Add PCI_ERROR_RESPONSE and related definitions for signaling and
     checking for transaction errors on PCI (Naveen Naidu)
   - Fabricate PCI_ERROR_RESPONSE data (~0) in config read wrappers,
     instead of in host controller drivers, when transactions fail on
     PCI (Naveen Naidu)
   - Use PCI_POSSIBLE_ERROR() to check for possible failure of config
     reads (Naveen Naidu)

  Peer-to-peer DMA:
   - Add Logan Gunthorpe as P2PDMA maintainer (Bjorn Helgaas)

  ASPM:
   - Calculate link L0s and L1 exit latencies when needed instead of
     caching them (Saheed O. Bolarinwa)
   - Calculate device L0s and L1 acceptable exit latencies when needed
     instead of caching them (Saheed O. Bolarinwa)
   - Remove struct aspm_latency since it's no longer needed (Saheed O.
     Bolarinwa)

  APM X-Gene PCIe controller driver:
   - Fix IB window setup, which was broken by the fact that IB resources
     are now sorted in address order instead of DT dma-ranges order (Rob
     Herring)

  Apple PCIe controller driver:
   - Enable clock gating to save power (Hector Martin)
   - Fix REFCLK1 enable/poll logic (Hector Martin)

  Broadcom STB PCIe controller driver:
   - Declare bitmap correctly for use by bitmap interfaces (Christophe
     JAILLET)
   - Clean up computation of legacy and non-legacy MSI bitmasks (Florian
     Fainelli)
   - Update suspend/resume/remove error handling to warn about errors
     and not fail the operation (Jim Quinlan)
   - Correct the "pcie" and "msi" interrupt descriptions in DT binding
     (Jim Quinlan)
   - Add DT bindings for endpoint voltage regulators (Jim Quinlan)
   - Split brcm_pcie_setup() into two functions (Jim Quinlan)
   - Add mechanism for turning on voltage regulators for connected
     devices (Jim Quinlan)
   - Turn voltage regulators for connected devices on/off when bus is
     added or removed (Jim Quinlan)
   - When suspending, don't turn off voltage regulators for wakeup
     devices (Jim Quinlan)

  Freescale i.MX6 PCIe controller driver:
   - Add i.MX8MM support (Richard Zhu)

  Freescale Layerscape PCIe controller driver:
   - Use DWC common ops instead of layerscape-specific link-up functions
     (Hou Zhiqiang)

  Intel VMD host bridge driver:
   - Honor platform ACPI _OSC feature negotiation for Root Ports below
     VMD (Kai-Heng Feng)
   - Add support for Raptor Lake SKUs (Karthik L Gopalakrishnan)
   - Reset everything below VMD before enumerating to work around
     failure to enumerate NVMe devices when guest OS reboots (Nirmal
     Patel)

  Bridge emulation (used by Marvell Aardvark and MVEBU):
   - Make emulated ROM BAR read-only by default (Pali Rohár)
   - Make some emulated legacy PCI bits read-only for PCIe devices (Pali
     Rohár)
   - Update reserved bits in emulated PCIe Capability (Pali Rohár)
   - Allow drivers to emulate different PCIe Capability versions (Pali
     Rohár)
   - Set emulated Capabilities List bit for all PCIe devices, since they
     must have at least a PCIe Capability (Pali Rohár)

  Marvell Aardvark PCIe controller driver:
   - Add bridge emulation definitions for PCIe DEVCAP2, DEVCTL2,
     DEVSTA2, LNKCAP2, LNKCTL2, LNKSTA2, SLTCAP2, SLTCTL2, SLTSTA2 (Pali
     Rohár)
   - Add aardvark support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2
     registers (Pali Rohár)
   - Clear all MSIs at setup to avoid spurious interrupts (Pali Rohár)
   - Disable bus mastering when unbinding host controller driver (Pali
     Rohár)
   - Mask all interrupts when unbinding host controller driver (Pali
     Rohár)
   - Fix memory leak in host controller unbind (Pali Rohár)
   - Assert PERST# when unbinding host controller driver (Pali Rohár)
   - Disable link training when unbinding host controller driver (Pali
     Rohár)
   - Disable common PHY when unbinding host controller driver (Pali
     Rohár)
   - Fix resource type checking to check only IORESOURCE_MEM, not
     IORESOURCE_MEM_64, which is a flavor of IORESOURCE_MEM (Pali Rohár)

  Marvell MVEBU PCIe controller driver:
   - Implement pci_remap_iospace() for ARM so mvebu can use
     devm_pci_remap_iospace() instead of the previous ARM-specific
     pci_ioremap_io() interface (Pali Rohár)
   - Use the standard pci_host_probe() instead of the device-specific
     mvebu_pci_host_probe() (Pali Rohár)
   - Replace all uses of ARM-specific pci_ioremap_io() with the ARM
     implementation of the standard pci_remap_iospace() interface and
     remove pci_ioremap_io() (Pali Rohár)
   - Skip initializing invalid Root Ports (Pali Rohár)
   - Check for errors from pci_bridge_emul_init() (Pali Rohár)
   - Ignore any bridges at non-zero function numbers (Pali Rohár)
   - Return ~0 data for invalid config read size (Pali Rohár)
   - Disallow mapping interrupts on emulated bridges (Pali Rohár)
   - Clear Root Port Memory & I/O Space Enable and Bus Master Enable at
     initialization (Pali Rohár)
   - Make type bits in Root Port I/O Base register read-only (Pali
     Rohár)
   - Disable Root Port windows when base/limit set to invalid values
     (Pali Rohár)
   - Set controller to Root Complex mode (Pali Rohár)
   - Set Root Port Class Code to PCI Bridge (Pali Rohár)
   - Update emulated Root Port secondary bus numbers to better reflect
     the actual topology (Pali Rohár)
   - Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so
     pci_reset_secondary_bus() can reset connected devices (Pali Rohár)
   - Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root
     Ports (Pali Rohár)
   - Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports
     (Pali Rohár)
   - Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on
     Armada XP and newer devices (Pali Rohár)
   - Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module
     (Pali Rohár)
   - Add support for compiling as a module (Pali Rohár)

  MediaTek PCIe controller driver:
   - Assert PERST# for 100ms to allow power and clock to stabilize
     (qizhong cheng)

  MediaTek PCIe Gen3 controller driver:
   - Disable Mediatek DVFSRC voltage request since lack of DVFSRC to
     respond to the request causes failure to exit L1 PM Substate
     (Jianjun Wang)

  MediaTek MT7621 PCIe controller driver:
   - Declare mt7621_pci_ops static (Sergio Paracuellos)
   - Give pcibios_root_bridge_prepare() access to host bridge windows
     (Sergio Paracuellos)
   - Move MIPS I/O coherency unit setup from driver to
     pcibios_root_bridge_prepare() (Sergio Paracuellos)
   - Add missing MODULE_LICENSE() (Sergio Paracuellos)
   - Allow COMPILE_TEST for all arches (Sergio Paracuellos)

  Microsoft Hyper-V host bridge driver:
   - Add hv-internal interfaces to encapsulate arch IRQ dependencies
     (Sunil Muthuswamy)
   - Add arm64 Hyper-V vPCI support (Sunil Muthuswamy)

  Qualcomm PCIe controller driver:
   - Undo PM setup in qcom_pcie_probe() error handling path (Christophe
     JAILLET)
   - Use __be16 type to store return value from cpu_to_be16()
     (Manivannan Sadhasivam)
   - Constify static dw_pcie_ep_ops (Rikard Falkeborn)

  Renesas R-Car PCIe controller driver:
   - Fix aarch32 abort handler so it doesn't check the wrong bus clock
     before accessing the host controller (Marek Vasut)

  TI Keystone PCIe controller driver:
   - Add register offset for ti,syscon-pcie-id and ti,syscon-pcie-mode
     DT properties (Kishon Vijay Abraham I)

  MicroSemi Switchtec management driver:
   - Add Gen4 automotive device IDs (Kelvin Cao)
   - Declare state_names[] as static so it's not allocated and
     initialized for every call (Kelvin Cao)

  Host controller driver cleanups:
   - Use of_device_get_match_data(), not of_match_device(), when we only
     need the device data in altera, artpec6, cadence, designware-plat,
     dra7xx, keystone, kirin (Fan Fei)
   - Drop pointless of_device_get_match_data() cast in j721e (Bjorn
     Helgaas)
   - Drop redundant struct device * from j721e since struct cdns_pcie
     already has one (Bjorn Helgaas)
   - Rename driver structs to *_pcie in intel-gw, iproc, ls-gen4,
     mediatek-gen3, microchip, mt7621, rcar-gen2, tegra194, uniphier,
     xgene, xilinx, xilinx-cpm for consistency across drivers (Fan Fei)
   - Fix invalid address space conversions in hisi, spear13xx (Bjorn
     Helgaas)

  Miscellaneous:
   - Sort Intel Device IDs by value (Andy Shevchenko)
   - Change Capability offsets to hex to match spec (Baruch Siach)
   - Correct misspellings (Krzysztof Wilczyński)
   - Terminate statement with semicolon in pci_endpoint_test.c (Ming
     Wang)"

* tag 'pci-v5.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (151 commits)
  PCI: mt7621: Allow COMPILE_TEST for all arches
  PCI: mt7621: Add missing MODULE_LICENSE()
  PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()
  PCI: Let pcibios_root_bridge_prepare() access bridge->windows
  PCI: mt7621: Declare mt7621_pci_ops static
  PCI: brcmstb: Do not turn off WOL regulators on suspend
  PCI: brcmstb: Add control of subdevice voltage regulators
  PCI: brcmstb: Add mechanism to turn on subdev regulators
  PCI: brcmstb: Split brcm_pcie_setup() into two funcs
  dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
  dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map.
  PCI: brcmstb: Fix function return value handling
  PCI: brcmstb: Do not use __GENMASK
  PCI: brcmstb: Declare 'used' as bitmap, not unsigned long
  PCI: hv: Add arm64 Hyper-V vPCI support
  PCI: hv: Make the code arch neutral by adding arch specific interfaces
  PCI: pciehp: Use down_read/write_nested(reset_lock) to fix lockdep errors
  x86/PCI: Remove initialization of static variables to false
  PCI: Use DWORD accesses for LTR, L1 SS to avoid erratum
  misc: pci_endpoint_test: Terminate statement with semicolon
  ...
2022-01-16 08:08:11 +02:00
Yury Norov b5c7e7ec7d all: replace find_next{,_zero}_bit with find_first{,_zero}_bit where appropriate
find_first{,_zero}_bit is a more effective analogue of 'next' version if
start == 0. This patch replaces 'next' with 'first' where things look
trivial.

Signed-off-by: Yury Norov <yury.norov@gmail.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2022-01-15 08:47:31 -08:00
Linus Torvalds 3fb561b1e0 - added support for more BCM47XX based devices
- added MIPS support for brcmstb PCIe controller
 - added Loongson 2K1000 reset driver
 - removed board support for rbtx4938/rbtx4939
 - removed support for TX4939 SoCs
 - fixes and cleanups
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Merge tag 'mips_5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - add support for more BCM47XX based devices

 - add MIPS support for brcmstb PCIe controller

 - add Loongson 2K1000 reset driver

 - remove board support for rbtx4938/rbtx4939

 - remove support for TX4939 SoCs

 - fixes and cleanups

* tag 'mips_5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (59 commits)
  MIPS: ath79: drop _machine_restart again
  PCI: brcmstb: Augment driver for MIPs SOCs
  MIPS: bmips: Remove obsolete DMA mapping support
  MIPS: bmips: Add support PCIe controller device nodes
  dt-bindings: PCI: Add compatible string for Brcmstb 74[23]5 MIPs SOCs
  MIPS: compressed: Fix build with ZSTD compression
  MIPS: BCM47XX: Add support for Netgear WN2500RP v1 & v2
  MIPS: BCM47XX: Add support for Netgear R6300 v1
  MIPS: BCM47XX: Add LEDs and buttons for Asus RTN-10U
  MIPS: BCM47XX: Add board entry for Linksys WRT320N v1
  MIPS: BCM47XX: Define Linksys WRT310N V2 buttons
  MIPS: Remove duplicated include in local.h
  MIPS: retire "asm/llsc.h"
  MIPS: rework local_t operation on MIPS64
  MIPS: fix local_{add,sub}_return on MIPS64
  mips/pci: remove redundant ret variable
  MIPS: Loongson64: Add missing of_node_put() in ls2k_reset_init()
  MIPS: new Kconfig option ZBOOT_LOAD_ADDRESS
  MIPS: enable both vmlinux.gz.itb and vmlinuz for generic
  MIPS: signal: Return immediately if call fails
  ...
2022-01-14 15:08:36 +01:00
Linus Torvalds feb7a43de5 Rework of the MSI interrupt infrastructure:
Treewide cleanup and consolidation of MSI interrupt handling in
   preparation for further changes in this area which are necessary to:
 
   - address existing shortcomings in the VFIO area
 
   - support the upcoming Interrupt Message Store functionality which
     decouples the message store from the PCI config/MMIO space
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Merge tag 'irq-msi-2022-01-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull MSI irq updates from Thomas Gleixner:
 "Rework of the MSI interrupt infrastructure.

  This is a treewide cleanup and consolidation of MSI interrupt handling
  in preparation for further changes in this area which are necessary
  to:

   - address existing shortcomings in the VFIO area

   - support the upcoming Interrupt Message Store functionality which
     decouples the message store from the PCI config/MMIO space"

* tag 'irq-msi-2022-01-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (94 commits)
  genirq/msi: Populate sysfs entry only once
  PCI/MSI: Unbreak pci_irq_get_affinity()
  genirq/msi: Convert storage to xarray
  genirq/msi: Simplify sysfs handling
  genirq/msi: Add abuse prevention comment to msi header
  genirq/msi: Mop up old interfaces
  genirq/msi: Convert to new functions
  genirq/msi: Make interrupt allocation less convoluted
  platform-msi: Simplify platform device MSI code
  platform-msi: Let core code handle MSI descriptors
  bus: fsl-mc-msi: Simplify MSI descriptor handling
  soc: ti: ti_sci_inta_msi: Remove ti_sci_inta_msi_domain_free_irqs()
  soc: ti: ti_sci_inta_msi: Rework MSI descriptor allocation
  NTB/msi: Convert to msi_on_each_desc()
  PCI: hv: Rework MSI handling
  powerpc/mpic_u3msi: Use msi_for_each-desc()
  powerpc/fsl_msi: Use msi_for_each_desc()
  powerpc/pasemi/msi: Convert to msi_on_each_dec()
  powerpc/cell/axon_msi: Convert to msi_on_each_desc()
  powerpc/4xx/hsta: Rework MSI handling
  ...
2022-01-13 09:05:29 -08:00
Bjorn Helgaas 87c7193163 Merge branch 'pci/driver-cleanup'
- Use of_device_get_match_data(), not of_match_device(), when we only need
  the device data in altera, artpec6, cadence, designware-plat, dra7xx,
  keystone, kirin (Fan Fei)

- Drop pointless of_device_get_match_data() cast in j721e (Bjorn Helgaas)

- Drop redundant struct device * from j721e since struct cdns_pcie already
  has one (Bjorn Helgaas)

- Rename driver structs to *_pcie in intel-gw, iproc, ls-gen4,
  mediatek-gen3, microchip, mt7621, rcar-gen2, tegra194, uniphier, xgene,
  xilinx, xilinx-cpm for consistency across drivers (Fan Fei)

- Fix invalid address space conversions in hisi, spear13xx (Bjorn Helgaas)

* pci/driver-cleanup:
  PCI: spear13xx: Avoid invalid address space conversions
  PCI: hisi: Avoid invalid address space conversions
  PCI: xilinx-cpm: Rename xilinx_cpm_pcie_port to xilinx_cpm_pcie
  PCI: xilinx: Rename xilinx_pcie_port to xilinx_pcie
  PCI: xgene: Rename xgene_pcie_port to xgene_pcie
  PCI: uniphier: Rename uniphier_pcie_priv to uniphier_pcie
  PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie
  PCI: rcar-gen2: Rename rcar_pci_priv to rcar_pci
  PCI: mt7621: Rename mt7621_pci_ to mt7621_pcie_
  PCI: microchip: Rename mc_port to mc_pcie
  PCI: mediatek-gen3: Rename mtk_pcie_port to mtk_gen3_pcie
  PCI: ls-gen4: Rename ls_pcie_g4 to ls_g4_pcie
  PCI: iproc: Rename iproc_pcie_pltfm_ to iproc_pltfm_pcie_
  PCI: iproc: Rename iproc_pcie_bcma_ to iproc_bcma_pcie_
  PCI: intel-gw: Rename intel_pcie_port to intel_pcie
  PCI: j721e: Drop redundant struct device *
  PCI: j721e: Drop pointless of_device_get_match_data() cast
  PCI: kirin: Prefer of_device_get_match_data()
  PCI: keystone: Prefer of_device_get_match_data()
  PCI: dra7xx: Prefer of_device_get_match_data()
  PCI: designware-plat: Prefer of_device_get_match_data()
  PCI: cadence: Prefer of_device_get_match_data()
  PCI: artpec6: Prefer of_device_get_match_data()
  PCI: altera: Prefer of_device_get_match_data()

# Conflicts:
#	drivers/pci/controller/pcie-mt7621.c
2022-01-13 09:57:53 -06:00
Bjorn Helgaas f5d3ca6fff Merge branch 'pci/errors'
- Add PCI_ERROR_RESPONSE and related definitions for signaling and checking
  for transaction errors on PCI (Naveen Naidu)

- Fabricate PCI_ERROR_RESPONSE data (~0) in config read wrappers, instead
  of in host controller drivers, when transactions fail on PCI (Naveen
  Naidu)

- Use PCI_POSSIBLE_ERROR() to check for possible failure of config reads
  (Naveen Naidu)

* pci/errors:
  PCI: xgene: Use PCI_ERROR_RESPONSE to identify config read errors
  PCI: hv: Use PCI_ERROR_RESPONSE to identify config read errors
  PCI: keystone: Use PCI_ERROR_RESPONSE to identify config read errors
  PCI: Use PCI_ERROR_RESPONSE to identify config read errors
  PCI: cpqphp: Use PCI_POSSIBLE_ERROR() to check config reads
  PCI/PME: Use PCI_POSSIBLE_ERROR() to check config reads
  PCI/DPC: Use PCI_POSSIBLE_ERROR() to check config reads
  PCI: pciehp: Use PCI_POSSIBLE_ERROR() to check config reads
  PCI: vmd: Use PCI_POSSIBLE_ERROR() to check config reads
  PCI/ERR: Use PCI_POSSIBLE_ERROR() to check config reads
  PCI: rockchip-host: Drop error data fabrication when config read fails
  PCI: rcar-host: Drop error data fabrication when config read fails
  PCI: altera: Drop error data fabrication when config read fails
  PCI: mvebu: Drop error data fabrication when config read fails
  PCI: aardvark: Drop error data fabrication when config read fails
  PCI: kirin: Drop error data fabrication when config read fails
  PCI: histb: Drop error data fabrication when config read fails
  PCI: exynos: Drop error data fabrication when config read fails
  PCI: mediatek: Drop error data fabrication when config read fails
  PCI: iproc: Drop error data fabrication when config read fails
  PCI: thunder: Drop error data fabrication when config read fails
  PCI: Drop error data fabrication when config read fails
  PCI: Use PCI_SET_ERROR_RESPONSE() for disconnected devices
  PCI: Set error response data when config read fails
  PCI: Add PCI_ERROR_RESPONSE and related definitions
2022-01-13 09:57:52 -06:00
Bjorn Helgaas da43f08db2 Merge branch 'pci/misc'
- Sort Intel Device IDs by value (Andy Shevchenko)

- Change Capability offsets to hex to match spec (Baruch Siach)

- Correct misspellings (Krzysztof Wilczyński)

- Terminate statement with semicolon in pci_endpoint_test.c (Ming Wang)

* pci/misc:
  misc: pci_endpoint_test: Terminate statement with semicolon
  PCI: Correct misspelled words
  PCI: Change capability register offsets to hex
  PCI: Sort Intel Device IDs by value
2022-01-13 09:57:52 -06:00
Bjorn Helgaas 2709f0338d Merge branch 'remotes/lorenzo/pci/bridge-emul'
- Make emulated ROM BAR read-only by default (Pali Rohár)

- Make some emulated legacy PCI bits read-only for PCIe devices (Pali
  Rohár)

- Update reserved bits in emulated PCIe Capability (Pali Rohár)

- Allow drivers to emulate different PCIe Capability versions (Pali Rohár)

- Set emulated Capabilities List bit for all PCIe devices, since they must
  have at least a PCIe Capability (Pali Rohár)

* remotes/lorenzo/pci/bridge-emul:
  PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device
  PCI: pci-bridge-emul: Correctly set PCIe capabilities
  PCI: pci-bridge-emul: Fix definitions of reserved bits
  PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space
  PCI: pci-bridge-emul: Make expansion ROM Base Address register read-only
2022-01-13 09:57:51 -06:00
Bjorn Helgaas a99f501f3e Merge branch 'remotes/lorenzo/pci/xilinx-nwl'
- Declare bitmap correctly and as part of struct nwl_msi managed resource
  (Christophe JAILLET)

* remotes/lorenzo/pci/xilinx-nwl:
  PCI: xilinx-nwl: Simplify code and fix a memory leak
2022-01-13 09:57:51 -06:00
Bjorn Helgaas 18b026da34 Merge branch 'remotes/lorenzo/pci/xgene'
- Use bitmap ops for MSI allocator (Christophe JAILLET)

- Fix IB window setup, which was broken by the fact that IB resources are
  now sorted in address order instead of DT dma-ranges order (Rob Herring)

* remotes/lorenzo/pci/xgene:
  PCI: xgene: Fix IB window setup
  PCI: xgene-msi: Use bitmap_zalloc() when applicable
2022-01-13 09:57:51 -06:00
Bjorn Helgaas ec5d85e7f0 Merge branch 'remotes/lorenzo/pci/vmd'
- Reset everything below VMD before enumerating to work around failure to
  enumerate NVMe devices when guest OS reboots (Nirmal Patel)

- Honor platform ACPI _OSC feature negotiation for Root Ports below VMD
  (Kai-Heng Feng)

- Add support for Raptor Lake SKUs (Karthik L Gopalakrishnan)

* remotes/lorenzo/pci/vmd:
  PCI: vmd: Add DID 8086:A77F for all Intel Raptor Lake SKU's
  PCI: vmd: Honor ACPI _OSC on PCIe features
  PCI: vmd: Clean up domain before enumeration
2022-01-13 09:57:50 -06:00
Bjorn Helgaas 4ceca42d39 Merge branch 'remotes/lorenzo/pci/rcar'
- Fix aarch32 abort handler so it doesn't check the wrong bus clock before
  accessing the host controller (Marek Vasut)

* remotes/lorenzo/pci/rcar:
  PCI: rcar: Check if device is runtime suspended instead of __clk_is_enabled()
2022-01-13 09:57:50 -06:00
Bjorn Helgaas f0eb209fed Merge branch 'remotes/lorenzo/pci/qcom'
- Undo PM setup in qcom_pcie_probe() error handling path (Christophe
  JAILLET)

- Use __be16 type to store return value from cpu_to_be16() (Manivannan
  Sadhasivam)

- Constify static dw_pcie_ep_ops (Rikard Falkeborn)

* remotes/lorenzo/pci/qcom:
  PCI: qcom-ep: Constify static dw_pcie_ep_ops
  PCI: qcom: Use __be16 type to store return value from cpu_to_be16()
  PCI: qcom: Fix an error handling path in 'qcom_pcie_probe()'
2022-01-13 09:57:50 -06:00
Bjorn Helgaas 0de15dbbd6 Merge branch 'remotes/lorenzo/pci/mvebu'
- Implement pci_remap_iospace() for ARM so mvebu can use
  devm_pci_remap_iospace() instead of the previous ARM-specific
  pci_ioremap_io() interface (Pali Rohár)

- Use the standard pci_host_probe() instead of the device-specific
  mvebu_pci_host_probe() (Pali Rohár)

- Replace all uses of ARM-specific pci_ioremap_io() with the
  ARM implementation of the standard pci_remap_iospace() interface and
  remove pci_ioremap_io() (Pali Rohár)

- Skip initializing invalid Root Ports (Pali Rohár)

- Check for errors from pci_bridge_emul_init() (Pali Rohár)

- Ignore any bridges at non-zero function numbers (Pali Rohár)

- Return ~0 data for invalid config read size (Pali Rohár)

- Disallow mapping interrupts on emulated bridges (Pali Rohár)

- Clear Root Port Memory & I/O Space Enable and Bus Master Enable at
  initialization (Pali Rohár)

- Make type bits in Root Port I/O Base register read-only (Pali Rohár)

- Disable Root Port windows when base/limit set to invalid values (Pali
  Rohár)

- Set controller to Root Complex mode (Pali Rohár)

- Set Root Port Class Code to PCI Bridge (Pali Rohár)

- Update emulated Root Port secondary bus numbers to better reflect the
  actual topology (Pali Rohár)

- Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so
  pci_reset_secondary_bus() can reset connected devices (Pali Rohár)

- Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root Ports
  (Pali Rohár)

- Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports (Pali
  Rohár)

- Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on Armada
  XP and newer devices (Pali Rohár)

- Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module (Pali
  Rohár)

- Add support for compiling as a module (Pali Rohár)

* remotes/lorenzo/pci/mvebu:
  PCI: mvebu: Add support for compiling driver as module
  bus: mvebu-mbus: Export symbols for public API window functions
  PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on emulated bridge
  PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridge
  PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridge
  PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge
  PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge
  PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge
  PCI: mvebu: Setup PCIe controller to Root Complex mode
  PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers
  PCI: mvebu: Do not modify PCI IO type bits in conf_write
  PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge
  PCI: mvebu: Disallow mapping interrupts on emulated bridges
  PCI: mvebu: Handle invalid size of read config request
  PCI: mvebu: Check that PCI bridge specified in DT has function number zero
  PCI: mvebu: Check for errors from pci_bridge_emul_init() call
  PCI: mvebu: Check for valid ports
  arm: ioremap: Remove unused ARM-specific function pci_ioremap_io()
  arm: ioremap: Replace pci_ioremap_io() usage by pci_remap_iospace()
  PCI: mvebu: Remove custom mvebu_pci_host_probe() function
  PCI: mvebu: Replace pci_ioremap_io() usage by devm_pci_remap_iospace()
  arm: ioremap: Implement standard PCI function pci_remap_iospace()
2022-01-13 09:57:49 -06:00
Bjorn Helgaas fc10f9d667 Merge branch 'pci/host/mt7621'
- Declare mt7621_pci_ops static (Sergio Paracuellos)

- Give pcibios_root_bridge_prepare() access to host bridge windows (Sergio
  Paracuellos)

- Move MIPS I/O coherency unit setup from driver to
  pcibios_root_bridge_prepare() (Sergio Paracuellos)

- Add missing MODULE_LICENSE() (Sergio Paracuellos)

- Allow COMPILE_TEST for all arches (Sergio Paracuellos)

* pci/host/mt7621:
  PCI: mt7621: Allow COMPILE_TEST for all arches
  PCI: mt7621: Add missing MODULE_LICENSE()
  PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()
  PCI: Let pcibios_root_bridge_prepare() access bridge->windows
  PCI: mt7621: Declare mt7621_pci_ops static
2022-01-13 09:57:49 -06:00
Bjorn Helgaas 96fe579384 Merge branch 'remotes/lorenzo/pci/mediatek-gen3'
- Disable Mediatek DVFSRC voltage request since lack of DVFSRC to respond
  to the request causes failure to exit L1 PM Substate (Jianjun Wang)

* remotes/lorenzo/pci/mediatek-gen3:
  PCI: mediatek-gen3: Disable DVFSRC voltage request
2022-01-13 09:57:48 -06:00
Bjorn Helgaas fd785c64f3 Merge branch 'remotes/lorenzo/pci/mediatek'
- Assert PERST# for 100ms to allow power and clock to stabilize (qizhong
  cheng)

* remotes/lorenzo/pci/mediatek:
  PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize
2022-01-13 09:57:48 -06:00
Bjorn Helgaas 0dfa6f6e68 Merge branch 'remotes/lorenzo/pci/keystone'
- Add register offset for ti,syscon-pcie-id and ti,syscon-pcie-mode DT
  properties (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/keystone:
  PCI: keystone: Use phandle argument from "ti,syscon-pcie-id"/"ti,syscon-pcie-mode"
  dt-bindings: PCI: ti,am65: Fix "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" to take argument
2022-01-13 09:57:48 -06:00
Bjorn Helgaas 6553ff3dd9 Merge branch 'pci/host/hv'
- Add hv-internal interfaces to encapsulate arch IRQ dependencies (Sunil
  Muthuswamy)

- Add arm64 Hyper-V vPCI support (Sunil Muthuswamy)

* pci/host/hv:
  PCI: hv: Add arm64 Hyper-V vPCI support
  PCI: hv: Make the code arch neutral by adding arch specific interfaces
2022-01-13 09:57:47 -06:00
Bjorn Helgaas 28b75189f0 Merge branch 'remotes/lorenzo/pci/endpoint'
- Return failure from pci_epc_set_msi() if no interrupts are available (Li
  Chen)

* remotes/lorenzo/pci/endpoint:
  PCI: endpoint: Return -EINVAL when interrupts num is smaller than 1
2022-01-13 09:57:47 -06:00
Bjorn Helgaas 2948ce70e6 Merge branch 'remotes/lorenzo/pci/dwc'
- Don't ioremap NULL when DT lacks ATU resource (Tim Harvey)

- Drop redundant qcom-ep error message for platform_get_irq_byname()
  failure (Krzysztof Wilczyński)

- Add i.MX8MM support (Richard Zhu)

- Use DWC common ops instead of layerscape-specific link-up functions (Hou
  Zhiqiang)

* remotes/lorenzo/pci/dwc:
  PCI: layerscape: Change to use the DWC common link-up check function
  PCI: imx: Add the imx8mm pcie support
  dt-bindings: imx6q-pcie: Add PHY phandles and name properties
  PCI: qcom-ep: Remove surplus dev_err() when using platform_get_irq_byname()
  PCI: dwc: Do not remap invalid res
2022-01-13 09:57:47 -06:00
Bjorn Helgaas c5f62d30e9 Merge branch 'pci/host/brcmstb'
- Declare bitmap correctly for use by bitmap interfaces (Christophe
  JAILLET)

- Clean up computation of legacy and non-legacy MSI bitmasks (Florian
  Fainelli)

- Update suspend/resume/remove error handling to warn about errors and not
  fail the operation (Jim Quinlan)

- Correct the "pcie" and "msi" interrupt descriptions in DT binding (Jim
  Quinlan)

- Add DT bindings for endpoint voltage regulators (Jim Quinlan)

- Split brcm_pcie_setup() into two functions (Jim Quinlan)

- Add mechanism for turning on voltage regulators for connected devices
  (Jim Quinlan)

- Turn voltage regulators for connected devices on/off when bus is added or
  removed (Jim Quinlan)

- When suspending, don't turn off voltage regulators for wakeup devices
  (Jim Quinlan)

* pci/host/brcmstb:
  PCI: brcmstb: Do not turn off WOL regulators on suspend
  PCI: brcmstb: Add control of subdevice voltage regulators
  PCI: brcmstb: Add mechanism to turn on subdev regulators
  PCI: brcmstb: Split brcm_pcie_setup() into two funcs
  dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
  dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map.
  PCI: brcmstb: Fix function return value handling
  PCI: brcmstb: Do not use __GENMASK
  PCI: brcmstb: Declare 'used' as bitmap, not unsigned long
2022-01-13 09:57:46 -06:00
Bjorn Helgaas 3164f27b5f Merge branch 'remotes/lorenzo/pci/apple'
- Enable clock gating to save power (Hector Martin)

- Fix REFCLK1 enable/poll logic (Hector Martin)

* remotes/lorenzo/pci/apple:
  PCI: apple: Fix REFCLK1 enable/poll logic
  PCI: apple: Enable clock gating
2022-01-13 09:57:46 -06:00
Bjorn Helgaas 800cee8b04 Merge branch 'remotes/lorenzo/pci/aardvark'
- Add bridge emulation definitions for PCIe DEVCAP2, DEVCTL2, DEVSTA2,
  LNKCAP2, LNKCTL2, LNKSTA2, SLTCAP2, SLTCTL2, SLTSTA2 (Pali Rohár)

- Add aardvark support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers
  (Pali Rohár)

- Clear all MSIs at setup to avoid spurious interrupts (Pali Rohár)

- Disable bus mastering when unbinding host controller driver (Pali Rohár)

- Mask all interrupts when unbinding host controller driver (Pali Rohár)

- Fix memory leak in host controller unbind (Pali Rohár)

- Assert PERST# when unbinding host controller driver (Pali Rohár)

- Disable link training when unbinding host controller driver (Pali Rohár)

- Disable common PHY when unbinding host controller driver (Pali Rohár)

- Fix resource type checking to check only IORESOURCE_MEM, not
  IORESOURCE_MEM_64, which is a flavor of IORESOURCE_MEM (Pali Rohár)

* remotes/lorenzo/pci/aardvark:
  PCI: aardvark: Fix checking for MEM resource type
  PCI: aardvark: Disable common PHY when unbinding driver
  PCI: aardvark: Disable link training when unbinding driver
  PCI: aardvark: Assert PERST# when unbinding driver
  PCI: aardvark: Fix memory leak in driver unbind
  PCI: aardvark: Mask all interrupts when unbinding driver
  PCI: aardvark: Disable bus mastering when unbinding driver
  PCI: aardvark: Comment actions in driver remove method
  PCI: aardvark: Clear all MSIs at setup
  PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge
  PCI: pci-bridge-emul: Add definitions for missing capabilities registers
  PCI: pci-bridge-emul: Add description for class_revision field
2022-01-13 09:57:46 -06:00
Bjorn Helgaas d03f92c43f Merge branch 'pci/virtualization'
- Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller so it
  can work with an IOMMU (Yifeng Li)

* pci/virtualization:
  PCI: Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller
2022-01-13 09:57:45 -06:00
Bjorn Helgaas 54f98a8b13 Merge branch 'pci/switchtec'
- Add Gen4 automotive device IDs (Kelvin Cao)

- Declare state_names[] as static so it's not allocated and initialized for
  every call (Kelvin Cao)

* pci/switchtec:
  PCI/switchtec: Declare local state_names[] as static
  PCI/switchtec: Add Gen4 automotive device IDs
2022-01-13 09:57:45 -06:00
Bjorn Helgaas 05642e2f64 Merge branch 'pci/resource'
- Always write Intel I210 ROM BAR on update to work around device defect
  (Bjorn Helgaas)

* pci/resource:
  PCI: Work around Intel I210 ROM BAR overlap defect
2022-01-13 09:57:45 -06:00
Bjorn Helgaas c6ff0f8dc0 Merge branch 'pci/p2pdma'
- Add Logan Gunthorpe as P2PDMA maintainer (Bjorn Helgaas)

- Optimize by using percpu_ref_tryget_live_rcu() inside RCU critical
  section (Christophe JAILLET)

* pci/p2pdma:
  PCI/P2PDMA: Use percpu_ref_tryget_live_rcu() inside RCU critical section
  MAINTAINERS: Add Logan Gunthorpe as P2PDMA maintainer
2022-01-13 09:57:44 -06:00
Bjorn Helgaas 7475f9319a Merge branch 'pci/hotplug'
- Fix infinite loop in pciehp IRQ handler on power fault (Lukas Wunner)

- Removed commented-out ibmphp functions (Vihas Mak)

- Fix pciehp lockdep errors on Thunderbolt undock (Hans de Goede)

* pci/hotplug:
  PCI: pciehp: Use down_read/write_nested(reset_lock) to fix lockdep errors
  PCI: ibmphp: Remove commented-out functions
  PCI: pciehp: Fix infinite loop in IRQ handler upon power fault
2022-01-13 09:57:43 -06:00
Bjorn Helgaas fb6c45130a Merge branch 'pci/enumeration'
- Use pci_find_vsec_capability() instead of open-coding it (Andy
  Shevchenko)

- Convert pci_dev_present() stub from macro to static inline to avoid
  'unused variable' errors (Hans de Goede)

- Convert sysfs slot attributes from default_attrs to default_groups (Greg
  Kroah-Hartman)

- Use DWORD accesses for LTR, L1 SS to avoid BayHub OZ711LV2 erratum (Rajat
  Jain)

- Remove unnecessary initialization of static variables (Longji Guo)

* pci/enumeration:
  x86/PCI: Remove initialization of static variables to false
  PCI: Use DWORD accesses for LTR, L1 SS to avoid erratum
  PCI/sysfs: Use default_groups in kobj_type for slot attrs
  PCI: Convert pci_dev_present() stub to static inline
  PCI: Use pci_find_vsec_capability() when looking for TBT devices
2022-01-13 09:57:43 -06:00
Linus Torvalds 3acbdbf42e dax + libnvdimm for v5.17
- Simplify the dax_operations API
   - Eliminate bdev_dax_pgoff() in favor of the filesystem maintaining
     and applying a partition offset to all its DAX iomap operations.
   - Remove wrappers and device-mapper stacked callbacks for
     ->copy_from_iter() and ->copy_to_iter() in favor of moving
     block_device relative offset responsibility to the
     dax_direct_access() caller.
   - Remove the need for an @bdev in filesystem-DAX infrastructure
   - Remove unused uio helpers copy_from_iter_flushcache() and
     copy_mc_to_iter() as only the non-check_copy_size() versions are
     used for DAX.
 - Prepare XFS for the pending (next merge window) DAX+reflink support
 - Remove deprecated DEV_DAX_PMEM_COMPAT support
 - Cleanup a straggling misuse of the GUID api
 
 Tags offered after the branch was cut:
 Reviewed-by: Mike Snitzer <snitzer@redhat.com>
 Link: https://lore.kernel.org/r/Ydb/3P+8nvjCjYfO@redhat.com
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Merge tag 'libnvdimm-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm

Pull dax and libnvdimm updates from Dan Williams:
 "The bulk of this is a rework of the dax_operations API after
  discovering the obstacles it posed to the work-in-progress DAX+reflink
  support for XFS and other copy-on-write filesystem mechanics.

  Primarily the need to plumb a block_device through the API to handle
  partition offsets was a sticking point and Christoph untangled that
  dependency in addition to other cleanups to make landing the
  DAX+reflink support easier.

  The DAX_PMEM_COMPAT option has been around for 4 years and not only
  are distributions shipping userspace that understand the current
  configuration API, but some are not even bothering to turn this option
  on anymore, so it seems a good time to remove it per the deprecation
  schedule. Recall that this was added after the device-dax subsystem
  moved from /sys/class/dax to /sys/bus/dax for its sysfs organization.
  All recent functionality depends on /sys/bus/dax.

  Some other miscellaneous cleanups and reflink prep patches are
  included as well.

  Summary:

   - Simplify the dax_operations API:

      - Eliminate bdev_dax_pgoff() in favor of the filesystem
        maintaining and applying a partition offset to all its DAX iomap
        operations.

      - Remove wrappers and device-mapper stacked callbacks for
        ->copy_from_iter() and ->copy_to_iter() in favor of moving
        block_device relative offset responsibility to the
        dax_direct_access() caller.

      - Remove the need for an @bdev in filesystem-DAX infrastructure

      - Remove unused uio helpers copy_from_iter_flushcache() and
        copy_mc_to_iter() as only the non-check_copy_size() versions are
        used for DAX.

   - Prepare XFS for the pending (next merge window) DAX+reflink support

   - Remove deprecated DEV_DAX_PMEM_COMPAT support

   - Cleanup a straggling misuse of the GUID api"

* tag 'libnvdimm-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm: (38 commits)
  iomap: Fix error handling in iomap_zero_iter()
  ACPI: NFIT: Import GUID before use
  dax: remove the copy_from_iter and copy_to_iter methods
  dax: remove the DAXDEV_F_SYNC flag
  dax: simplify dax_synchronous and set_dax_synchronous
  uio: remove copy_from_iter_flushcache() and copy_mc_to_iter()
  iomap: turn the byte variable in iomap_zero_iter into a ssize_t
  memremap: remove support for external pgmap refcounts
  fsdax: don't require CONFIG_BLOCK
  iomap: build the block based code conditionally
  dax: fix up some of the block device related ifdefs
  fsdax: shift partition offset handling into the file systems
  dax: return the partition offset from fs_dax_get_by_bdev
  iomap: add a IOMAP_DAX flag
  xfs: pass the mapping flags to xfs_bmbt_to_iomap
  xfs: use xfs_direct_write_iomap_ops for DAX zeroing
  xfs: move dax device handling into xfs_{alloc,free}_buftarg
  ext4: cleanup the dax handling in ext4_fill_super
  ext2: cleanup the dax handling in ext2_fill_super
  fsdax: decouple zeroing from the iomap buffered I/O code
  ...
2022-01-12 15:46:11 -08:00
Sergio Paracuellos 44ddb791f8 PCI: mt7621: Allow COMPILE_TEST for all arches
Since all MIPS-specific code has been removed from driver, allow it to be
enabled for COMPILE_TEST on all architectures.

Mark it as tristate and remove MIPS the MIPS dependency.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12 15:46:56 -06:00
Sergio Paracuellos e4b1cd02dc PCI: mt7621: Add missing MODULE_LICENSE()
The MT7621 PCIe host controller driver can be built as a module, but it
lacks a MODULE_LICENSE(), which causes a build error:

  ERROR: modpost: missing MODULE_LICENSE() in drivers/pci/controller/pcie-mt7621.o

Add MODULE_LICENSE() to the driver.

Fixes: 2bdd5238e7 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver")
Link: https://lore.kernel.org/r/20211207104924.21327-5-sergio.paracuellos@gmail.com
Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
2022-01-12 15:46:56 -06:00
Sergio Paracuellos fe7498ef79 PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()
On the MIPS ralink mt7621 platform, we need to set up I/O coherency units
based on the host bridge apertures.

To remove this arch dependency from the driver itself, move the coherency
setup from the driver to pcibios_root_bridge_prepare().

[bhelgaas: squash add/remove into one patch, commit log]
Link: https://lore.kernel.org/r/20211207104924.21327-3-sergio.paracuellos@gmail.com
Link: https://lore.kernel.org/r/20211207104924.21327-4-sergio.paracuellos@gmail.com
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>             # arch/mips
Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>   # arch/mips
2022-01-12 15:38:20 -06:00
Sergio Paracuellos 661c4c4f26 PCI: Let pcibios_root_bridge_prepare() access bridge->windows
When pci_register_host_bridge() is called, bridge->windows are already
available. However these windows are being moved temporarily from there.

To let pcibios_root_bridge_prepare() have access to these windows, move the
windows movement after calling this function. This is useful for the MIPS
ralink mt7621 platform so it can set up I/O coherence units and avoid
custom MIPS code in the mt7621 PCIe controller driver.

Link: https://lore.kernel.org/r/20211207104924.21327-2-sergio.paracuellos@gmail.com
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2022-01-12 15:37:10 -06:00
Sergio Paracuellos da48157092 PCI: mt7621: Declare mt7621_pci_ops static
Sparse complains about mt7621_pci_ops symbol is not declared and asks if
it should be declared as static instead. Sparse is right. Hence declare
symbol as static.

Link: https://lore.kernel.org/r/20211117152952.12271-1-sergio.paracuellos@gmail.com
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
2022-01-12 15:22:32 -06:00
Jim Quinlan 11ed8b8624 PCI: brcmstb: Do not turn off WOL regulators on suspend
If any downstream device can be a wakeup device, do not turn off the
regulators as the device will need them on.

Link: https://lore.kernel.org/r/20220106160332.2143-8-jim2101024@gmail.com
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12 13:45:50 -06:00
Jim Quinlan 93e41f3fca PCI: brcmstb: Add control of subdevice voltage regulators
This Broadcom STB PCIe RC driver has one port and connects directly to one
device, be it a switch or an endpoint.  We want to be able to leverage the
recently added mechanism that allocates and turns on/off subdevice
regulators.

All that needs to be done is to put the regulator DT nodes in the bridge
below host and to set the pci_ops methods add_bus and remove_bus.

Note that the pci_subdev_regulators_add_bus() method is wrapped for two
reasons:

   1. To achieve link up after the voltage regulators are turned on.

   2. If, in the case of an unsuccessful link up, to redirect any PCIe
      accesses to subdevices, e.g. the scan for DEV/ID.  This redirection
      is needed because the Broadcom PCIe HW will issue a CPU abort if such
      an access is made when the link is down.

[bhelgaas: fold in
https://lore.kernel.org/r/20220112013100.48029-1-jim2101024@gmail.com]
Link: https://lore.kernel.org/r/20220106160332.2143-7-jim2101024@gmail.com
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12 13:45:50 -06:00
Jim Quinlan 67211aadcb PCI: brcmstb: Add mechanism to turn on subdev regulators
Add a mechanism to identify standard PCIe regulators in the DT, allocate
them, and turn them on before the rest of the bus is scanned during
pci_host_probe().

The allocated structure that contains the regulators is stored in the port
driver dev.driver_data field.  Here is a point-by-point of how and when
this mechanism is activated:

If:
    -- PCIe RC driver sets pci_ops {add,remove)_bus to
       pci_subdev_regulators_{add,remove}_bus during its probe.
    -- There is a DT node "RB" under the host bridge DT node.
    -- During the RC driver's pci_host_probe() the add_bus callback
       is invoked where (bus->parent && pci_is_root_bus(bus->parent)
       is true

Then:
    -- A struct subdev_regulators structure will be allocated and
       assigned to bus->dev.driver_data.
    -- regulator_bulk_{get,enable} will be invoked on &bus->dev
       and the former will search for and process any
       vpcie{12v,3v3,3v3aux}-supply properties that reside in node "RB".
    -- The regulators will be turned off/on for any unbind/bind operations.
    -- The regulators will be turned off/on for any suspend/resumes, but
       only if the RC driver handles this on its own.  This will appear
       in a later commit for the pcie-brcmstb.c driver.

The unabridged reason for doing this is as follows.  We would like the
Broadcom STB PCIe root complex driver (and others) to be able to turn
off/on regulators[1] that provide power to endpoint[2] devices.  Typically,
the drivers of these endpoint devices are stock Linux drivers that are not
aware that these regulator(s) exist and must be turned on for the driver to
be probed.  The simple solution of course is to turn these regulators on at
boot and keep them on.  However, this solution does not satisfy at least
three of our usage modes:

  1. For example, one customer uses multiple PCIe controllers, but wants
     the ability to, by script invoking and unbind, turn any or all of them
     and their subdevices off to save power, e.g. when in battery mode.

  2. Another example is when a watchdog script discovers that an endpoint
     device is in an unresponsive state and would like to unbind, power
     toggle, and re-bind just the PCIe endpoint and controller.

  3. Of course we also want power turned off during suspend mode.  However,
     some endpoint devices may be able to "wake" during suspend and we need
     to recognise this case and veto the nominal act of turning off its
     regulator.  Such is the case with Wake-on-LAN and Wake-on-WLAN support
     where the PCIe endpoint device needs to be kept powered on in order to
     receive network packets and wake the system.

In all of these cases it is advantageous for the PCIe controller to govern
the turning off/on the regulators needed by the endpoint device.  The first
two cases can be done by simply unbinding and binding the PCIe controller,
if the controller has control of these regulators.

[1] These regulators typically govern the actual power supply to the
    endpoint chip.  Sometimes they may be the official PCIe socket
    power -- such as 3.3v or aux-3.3v.  Sometimes they are truly
    the regulator(s) that supply power to the EP chip.

[2] The 99% configuration of our boards is a single endpoint device
    attached to the PCIe controller.  I use the term endpoint but it could
    possibly mean a switch as well.

Link: https://lore.kernel.org/r/20220106160332.2143-6-jim2101024@gmail.com
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12 13:45:50 -06:00
Jim Quinlan 830aa6f29f PCI: brcmstb: Split brcm_pcie_setup() into two funcs
We need to take some code in brcm_pcie_setup() and put it in a new function
brcm_pcie_linkup().  In future commits the brcm_pcie_linkup() function will
be called indirectly by pci_host_probe() as opposed to the host driver
invoking it directly.

Some code that was executed after the PCIe linkup is now placed so that it
executes prior to linkup, since this code has to run prior to the
invocation of pci_host_probe().

Link: https://lore.kernel.org/r/20220106160332.2143-5-jim2101024@gmail.com
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12 13:45:50 -06:00
Jim Quinlan 41ac424ac1 PCI: brcmstb: Fix function return value handling
Do at least a dev_err() on some calls to reset_control_rearm() and
brcm_phy_stop().  In some cases it may not make sense to return this error
value "above" as doing so will cause more trouble than is warranted.

Link: https://lore.kernel.org/r/20220106160332.2143-2-jim2101024@gmail.com
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2022-01-12 13:45:49 -06:00
Florian Fainelli 09a710d952 PCI: brcmstb: Do not use __GENMASK
Define the legacy MSI interrupt bitmask as well as the non-legacy interrupt
bitmask using GENMASK and then use them in brcm_msi_set_regs() in place of
__GENMASK().

Link: https://lore.kernel.org/r/20211122190459.3189616-1-f.fainelli@gmail.com
Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2022-01-12 13:45:49 -06:00
Christophe JAILLET bf73258825 PCI: brcmstb: Declare 'used' as bitmap, not unsigned long
The 'used' field of 'struct brcm_msi' is used as a bitmap.  Declare it with
DECLARE_BITMAP() and adjust users accordingly.

This fixes a harmless Coverity warning about array vs singleton usage.

This bitmap can be used for either legacy or MSI interrupts, which require
a size of BRCM_INT_PCI_MSI_LEGACY_NR or BRCM_INT_PCI_MSI_NR respectively.
Add a BUILD_BUG_ON() to ensure it is large enough.

Suggested-by: Krzysztof Wilczynski <kw@linux.com>
Addresses-Coverity: "Out-of-bounds access (ARRAY_VS_SINGLETON)"
Link: https://lore.kernel.org/r/e6d9da2112aab2939d1507b90962d07bfd735b4c.1636273671.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
2022-01-12 13:45:36 -06:00
Sunil Muthuswamy d9932b4691 PCI: hv: Add arm64 Hyper-V vPCI support
Add arm64 Hyper-V vPCI support by implementing the arch specific
interfaces. Introduce an IRQ domain and chip specific to Hyper-v vPCI that
is based on SPIs. The IRQ domain parents itself to the arch GIC IRQ domain
for basic vector management.

[bhelgaas: squash in fix from Yang Li <yang.lee@linux.alibaba.com>:
https://lore.kernel.org/r/20220112003324.62755-1-yang.lee@linux.alibaba.com]
Link: https://lore.kernel.org/r/1641411156-31705-3-git-send-email-sunilmut@linux.microsoft.com
Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
2022-01-12 08:24:29 -06:00
Sunil Muthuswamy 831c1ae725 PCI: hv: Make the code arch neutral by adding arch specific interfaces
Encapsulate arch dependencies in Hyper-V vPCI through a set of
arch-dependent interfaces. Adding these arch specific interfaces will
allow for an implementation for other architectures, such as arm64.

There are no functional changes expected from this patch.

Link: https://lore.kernel.org/r/1641411156-31705-2-git-send-email-sunilmut@linux.microsoft.com
Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Boqun Feng <boqun.feng@gmail.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
2022-01-12 08:21:54 -06:00
Hans de Goede 085a9f4343 PCI: pciehp: Use down_read/write_nested(reset_lock) to fix lockdep errors
Use down_read_nested() and down_write_nested() when taking the
ctrl->reset_lock rw-sem, passing the number of PCIe hotplug controllers in
the path to the PCI root bus as lock subclass parameter.

This fixes the following false-positive lockdep report when unplugging a
Lenovo X1C8 from a Lenovo 2nd gen TB3 dock:

  pcieport 0000:06:01.0: pciehp: Slot(1): Link Down
  pcieport 0000:06:01.0: pciehp: Slot(1): Card not present
  ============================================
  WARNING: possible recursive locking detected
  5.16.0-rc2+ #621 Not tainted
  --------------------------------------------
  irq/124-pciehp/86 is trying to acquire lock:
  ffff8e5ac4299ef8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_check_presence+0x23/0x80

  but task is already holding lock:
  ffff8e5ac4298af8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_ist+0xf3/0x180

   other info that might help us debug this:
   Possible unsafe locking scenario:

	 CPU0
	 ----
    lock(&ctrl->reset_lock);
    lock(&ctrl->reset_lock);

   *** DEADLOCK ***

   May be due to missing lock nesting notation

  3 locks held by irq/124-pciehp/86:
   #0: ffff8e5ac4298af8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_ist+0xf3/0x180
   #1: ffffffffa3b024e8 (pci_rescan_remove_lock){+.+.}-{3:3}, at: pciehp_unconfigure_device+0x31/0x110
   #2: ffff8e5ac1ee2248 (&dev->mutex){....}-{3:3}, at: device_release_driver+0x1c/0x40

  stack backtrace:
  CPU: 4 PID: 86 Comm: irq/124-pciehp Not tainted 5.16.0-rc2+ #621
  Hardware name: LENOVO 20U90SIT19/20U90SIT19, BIOS N2WET30W (1.20 ) 08/26/2021
  Call Trace:
   <TASK>
   dump_stack_lvl+0x59/0x73
   __lock_acquire.cold+0xc5/0x2c6
   lock_acquire+0xb5/0x2b0
   down_read+0x3e/0x50
   pciehp_check_presence+0x23/0x80
   pciehp_runtime_resume+0x5c/0xa0
   device_for_each_child+0x45/0x70
   pcie_port_device_runtime_resume+0x20/0x30
   pci_pm_runtime_resume+0xa7/0xc0
   __rpm_callback+0x41/0x110
   rpm_callback+0x59/0x70
   rpm_resume+0x512/0x7b0
   __pm_runtime_resume+0x4a/0x90
   __device_release_driver+0x28/0x240
   device_release_driver+0x26/0x40
   pci_stop_bus_device+0x68/0x90
   pci_stop_bus_device+0x2c/0x90
   pci_stop_and_remove_bus_device+0xe/0x20
   pciehp_unconfigure_device+0x6c/0x110
   pciehp_disable_slot+0x5b/0xe0
   pciehp_handle_presence_or_link_change+0xc3/0x2f0
   pciehp_ist+0x179/0x180

This lockdep warning is triggered because with Thunderbolt, hotplug ports
are nested. When removing multiple devices in a daisy-chain, each hotplug
port's reset_lock may be acquired recursively. It's never the same lock, so
the lockdep splat is a false positive.

Because locks at the same hierarchy level are never acquired recursively, a
per-level lockdep class is sufficient to fix the lockdep warning.

The choice to use one lockdep subclass per pcie-hotplug controller in the
path to the root-bus was made to conserve class keys because their number
is limited and the complexity grows quadratically with number of keys
according to Documentation/locking/lockdep-design.rst.

Link: https://lore.kernel.org/linux-pci/20190402021933.GA2966@mit.edu/
Link: https://lore.kernel.org/linux-pci/de684a28-9038-8fc6-27ca-3f6f2f6400d7@redhat.com/
Link: https://lore.kernel.org/r/20211217141709.379663-1-hdegoede@redhat.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=208855
Reported-by: "Theodore Ts'o" <tytso@mit.edu>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lukas Wunner <lukas@wunner.de>
Cc: stable@vger.kernel.org
2022-01-12 06:42:51 -06:00
Rajat Jain 4353594eb0 PCI: Use DWORD accesses for LTR, L1 SS to avoid erratum
Some devices have an erratum such that they only support DWORD accesses to
some registers.  E.g., this Bayhub O2 device ([VID:DID] = [0x1217:0x8621])
only supports DWORD accesses to LTR latency registers and L1 PM substates
control registers:

  https://github.com/rajatxjain/public_shared/blob/main/OZ711LV2_appnote.pdf

The L1 PM substate control registers are DWORD sized, and hence their
access in the kernel is already DWORD sized, so we don't need to do
anything for them.

However, the LTR registers being WORD sized, are in need of a solution.
Convert the WORD sized accesses to these registers into DWORD sized
accesses while saving and restoring them.

Link: https://lore.kernel.org/r/20211222012105.3438916-1-rajatja@google.com
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-11 10:41:24 -06:00
Bjorn Helgaas 500b55b05d PCI: Work around Intel I210 ROM BAR overlap defect
Per PCIe r5, sec 7.5.1.2.4, a device must not claim accesses to its
Expansion ROM unless both the Memory Space Enable and the Expansion ROM
Enable bit are set.  But apparently some Intel I210 NICs don't work
correctly if the ROM BAR overlaps another BAR, even if the Expansion ROM is
disabled.

Michael reported that on a Kontron SMARC-sAL28 ARM64 system with U-Boot
v2021.01-rc3, the ROM BAR overlaps BAR 3, and networking doesn't work at
all:

  BAR 0: 0x40000000 (32-bit, non-prefetchable) [size=1M]
  BAR 3: 0x40200000 (32-bit, non-prefetchable) [size=16K]
  ROM:   0x40200000 (disabled) [size=1M]

  NETDEV WATCHDOG: enP2p1s0 (igb): transmit queue 0 timed out
  Hardware name: Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier (DT)
  igb 0002:01:00.0 enP2p1s0: Reset adapter

Previously, pci_std_update_resource() wrote the assigned ROM address to the
BAR only when the ROM was enabled.  This meant that the I210 ROM BAR could
be left with an address assigned by firmware, which might overlap with
other BARs.

Quirk these I210 devices so pci_std_update_resource() always writes the
assigned address to the ROM BAR, whether or not the ROM is enabled.

Link: https://lore.kernel.org/r/20211223163754.GA1267351@bhelgaas
Link: https://lore.kernel.org/r/20201230185317.30915-1-michael@walle.cc
Link: https://bugzilla.kernel.org/show_bug.cgi?id=211105
Reported-by: Michael Walle <michael@walle.cc>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-11 09:33:10 -06:00
Jim Quinlan aa8589aac8 PCI: brcmstb: Augment driver for MIPs SOCs
The current brcmstb driver works for Arm and Arm64.  A few things are
modified here for us to support MIPs as well.

  o There are four outbound range register groups and each directs a window
    of up to 128MB.  Even though there are four 128MB DT "ranges" in the
    bmips PCIe DT node, these ranges are contiguous and are collapsed into
    a single range by the OF range parser.  Now the driver assumes a single
    range -- for MIPs only -- and splits it back into 128MB sizes.

  o For bcm7425, the config space accesses must be 32-bit reads or
    writes.  In addition, the 4k config space register array is missing
    and not used.

  o The registers for the upper 32-bits of the outbound window address do
    not exist.

  o Burst size must be set to 256 (this refers to an internal bus).

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-01-11 11:55:41 +01:00
Linus Torvalds fe8152b38d Device properties framework updates for 5.17-rc1
- Remove device_add_properties() which does not work correctly if
    software nodes holding additional device properties are shared
    or reused (Heikki Krogerus).
 
  - Fix nargs_prop property handling for software nodes (Clément Léger).
 
  - Update documentation of ACPI device properties (Sakari Ailus).
 
  - Update the handling of graph properties in the generic framework
    to match the DT case (Sakari Ailus).
 
  - Update software nodes entry in MAINTAINERS (Andy Shevchenko).
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Merge tag 'devprop-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull device properties framework updates from Rafael Wysocki:
 "These update the handling of software nodes and graph properties, and
  the MAINTAINERS entry for the former.

  Specifics:

   - Remove device_add_properties() which does not work correctly if
     software nodes holding additional device properties are shared or
     reused (Heikki Krogerus).

   - Fix nargs_prop property handling for software nodes (Clément
     Léger).

   - Update documentation of ACPI device properties (Sakari Ailus).

   - Update the handling of graph properties in the generic framework to
     match the DT case (Sakari Ailus).

   - Update software nodes entry in MAINTAINERS (Andy Shevchenko)"

* tag 'devprop-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
  software node: Update MAINTAINERS data base
  software node: fix wrong node passed to find nargs_prop
  device property: Drop fwnode_graph_get_remote_node()
  device property: Use fwnode_graph_for_each_endpoint() macro
  device property: Implement fwnode_graph_get_endpoint_count()
  Documentation: ACPI: Update references
  Documentation: ACPI: Fix data node reference documentation
  device property: Fix documentation for FWNODE_GRAPH_DEVICE_DISABLED
  device property: Fix fwnode_graph_devcon_match() fwnode leak
  device property: Remove device_add_properties() API
  driver core: Don't call device_remove_properties() from device_del()
  PCI: Convert to device_create_managed_software_node()
2022-01-10 20:48:19 -08:00
Krzysztof Wilczyński ccd36795be PCI: Correct misspelled words
Fix a number of misspelled words, and while at it, correct two phrases used
to indicate a status of an operation where words used have been cleverly
truncated and thus always trigger a spellchecking error while performing a
static code analysis over the PCI tree.

[bhelgaas: reverse sense of quirk ternary]
Link: https://lore.kernel.org/r/20220107225942.121484-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-07 20:43:23 -06:00
Kishon Vijay Abraham I 7dcf07ac88 PCI: keystone: Use phandle argument from "ti,syscon-pcie-id"/"ti,syscon-pcie-mode"
Get "syscon" pcie_mode and pcie_id offset from the argument of
"ti,syscon-pcie-id" and "ti,syscon-pcie-mode" phandle respectively.
Previously a subnode to "syscon" node was added which has the
exact memory mapped address of pcie_mode and pcie_id but now the
offset of pcie_mode and pcie_id within "syscon" is now being passed
as argument to "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" phandle.

If the offset is not provided in "ti,syscon-pcie-id"/"ti,syscon-pcie-mode",
the full memory mapped address of pcie_ctrl is used in order to maintain
old DT compatibility.

Similar change for J721E is as discussed in [1]

[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Link: https://lore.kernel.org/r/20211126083119.16570-3-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-07 10:54:37 +00:00
Li Chen 50b620303a PCI: endpoint: Return -EINVAL when interrupts num is smaller than 1
In pci_epc_set_msi() we should return immediately if there are no
interrupts to configure; update the code to return early.

Link: https://lore.kernel.org/r/CH2PR19MB402491B9E503694DBCAC6005A07C9@CH2PR19MB4024.namprd19.prod.outlook.com
Signed-off-by: Li Chen <lchen@ambarella.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
2022-01-07 10:35:34 +00:00
qizhong cheng 65ace9a85f PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.

Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Pali Rohár <pali@kernel.org>
2022-01-07 10:21:51 +00:00
Pali Rohár 0746ae1be1 PCI: mvebu: Add support for compiling driver as module
Now when driver uses devm_pci_remap_iospace() function, it is possible
implement ->remove() callback for unbinding device from driver.

Implement mvebu_pcie_remove() callback with proper cleanup phase, drop
driver's suppress_bind_attrs flag and switch type of CONFIG_PCI_MVEBU
option from bool to tristate.

This allows to compile pci-mvebu.c driver as loadable module pci-mvebu.ko
with ability to unload it.

Link: https://lore.kernel.org/r/20211126144307.7568-3-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-06 13:37:47 +00:00
Karthik L Gopalakrishnan 922bfd001d PCI: vmd: Add DID 8086:A77F for all Intel Raptor Lake SKU's
Add support for this VMD device which supports the bus restriction mode.
The feature that turns off vector 0 for MSI-X remapping is also enabled.

Link: https://lore.kernel.org/r/20211217231211.46018-1-francisco.munoz.ruiz@linux.intel.com
Signed-off-by: Karthik L Gopalakrishnan <karthik.l.gopalakrishnan@intel.com>
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@linux.intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Jon Derrick <jonathan.derrick@linux.dev>
2022-01-05 16:24:45 +00:00
Hou Zhiqiang d23f0c11ac PCI: layerscape: Change to use the DWC common link-up check function
The current Layerscape PCIe driver directly uses the physical layer
LTSSM code to check the link-up state, which treats the > L0 states
as link-up. This is not correct, since there is not explicit map
between link-up state and LTSSM. So this patch changes to use the
DWC common link-up check function.

Link: https://lore.kernel.org/r/20211224094000.8513-1-Zhiqiang.Hou@nxp.com
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
2022-01-05 15:23:15 +00:00
Rikard Falkeborn 840a720aaa PCI: qcom-ep: Constify static dw_pcie_ep_ops
The only usage of pci_ep_ops is to assign its address to the ops field
in the dw_pcie_ep struct which is a pointer to const struct dw_pcie_ep_ops.
Make it const to allow the compiler to put it in read-only memory.

Link: https://lore.kernel.org/r/20211204220316.88655-1-rikard.falkeborn@gmail.com
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
2022-01-04 15:29:14 +00:00
Kai-Heng Feng 04b12ef163 PCI: vmd: Honor ACPI _OSC on PCIe features
When Samsung PCIe Gen4 NVMe is connected to Intel ADL VMD, the
combination causes AER message flood and drags the system performance
down.

The issue doesn't happen when VMD mode is disabled in BIOS, since AER
isn't enabled by acpi_pci_root_create() . When VMD mode is enabled, AER
is enabled regardless of _OSC:
[    0.410076] acpi PNP0A08:00: _OSC: platform does not support [AER]
...
[    1.486704] pcieport 10000:e0:06.0: AER: enabled with IRQ 146

Since VMD is an aperture to regular PCIe root ports, honor ACPI _OSC to
disable PCIe features accordingly to resolve the issue.

Suggested-by: Rafael J. Wysocki <rafael@kernel.org>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=215027
Link: https://lore.kernel.org/r/20211203031541.1428904-1-kai.heng.feng@canonical.com
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-01-04 15:25:27 +00:00
Pali Rohár 4ab34548c5 PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on emulated bridge
Armada XP and new hardware supports access to DEVCAP2, DEVCTL2 and LNKCTL2
configuration registers of PCIe core via PCIE_CAP_PCIEXP. So export them
via emulated software root bridge.

Pre-XP hardware does not support these registers and returns zeros.

Link: https://lore.kernel.org/r/20211125124605.25915-16-pali@kernel.org
Fixes: 1f08673eef ("PCI: mvebu: Convert to PCI emulated bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 15:00:03 +00:00
Pali Rohár 838ff44a39 PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridge
PME Status bit in Root Status Register (PCIE_RC_RTSTA_OFF) is read-only and
can be cleared only by writing 0b to the Interrupt Cause RW0C register
(PCIE_INT_CAUSE_OFF).

Link: https://lore.kernel.org/r/20211125124605.25915-15-pali@kernel.org
Fixes: 1f08673eef ("PCI: mvebu: Convert to PCI emulated bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:59:45 +00:00
Pali Rohár ecae073e39 PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridge
Comment in Armada 370 functional specification is misleading.
PCI_EXP_DEVCTL_*RE bits are supported and configures receiving of error
interrupts.

Link: https://lore.kernel.org/r/20211125124605.25915-14-pali@kernel.org
Fixes: 1f08673eef ("PCI: mvebu: Convert to PCI emulated bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:59:37 +00:00
Pali Rohár d75404cc08 PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge
Hardware supports PCIe Hot Reset via PCIE_CTRL_OFF register. Use it for
implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL register on
emulated bridge.

With this change the function pci_reset_secondary_bus() starts working and
can reset connected PCIe card.

Link: https://lore.kernel.org/r/20211125124605.25915-13-pali@kernel.org
Fixes: 1f08673eef ("PCI: mvebu: Convert to PCI emulated bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:59:25 +00:00
Pali Rohár 91a8d79fc7 PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge
It looks like that mvebu PCIe controller has for each PCIe link fully
independent PCIe host bridge and so every PCIe Root Port is isolated not
only on its own bus but also isolated from each others. But in past device
tree structure was defined to put all PCIe Root Ports (as PCI Bridge
devices) into one root bus 0 and this bus is emulated by pci-mvebu.c
driver.

Probably reason for this decision was incorrect understanding of PCIe
topology of these Armada SoCs and also reason of misunderstanding how is
PCIe controller generating Type 0 and Type 1 config requests (it is fully
different compared to other drivers). Probably incorrect setup leaded to
very surprised things like having PCIe Root Port (PCI Bridge device, with
even incorrect Device Class set to Memory Controller) and the PCIe device
behind the Root Port on the same PCI bus, which obviously was needed to
somehow hack (as these two devices cannot be in reality on the same bus).

Properly set mvebu local bus number and mvebu local device number based on
PCI Bridge secondary bus number configuration. Also correctly report
configured secondary bus number in config space. And explain in driver
comment why this setup is correct.

Link: https://lore.kernel.org/r/20211125124605.25915-12-pali@kernel.org
Fixes: 1f08673eef ("PCI: mvebu: Convert to PCI emulated bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:59:18 +00:00
Pali Rohár f587775828 PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge
The default value of Class Code of this bridge corresponds to a Memory
controller, though. This is probably relict from the past when old
Marvell/Galileo PCI-based controllers were used as standalone PCI device
for connecting SDRAM or workaround for PCs with broken BIOS. Details are
in commit 36de23a4c5 ("MIPS: Cobalt: Explain GT64111 early PCI fixup").

Change the Class Code to correspond to a PCI Bridge.

Add comment explaining this change.

Link: https://lore.kernel.org/r/20211125124605.25915-11-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:59:07 +00:00
Pali Rohár df08ac0161 PCI: mvebu: Setup PCIe controller to Root Complex mode
This driver operates only in Root Complex mode, so ensure that hardware is
properly configured in Root Complex mode.

Link: https://lore.kernel.org/r/20211125124605.25915-10-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:59:01 +00:00
Pali Rohár e7a0187672 PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers
Properly propagate failure from mvebu_pcie_add_windows() function back to
the caller mvebu_pci_bridge_emul_base_conf_write() and correctly updates
PCI_IO_BASE, PCI_MEM_BASE and PCI_IO_BASE_UPPER16 registers on error.
On error set base value higher than limit value which indicates that
address range is disabled. When IO is unsupported then let IO registers
zeroed as required by PCIe base specification.

Link: https://lore.kernel.org/r/20211125124605.25915-9-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:58:55 +00:00
Pali Rohár 2cf150216e PCI: mvebu: Do not modify PCI IO type bits in conf_write
PCI IO type bits are already initialized in mvebu_pci_bridge_emul_init()
function and only when IO support is enabled. These type bits are read-only
and pci-bridge-emul.c code already does not allow to modify them from upper
layers.

When IO support is disabled then all IO registers should be read-only and
return zeros. Therefore do not modify PCI IO type bits in
mvebu_pci_bridge_emul_base_conf_write() callback.

Link: https://lore.kernel.org/r/20211125124605.25915-8-pali@kernel.org
Fixes: 1f08673eef ("PCI: mvebu: Convert to PCI emulated bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:58:48 +00:00
Pali Rohár e42b855837 PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge
According to PCI specifications bits [0:2] of Command Register, this should
be by default disabled on reset. So explicitly disable these bits at early
beginning of driver initialization.

Also remove code which unconditionally enables all 3 bits and let kernel
code (via pci_set_master() function) to handle bus mastering of PCI Bridge
via emulated PCI_COMMAND on emulated bridge.

Adjust existing functions mvebu_pcie_handle_iobase_change() and
mvebu_pcie_handle_membase_change() to handle PCI_IO_BASE and PCI_MEM_BASE
registers correctly even when bus mastering on emulated bridge is disabled.

Link: https://lore.kernel.org/r/20211125124605.25915-7-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:58:43 +00:00
Pali Rohár 319e6046bd PCI: mvebu: Disallow mapping interrupts on emulated bridges
Interrupt support on mvebu emulated bridges is not implemented yet.

So properly indicate return value to callers that they cannot request
interrupts from emulated bridge.

Link: https://lore.kernel.org/r/20211125124605.25915-6-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:58:39 +00:00
Pali Rohár 11c2bf4a20 PCI: mvebu: Handle invalid size of read config request
Function mvebu_pcie_hw_rd_conf() does not handle invalid size. So correctly
set read value to all-ones and return appropriate error return value
PCIBIOS_BAD_REGISTER_NUMBER like in mvebu_pcie_hw_wr_conf() function.

Link: https://lore.kernel.org/r/20211125124605.25915-5-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:58:35 +00:00
Pali Rohár 489bfc5187 PCI: mvebu: Check that PCI bridge specified in DT has function number zero
Driver cannot handle PCI bridges at non-zero function address. So add
appropriate check. Currently all in-tree kernel DTS files set PCI bridge
function to zero.

Link: https://lore.kernel.org/r/20211125124605.25915-4-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:58:32 +00:00
Pali Rohár 5d18d702e5 PCI: mvebu: Check for errors from pci_bridge_emul_init() call
Function pci_bridge_emul_init() may fail so correctly check for errors.

Link: https://lore.kernel.org/r/20211125124605.25915-3-pali@kernel.org
Fixes: 1f08673eef ("PCI: mvebu: Convert to PCI emulated bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:58:26 +00:00
Pali Rohár 8cdabfdd5a PCI: mvebu: Check for valid ports
Some mvebu ports do not have to be initialized. So skip these uninitialized
mvebu ports in every port iteration function to prevent access to unmapped
memory or dereferencing NULL pointers. Uninitialized mvebu port has base
address set to NULL.

Link: https://lore.kernel.org/r/20211125124605.25915-2-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04 14:58:18 +00:00
Bjorn Helgaas 73a0c2be75 PCI: spear13xx: Avoid invalid address space conversions
The sparse checker complains about converting pointers between address
spaces.  We correctly stored an __iomem pointer in struct spear13xx_pcie,
but discarded the __iomem when extracting app_base, causing one warning.
Then we passed the non-__iomem pointer to writel(), which expects an
__iomem pointer, causing another warning.

Add the appropriate annotations.

The sparse warnings look like this:

  $ make C=2 drivers/pci/controller/
  drivers/pci/controller/dwc/pcie-spear13xx.c:72:54: warning: incorrect type in initializer (different address spaces)
  drivers/pci/controller/dwc/pcie-spear13xx.c:72:54:    expected struct pcie_app_reg *app_reg
  drivers/pci/controller/dwc/pcie-spear13xx.c:72:54:    got void [noderef] __iomem *app_base
  drivers/pci/controller/dwc/pcie-spear13xx.c:78:26: warning: incorrect type in argument 2 (different address spaces)
  drivers/pci/controller/dwc/pcie-spear13xx.c:78:26:    expected void volatile [noderef] __iomem *addr
  drivers/pci/controller/dwc/pcie-spear13xx.c:78:26:    got unsigned int *

Link: https://lore.kernel.org/r/20211223213749.1314142-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
2022-01-03 15:05:28 -06:00
Bjorn Helgaas 088c840599 PCI: hisi: Avoid invalid address space conversions
The sparse checker complains about converting pointers between address
spaces.  The pci_config_window.priv pointer is a generic void *, but
hisi_pcie_map_bus() needs a void __iomem *.

This isn't a problem in other drivers because they store the __iomem
pointer in a driver struct.  Add a trivial struct hisi_pcie to avoid the
warning.

The sparse warning looks like this:

  $ make C=2 drivers/pci/controller/
  drivers/pci/controller/dwc/pcie-hisi.c:61:37: warning: incorrect type in initializer (different address spaces)
  drivers/pci/controller/dwc/pcie-hisi.c:61:37:    expected void [noderef] __iomem *reg_base
  drivers/pci/controller/dwc/pcie-hisi.c:61:37:    got void *priv

Link: https://lore.kernel.org/r/20211223213749.1314142-2-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
2022-01-03 15:05:28 -06:00
Bjorn Helgaas dacee5872d PCI: xilinx-cpm: Rename xilinx_cpm_pcie_port to xilinx_cpm_pcie
Rename struct xilinx_cpm_pcie_port to xilinx_cpm_pcie to match the
convention of <driver>_pcie. No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-24-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2022-01-03 15:05:28 -06:00
Fan Fei 0519f73adb PCI: xilinx: Rename xilinx_pcie_port to xilinx_pcie
Rename struct xilinx_pcie_port to xilinx_pcie to match the convention of
<driver>_pcie. No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-23-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2022-01-03 15:05:28 -06:00
Fan Fei 24d174a116 PCI: xgene: Rename xgene_pcie_port to xgene_pcie
Rename struct xgene_pcie_port to xgene_pcie to match the convention of
<driver>_pcie. No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-22-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Toan Le <toan@os.amperecomputing.com>
2022-01-03 15:05:28 -06:00
Fan Fei de8bd0c6c3 PCI: uniphier: Rename uniphier_pcie_priv to uniphier_pcie
Rename struct uniphier_pcie_priv to uniphier_pcie to match the convention
of <driver>_pcie. No functional change intended.

[bhelgaas: drop extraneous uniphier_pcie_irq_ack() from patch]
Link: https://lore.kernel.org/r/20211223011054.1227810-21-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
2022-01-03 15:05:28 -06:00
Fan Fei b572569183 PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie
Rename tegra_pcie_dw to tegra194_pcie to match the convention of
<driver>_pcie. No functional change intended.

[bhelgaas: rename functions similarly]
Link: https://lore.kernel.org/r/20211223011054.1227810-20-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
2022-01-03 15:05:28 -06:00
Bjorn Helgaas 7025ecb658 PCI: rcar-gen2: Rename rcar_pci_priv to rcar_pci
Rename struct rcar_pci_priv to rcar_pci to match the convention of
<driver>_pci. No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-19-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
2022-01-03 15:05:28 -06:00
Bjorn Helgaas 4793895f59 PCI: mt7621: Rename mt7621_pci_ to mt7621_pcie_
Rename mt7621_pci_* structs and functions to mt7621_pcie_* for consistency
with the rest of the file.

Link: https://lore.kernel.org/r/20211223011054.1227810-18-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-03 15:05:19 -06:00
Bjorn Helgaas 5fe714fd92 PCI: microchip: Rename mc_port to mc_pcie
Rename struct mc_port to mc_pcie to match the convention of <driver>_pcie.
No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-16-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Daire McNamara <daire.mcnamara@microchip.com>
2022-01-03 15:02:08 -06:00
Fan Fei d5a4835b5e PCI: mediatek-gen3: Rename mtk_pcie_port to mtk_gen3_pcie
Rename struct mtk_pcie_port to mtk_gen3_pcie to match the convention of
<driver>_pcie. No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-15-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Jianjun Wang <jianjun.wang@mediatek.com>
2022-01-03 15:02:02 -06:00
Bjorn Helgaas 4688594ff4 PCI: ls-gen4: Rename ls_pcie_g4 to ls_g4_pcie
Rename struct ls_pcie_g4 to ls_g4_pcie to match the convention of
<driver>_pcie. No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-14-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2022-01-03 15:01:59 -06:00
Bjorn Helgaas 05463a768f PCI: iproc: Rename iproc_pcie_pltfm_ to iproc_pltfm_pcie_
Rename iproc_pcie_pltfm_* to iproc_pltfm_pcie_* for consistency with other
drivers.  No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-13-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
2022-01-03 15:01:53 -06:00
Bjorn Helgaas 8fa9663520 PCI: iproc: Rename iproc_pcie_bcma_ to iproc_bcma_pcie_
Rename iproc_pcie_bcma_* to iproc_bcma_pcie_* for consistency with other
drivers.  No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-12-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
2022-01-03 15:01:49 -06:00
Fan Fei 733770d4a2 PCI: intel-gw: Rename intel_pcie_port to intel_pcie
Rename struct intel_pcie_port to intel_pcie to match the convention of
<driver>_pcie. No functional change intended.

Link: https://lore.kernel.org/r/20211223011054.1227810-11-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rahul Tanwar <rtanwar@maxlinear.com>
2022-01-03 15:01:43 -06:00
Bjorn Helgaas 19e863828a PCI: j721e: Drop redundant struct device *
The struct cdns_pcie already contains the struct device for the j721e PCIe
controller.  There's no need to store another copy in struct j721e_pcie.
Remove the redundant copy from struct j721e_pcie.

Link: https://lore.kernel.org/r/20211223011054.1227810-10-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Tom Joseph <tjoseph@cadence.com>
2022-01-03 15:01:38 -06:00
Bjorn Helgaas 72de208f2b PCI: j721e: Drop pointless of_device_get_match_data() cast
of_device_get_match_data() returns "void *", so no cast is needed when
assigning the result to a pointer type.  Drop the unnecessary cast.

Link: https://lore.kernel.org/r/20211223011054.1227810-9-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Tom Joseph <tjoseph@cadence.com>
2022-01-03 15:01:33 -06:00
Fan Fei a622435fbe PCI: kirin: Prefer of_device_get_match_data()
The kirin driver only needs the device data, not the whole struct
of_device_id.  Use of_device_get_match_data() instead of of_match_device().
No functional change intended.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20211223011054.1227810-8-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
2022-01-03 15:01:28 -06:00
Fan Fei 39a29fbd4e PCI: keystone: Prefer of_device_get_match_data()
The keystone driver only needs the device data, not the whole struct
of_device_id.  Use of_device_get_match_data() instead of of_match_device().
No functional change intended.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20211223011054.1227810-7-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
2022-01-03 15:01:23 -06:00
Fan Fei dc078f1571 PCI: dra7xx: Prefer of_device_get_match_data()
The dra7xx driver only needs the device data, not the whole struct
of_device_id.  Use of_device_get_match_data() instead of of_match_device().
No functional change intended.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20211223011054.1227810-6-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
2022-01-03 15:01:16 -06:00
Fan Fei 5c204204cf PCI: designware-plat: Prefer of_device_get_match_data()
The designware-plat driver only needs the device data, not the whole struct
of_device_id.  Use of_device_get_match_data() instead of of_match_device().
No functional change intended.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20211223011054.1227810-5-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2022-01-03 15:01:09 -06:00
Fan Fei 131748ad29 PCI: cadence: Prefer of_device_get_match_data()
The cadence driver only needs the device data, not the whole struct
of_device_id.  Use of_device_get_match_data() instead of of_match_device().
No functional change intended.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20211223011054.1227810-4-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Tom Joseph <tjoseph@cadence.com>
2022-01-03 15:01:04 -06:00
Fan Fei 7073f2ceca PCI: artpec6: Prefer of_device_get_match_data()
The artpec6 driver only needs the device data, not the whole struct
of_device_id.  Use of_device_get_match_data() instead of of_match_device().
No functional change intended.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20211223011054.1227810-3-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2022-01-03 15:00:55 -06:00
Fan Fei c31990dbeb PCI: altera: Prefer of_device_get_match_data()
The altera driver only needs the device data, not the whole struct
of_device_id.  Use of_device_get_match_data() instead of of_match_device().
No functional change intended.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20211223011054.1227810-2-helgaas@kernel.org
Signed-off-by: Fan Fei <ffclaire1224@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Joyce Ooi <joyce.ooi@intel.com>
2022-01-03 15:00:47 -06:00
Greg Kroah-Hartman 0cf948aab9 PCI/sysfs: Use default_groups in kobj_type for slot attrs
There are currently two ways to create a set of sysfs files for a
kobj_type: through the default_attrs field, and the default_groups field.
Move the PCI slot code to use the default_groups field which has been the
preferred way since aa30f47cf6 ("kobject: Add support for default
attribute groups to kobj_type") so that we can soon get rid of the obsolete
default_attrs field.

Link: https://lore.kernel.org/r/20211228135722.381023-1-gregkh@linuxfoundation.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-12-29 13:42:04 -06:00
Richard Zhu 178e244cb6 PCI: imx: Add the imx8mm pcie support
i.MX8MM PCIe works mostly like the i.MX8MQ one, but has a different PHY
and allows to output the internal PHY reference clock via the refclk pad.
Add the i.MX8MM PCIe support based on the standalone PHY driver.

Link: https://lore.kernel.org/r/1640312885-31142-2-git-send-email-hongxing.zhu@nxp.com
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
2021-12-26 12:13:32 +00:00
Linus Torvalds a76c3d0358 - Clear the PCI_MSIX_FLAGS_MASKALL bit too on the error path so that it
is restored to its reset state
 
 - Mask MSI-X vectors late on the init path in order to handle
 out-of-spec Marvell NVME devices which apparently look at the MSI-X mask
 even when MSI-X is disabled
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Merge tag 'irq_urgent_for_v5.16_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Borislav Petkov:

 - Clear the PCI_MSIX_FLAGS_MASKALL bit too on the error path so that it
   is restored to its reset state

 - Mask MSI-X vectors late on the init path in order to handle
   out-of-spec Marvell NVME devices which apparently look at the MSI-X
   mask even when MSI-X is disabled

* tag 'irq_urgent_for_v5.16_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  PCI/MSI: Clear PCI_MSIX_FLAGS_MASKALL on error
  PCI/MSI: Mask MSI-X vectors only on success
2021-12-19 12:28:46 -08:00
Thomas Gleixner d558285413 PCI/MSI: Unbreak pci_irq_get_affinity()
The recent cleanup of pci_irq_get_affinity() broke the function for
PCI/MSI-X and indices > 0. Only the MSI descriptor for PCI/MSI has more
than one affinity mask which can be retrieved via the MSI index.

PCI/MSI-X has one descriptor per vector and each has a single affinity
mask.

Use index 0 when accessing the affinity mask in the MSI descriptor when
MSI-X is enabled.

Fixes: f482359001 ("PCI/MSI: Simplify pci_irq_get_affinity()")
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/87v8zm9pmd.ffs@tglx
2021-12-18 20:33:21 +01:00
Thomas Gleixner dc2b453290 PCI: hv: Rework MSI handling
Replace the about to vanish iterators and make use of the filtering. Take
the descriptor lock around the iterators.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210748.629363944@linutronix.de
2021-12-16 22:22:19 +01:00
Thomas Gleixner 3d31bbd39a xen/pcifront: Rework MSI handling
Replace the about to vanish iterators.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20211206210748.251752714@linutronix.de
2021-12-16 22:22:18 +01:00
Thomas Gleixner ae24e28fef PCI/MSI: Use msi_on_each_desc()
Use the new iterator functions which pave the way for dynamically extending
MSI-X vectors.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210748.142603657@linutronix.de
2021-12-16 22:22:18 +01:00
Thomas Gleixner 9fb9eb4b59 PCI/MSI: Let core code free MSI descriptors
Set the domain info flag which tells the core code to free the MSI
descriptors from msi_domain_free_irqs() and add an explicit call to the
core function into the legacy code.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210748.089085131@linutronix.de
2021-12-16 22:22:17 +01:00
Thomas Gleixner 71020a3c0d PCI/MSI: Use msi_add_msi_desc()
Simplify the allocation of MSI descriptors by using msi_add_msi_desc()
which moves the storage handling to core code and prepares for dynamic
extension of the MSI-X vector space.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210748.035348646@linutronix.de
2021-12-16 22:22:17 +01:00
Thomas Gleixner 5512c5eaf5 PCI/MSI: Protect MSI operations
To prepare for dynamic extension of MSI-X vectors, protect the MSI
operations for MSI and MSI-X. This requires to move the invocation of
irq_create_affinity_masks() out of the descriptor lock section to avoid
reverse lock ordering vs. CPU hotplug lock as some callers of the PCI/MSI
allocation interfaces already hold it.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210747.982292705@linutronix.de
2021-12-16 22:22:17 +01:00
Thomas Gleixner f482359001 PCI/MSI: Simplify pci_irq_get_affinity()
Replace open coded MSI descriptor chasing and use the proper accessor
functions instead.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20211210221814.900929381@linutronix.de
2021-12-16 22:16:41 +01:00
Thomas Gleixner 82ff8e6b78 PCI/MSI: Use msi_get_virq() in pci_get_vector()
Use msi_get_vector() and handle the return value to be compatible.

No functional change intended.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20211210221814.841243231@linutronix.de
2021-12-16 22:16:41 +01:00
Thomas Gleixner 7a823443e9 PCI/MSI: Provide MSI_FLAG_MSIX_CONTIGUOUS
Provide a domain info flag which makes the core code check for a contiguous
MSI-X index on allocation. That's simpler than checking it at some other
domain callback in architecture code.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211210221814.662401116@linutronix.de
2021-12-16 22:16:40 +01:00
Thomas Gleixner 173ffad79d PCI/MSI: Use msi_desc::msi_index
The usage of msi_desc::pci::entry_nr is confusing at best. It's the index
into the MSI[X] descriptor table.

Use msi_desc::msi_index which is shared between all MSI incarnations
instead of having a PCI specific storage for no value.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211210221814.602911509@linutronix.de
2021-12-16 22:16:40 +01:00
Thomas Gleixner ffd84485e6 PCI/MSI: Let the irq code handle sysfs groups
Set the domain info flag which makes the core code handle sysfs groups and
put an explicit invocation into the legacy code.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211210221814.048612053@linutronix.de
2021-12-16 22:16:39 +01:00
Thomas Gleixner 93296cd132 PCI/MSI: Allocate MSI device data on first use
Allocate MSI device data on first use, i.e. when a PCI driver invokes one
of the PCI/MSI enablement functions.

Add a wrapper function to ensure that the ordering vs. pcim_msi_release()
is correct.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/87r1adrdje.ffs@tglx
2021-12-16 22:16:38 +01:00
Thomas Gleixner 3f35d2cf9f PCI/MSI: Decouple MSI[-X] disable from pcim_release()
The MSI core will introduce runtime allocation of MSI related data. This
data will be devres managed and has to be set up before enabling
PCI/MSI[-X]. This would introduce an ordering issue vs. pcim_release().

The setup order is:

   pcim_enable_device()
	devres_alloc(pcim_release...);
	...
	pci_irq_alloc()
	  msi_setup_device_data()
	     devres_alloc(msi_device_data_release, ...)

and once the device is released these release functions are invoked in the
opposite order:

    msi_device_data_release()
    ...
    pcim_release()
       pci_disable_msi[x]()

which is obviously wrong, because pci_disable_msi[x]() requires the MSI
data to be available to tear down the MSI[-X] interrupts.

Remove the MSI[-X] teardown from pcim_release() and add an explicit action
to be installed on the attempt of enabling PCI/MSI[-X].

This allows the MSI core data allocation to be ordered correctly in a
subsequent step.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/87tuf9rdoj.ffs@tglx
2021-12-16 22:16:38 +01:00
Thomas Gleixner c7ecb95ca6 PCI/MSI: Set pci_dev::msi[x]_enabled early
There are quite some places which retrieve the first MSI descriptor to
evaluate whether the setup is for MSI or MSI-X. That's required because
pci_dev::msi[x]_enabled is only set when the setup completed successfully.

There is no real reason why msi[x]_enabled can't be set at the beginning of
the setup sequence and cleared in case of a failure.

Implement that so the MSI descriptor evaluations can be converted to simple
property queries.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20211210221813.250049810@linutronix.de
2021-12-16 22:16:37 +01:00
Christophe JAILLET 69f457b18f PCI/P2PDMA: Use percpu_ref_tryget_live_rcu() inside RCU critical section
Since pci_alloc_p2pmem() has already called rcu_read_lock(), we're in an
RCU read-side critical section and don't need to take the lock again.  Use
percpu_ref_tryget_live_rcu() instead of percpu_ref_tryget_live() to save a
few cycles.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/ab80164f4d5b32f9e6240aa4863c3a147ff9c89f.1635974126.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
2021-12-15 16:13:13 -06:00
Yifeng Li e445375882 PCI: Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller
Like other SATA controller chips in the Marvell 88SE91xx series, the
Marvell 88SE9125 has the same DMA requester ID hardware bug that prevents
it from working under IOMMU.  Add it to the list of devices that need the
quirk.

Without this patch, device initialization fails with DMA errors:

  ata8: softreset failed (1st FIS failed)
  DMAR: DRHD: handling fault status reg 2
  DMAR: [DMA Write NO_PASID] Request device [03:00.1] fault addr 0xfffc0000 [fault reason 0x02] Present bit in context entry is clear
  DMAR: DRHD: handling fault status reg 2
  DMAR: [DMA Read NO_PASID] Request device [03:00.1] fault addr 0xfffc0000 [fault reason 0x02] Present bit in context entry is clear

After applying the patch, the controller can be successfully initialized:

  ata8: SATA link up 1.5 Gbps (SStatus 113 SControl 330)
  ata8.00: ATAPI: PIONEER BD-RW   BDR-207M, 1.21, max UDMA/100
  ata8.00: configured for UDMA/100
  scsi 7:0:0:0: CD-ROM            PIONEER  BD-RW   BDR-207M 1.21 PQ: 0 ANSI: 5

Link: https://lore.kernel.org/r/YahpKVR+McJVDdkD@work
Reported-by: Sam Bingner <sam@bingner.com>
Tested-by: Sam Bingner <sam@bingner.com>
Tested-by: Yifeng Li <tomli@tomli.me>
Signed-off-by: Yifeng Li <tomli@tomli.me>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Cc: stable@vger.kernel.org
2021-12-15 14:28:18 -06:00
Thomas Gleixner 09eb3ad55f Merge branch 'irq/urgent' into irq/msi
to pick up the PCI/MSI-x fixes.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2021-12-14 13:30:34 +01:00
Thomas Gleixner 94185adbfa PCI/MSI: Clear PCI_MSIX_FLAGS_MASKALL on error
PCI_MSIX_FLAGS_MASKALL is set in the MSI-X control register at MSI-X
interrupt setup time. It's cleared on success, but the error handling path
only clears the PCI_MSIX_FLAGS_ENABLE bit.

That's incorrect as the reset state of the PCI_MSIX_FLAGS_MASKALL bit is
zero. That can be observed via lspci:

        Capabilities: [b0] MSI-X: Enable- Count=67 Masked+

Clear the bit in the error path to restore the reset state.

Fixes: 438553958b ("PCI/MSI: Enable and mask MSI-X early")
Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Stefan Roese <sr@denx.de>
Cc: linux-pci@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Marek Vasut <marex@denx.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/87tufevoqx.ffs@tglx
2021-12-14 13:23:32 +01:00
Stefan Roese 83dbf898a2 PCI/MSI: Mask MSI-X vectors only on success
Masking all unused MSI-X entries is done to ensure that a crash kernel
starts from a clean slate, which correponds to the reset state of the
device as defined in the PCI-E specificion 3.0 and later:

 Vector Control for MSI-X Table Entries
 --------------------------------------

 "00: Mask bit:  When this bit is set, the function is prohibited from
                 sending a message using this MSI-X Table entry.
                 ...
                 This bit’s state after reset is 1 (entry is masked)."

A Marvell NVME device fails to deliver MSI interrupts after trying to
enable MSI-X interrupts due to that masking. It seems to take the MSI-X
mask bits into account even when MSI-X is disabled.

While not specification compliant, this can be cured by moving the masking
into the success path, so that the MSI-X table entries stay in device reset
state when the MSI-X setup fails.

[ tglx: Move it into the success path, add comment and amend changelog ]

Fixes: aa8092c1d1f1 ("PCI/MSI: Mask all unused MSI-X entries")                                                                                                                                                                                                                 
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-pci@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Marek Vasut <marex@denx.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20211210161025.3287927-1-sr@denx.de
2021-12-14 13:23:32 +01:00
Sergio Paracuellos aa50faff44 PCI: mt7621: Convert driver into 'bool'
The driver is not ready yet to be compiled as a module since it depends
on some symbols not exported on MIPS.  We have the following current
problems:

  Building mips:allmodconfig ... failed
  --------------
  Error log:
  ERROR: modpost: missing MODULE_LICENSE() in drivers/pci/controller/pcie-mt7621.o
  ERROR: modpost: "mips_cm_unlock_other" [drivers/pci/controller/pcie-mt7621.ko] undefined!
  ERROR: modpost: "mips_cpc_base" [drivers/pci/controller/pcie-mt7621.ko] undefined!
  ERROR: modpost: "mips_cm_lock_other" [drivers/pci/controller/pcie-mt7621.ko] undefined!
  ERROR: modpost: "mips_cm_is64" [drivers/pci/controller/pcie-mt7621.ko] undefined!
  ERROR: modpost: "mips_gcr_base" [drivers/pci/controller/pcie-mt7621.ko] undefined!

Temporarily move from 'tristate' to 'bool' until a better solution is
ready.

Also RALINK is redundant because SOC_MT7621 already depends on it.
Hence, simplify condition.

Fixes: 2bdd5238e7 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver").
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-and-Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2021-12-13 11:13:32 -08:00
Linus Torvalds b8a98b6bf6 pci-v5.16-fixes-2
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Merge tag 'pci-v5.16-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:

 - Revert emulation of Marvell Armada A3720 expansion ROM because it
   doesn't work as expected (Marek Behún)

 - Assert PERST# in Apple M1 driver to fix initialization when booting
   from bootloaders using PCIe, such as U-Boot (Marc Zyngier)

 - Describe PERST# as active low in Apple T8103 DT and update driver to
   match (Marc Zyngier)

* tag 'pci-v5.16-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: apple: Fix PERST# polarity
  arm64: dts: apple: t8103: Mark PCIe PERST# polarity active low in DT
  PCI: apple: Follow the PCIe specifications when resetting the port
  Revert "PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge"
2021-12-10 11:56:05 -08:00
Vihas Mak e1a6333e7f PCI: ibmphp: Remove commented-out functions
The functions get_max_adapter_speed() and get_bus_name() in ibmphp_core.c
are commented-out and the fields .get_max_adapter_speed and
.get_bus_name_status are removed from struct hotplug_slot_ops in
pci_hotplug.h. Remove the commented-out functions.

Link: https://lore.kernel.org/r/20211209213618.20522-1-makvihas@gmail.com
Signed-off-by: Vihas Mak <makvihas@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-12-10 09:55:47 -06:00
Thomas Gleixner 60bf9b33c8 PCI/MSI: Move descriptor counting on allocation fail to the legacy code
The irqdomain code already returns the information. Move the loop to the
legacy code.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20211206210225.101336873@linutronix.de
2021-12-09 11:52:23 +01:00
Thomas Gleixner 890337624e genirq/msi: Handle PCI/MSI allocation fail in core code
Get rid of yet another irqdomain callback and let the core code return the
already available information of how many descriptors could be allocated.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>	# PCI
Link: https://lore.kernel.org/r/20211206210225.046615302@linutronix.de
2021-12-09 11:52:22 +01:00
Thomas Gleixner 57ce3a3c99 PCI/MSI: Make pci_msi_domain_check_cap() static
No users outside of that file.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.980989243@linutronix.de
2021-12-09 11:52:22 +01:00
Thomas Gleixner cd119b09a8 PCI/MSI: Move msi_lock to struct pci_dev
It's only required for PCI/MSI. So no point in having it in every struct
device.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.925241961@linutronix.de
2021-12-09 11:52:22 +01:00
Thomas Gleixner 85aa607e79 PCI/MSI: Sanitize MSI-X table map handling
Unmapping the MSI-X base mapping in the loops which allocate/free MSI
descriptors is daft and in the way of allowing runtime expansion of MSI-X
descriptors.

Store the mapping in struct pci_dev and free it after freeing the MSI-X
descriptors.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.871651518@linutronix.de
2021-12-09 11:52:22 +01:00
Thomas Gleixner aa423ac422 PCI/MSI: Split out irqdomain code
Move the irqdomain specific code into its own file.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.817754783@linutronix.de
2021-12-09 11:52:22 +01:00
Thomas Gleixner a01e09ef12 PCI/MSI: Split out !IRQDOMAIN code
Split out the non irqdomain code into its own file.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.763574089@linutronix.de
2021-12-09 11:52:22 +01:00
Thomas Gleixner 54324c2f3d PCI/MSI: Split out CONFIG_PCI_MSI independent part
These functions are required even when CONFIG_PCI_MSI is not set. Move them
to their own file.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.710137730@linutronix.de
2021-12-09 11:52:22 +01:00
Thomas Gleixner 288c81ce4b PCI/MSI: Move code into a separate directory
msi.c is getting larger and really could do with a splitup. Move it into
its own directory to prepare for that.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.655043033@linutronix.de
2021-12-09 11:52:22 +01:00
Thomas Gleixner 7112158d97 PCI/MSI: Make msix_update_entries() smarter
No need to walk the descriptors and check for each one whether the entries
pointer function argument is NULL. Do it once.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.600351129@linutronix.de
2021-12-09 11:52:21 +01:00
Thomas Gleixner 29a03ada4a PCI/MSI: Cleanup include zoo
Get rid of the pile of unneeded includes which accumulated over time.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.539281124@linutronix.de
2021-12-09 11:52:21 +01:00
Thomas Gleixner ae72f31567 PCI/MSI: Make arch_restore_msi_irqs() less horrible.
Make arch_restore_msi_irqs() return a boolean which indicates whether the
core code should restore the MSI message or not. Get rid of the indirection
in x86.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>	# PCI
Link: https://lore.kernel.org/r/20211206210224.485668098@linutronix.de
2021-12-09 11:52:21 +01:00
Thomas Gleixner e58f2259b9 genirq/msi, treewide: Use a named struct for PCI/MSI attributes
The unnamed struct sucks and is in the way of further cleanups. Stick the
PCI related MSI data into a real data structure and cleanup all users.

No functional change.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20211206210224.374863119@linutronix.de
2021-12-09 11:52:21 +01:00
Thomas Gleixner 793c500676 PCI/sysfs: Use pci_irq_vector()
instead of fiddling with MSI descriptors.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.265589103@linutronix.de
2021-12-09 11:52:21 +01:00
Thomas Gleixner ade044a3d0 PCI/MSI: Remove msi_desc_to_pci_sysdata()
Last user is gone long ago.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210224.210768199@linutronix.de
2021-12-09 11:52:21 +01:00
Thomas Gleixner 9e8688c5f2 PCI/MSI: Make pci_msi_domain_write_msg() static
There is no point to have this function public as it is set by the PCI core
anyway when a PCI/MSI irqdomain is created.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>	# PCI
Link: https://lore.kernel.org/r/20211206210224.157070464@linutronix.de
2021-12-09 11:52:20 +01:00
Thomas Gleixner 29bbc35e29 PCI/MSI: Fix pci_irq_vector()/pci_irq_get_affinity()
pci_irq_vector() and pci_irq_get_affinity() use the list position to find the
MSI-X descriptor at a given index. That's correct for the normal case where
the entry number is the same as the list position.

But it's wrong for cases where MSI-X was allocated with an entries array
describing sparse entry numbers into the hardware message descriptor
table. That's inconsistent at best.

Make it always check the entry number because that's what the zero base
index really means. This change won't break existing users which use a
sparse entries array for allocation because these users retrieve the Linux
interrupt number from the entries array after allocation and none of them
uses pci_irq_vector() or pci_irq_get_affinity().

Fixes: aff171641d ("PCI: Provide sensible IRQ vector alloc/free routines")
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211206210223.929792157@linutronix.de
2021-12-09 11:52:20 +01:00
Jakub Kicinski 6efcdadc15 Merge https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf
Daniel Borkmann says:

====================
bpf 2021-12-08

We've added 12 non-merge commits during the last 22 day(s) which contain
a total of 29 files changed, 659 insertions(+), 80 deletions(-).

The main changes are:

1) Fix an off-by-two error in packet range markings and also add a batch of
   new tests for coverage of these corner cases, from Maxim Mikityanskiy.

2) Fix a compilation issue on MIPS JIT for R10000 CPUs, from Johan Almbladh.

3) Fix two functional regressions and a build warning related to BTF kfunc
   for modules, from Kumar Kartikeya Dwivedi.

4) Fix outdated code and docs regarding BPF's migrate_disable() use on non-
   PREEMPT_RT kernels, from Sebastian Andrzej Siewior.

5) Add missing includes in order to be able to detangle cgroup vs bpf header
   dependencies, from Jakub Kicinski.

6) Fix regression in BPF sockmap tests caused by missing detachment of progs
   from sockets when they are removed from the map, from John Fastabend.

7) Fix a missing "no previous prototype" warning in x86 JIT caused by BPF
   dispatcher, from Björn Töpel.

* https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf:
  bpf: Add selftests to cover packet access corner cases
  bpf: Fix the off-by-two error in range markings
  treewide: Add missing includes masked by cgroup -> bpf dependency
  tools/resolve_btfids: Skip unresolved symbol warning for empty BTF sets
  bpf: Fix bpf_check_mod_kfunc_call for built-in modules
  bpf: Make CONFIG_DEBUG_INFO_BTF depend upon CONFIG_BPF_SYSCALL
  mips, bpf: Fix reference to non-existing Kconfig symbol
  bpf: Make sure bpf_disable_instrumentation() is safe vs preemption.
  Documentation/locking/locktypes: Update migrate_disable() bits.
  bpf, sockmap: Re-evaluate proto ops when psock is removed from sockmap
  bpf, sockmap: Attach map progs to psock early for feature probes
  bpf, x86: Fix "no previous prototype" warning
====================

Link: https://lore.kernel.org/r/20211208155125.11826-1-daniel@iogearbox.net
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-12-08 16:06:44 -08:00
Marc Zyngier 8762051268 PCI: apple: Fix PERST# polarity
Now that PERST# is properly defined as active-low in the device tree, fix
the driver to correctly drive the line independently of the implied
polarity.

Suggested-by: Pali Rohár <pali@kernel.org>
Fixes: 1e33888fbe ("PCI: apple: Add initial hardware bring-up")
Link: https://lore.kernel.org/r/20211123180636.80558-4-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2021-12-07 14:27:29 -06:00
Marc Zyngier ee91cb570d PCI: apple: Follow the PCIe specifications when resetting the port
While the Apple PCIe driver works correctly when directly booted from the
firmware, it fails to initialise when the kernel is booted from a
bootloader using PCIe such as u-boot.

That's because we're missing a proper reset of the port (we only clear the
reset, but never assert it).

The PCIe spec requirements are two-fold:

  - PERST# must be asserted before setting up the clocks and stay asserted
    for at least 100us (Tperst-clk)

  - Once PERST# is deasserted, the OS must wait for at least 100ms "from
    the end of a Conventional Reset" before we can start talking to the
    devices

Implementing this results in a booting system.

[bhelgaas: #PERST -> PERST#, update spec references to current]
Fixes: 1e33888fbe ("PCI: apple: Add initial hardware bring-up")
Link: https://lore.kernel.org/r/20211123180636.80558-2-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Acked-by: Pali Rohár <pali@kernel.org>
Cc: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-07 10:37:31 -06:00
Pali Rohár 3be9d243b2 PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device
Since all PCI Express device Functions are required to implement the PCI
Express Capability structure, Capabilities List bit in PCI Status Register
must be hardwired to 1b. Capabilities Pointer register (which is already
set by pci-bride-emul.c driver) is valid only when Capabilities List is set
to 1b.

Link: https://lore.kernel.org/r/20211124155944.1290-7-pali@kernel.org
Fixes: 23a5fba4d9 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
2021-12-06 14:12:57 +00:00
Pali Rohár 1f1050c5e1 PCI: pci-bridge-emul: Correctly set PCIe capabilities
Older mvebu hardware provides PCIe Capability structure only in version 1.
New mvebu and aardvark hardware provides it in version 2. So do not force
version to 2 in pci_bridge_emul_init() and rather allow drivers to set
correct version. Drivers need to set version in pcie_conf.cap field without
overwriting PCI_CAP_LIST_ID register. Both drivers (mvebu and aardvark) do
not provide slot support yet, so do not set PCI_EXP_FLAGS_SLOT flag.

Link: https://lore.kernel.org/r/20211124155944.1290-6-pali@kernel.org
Fixes: 23a5fba4d9 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
2021-12-06 14:12:57 +00:00
Pali Rohár 12998087d9 PCI: pci-bridge-emul: Fix definitions of reserved bits
Some bits in PCI_EXP registers are reserved for non-root ports. Driver
pci-bridge-emul.c implements PCIe Root Port device therefore it should not
allow setting reserved bits of registers.

Properly define non-reserved bits for all PCI_EXP registers.

Link: https://lore.kernel.org/r/20211124155944.1290-5-pali@kernel.org
Fixes: 23a5fba4d9 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
2021-12-06 14:12:57 +00:00
Pali Rohár 7b067ac63a PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space
Some bits in PCI config space are reserved when device is PCIe. Properly
define behavior of PCI registers for PCIe emulated bridge and ensure that
it would not be possible change these reserved bits.

Link: https://lore.kernel.org/r/20211124155944.1290-3-pali@kernel.org
Fixes: 23a5fba4d9 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
2021-12-06 12:18:21 +00:00
Pali Rohár 1c1a3b4d3e PCI: pci-bridge-emul: Make expansion ROM Base Address register read-only
If expansion ROM is unsupported (which is the case of pci-bridge-emul.c
driver) then ROM Base Address register must be implemented as read-only
register that return 0 when read, same as for unused Base Address
registers.

Link: https://lore.kernel.org/r/20211124155944.1290-2-pali@kernel.org
Fixes: 23a5fba4d9 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
2021-12-06 12:18:21 +00:00
Krzysztof Wilczyński 549bf94dd2 PCI: qcom-ep: Remove surplus dev_err() when using platform_get_irq_byname()
There is no need to call the dev_err() function directly to print a
custom message when handling an error from either the platform_get_irq()
or platform_get_irq_byname() functions as both are going to display an
appropriate error message in case of a failure.

This change is as per suggestions from Coccinelle, e.g.,
  drivers/pci/controller/dwc/pcie-qcom-ep.c:556:2-9: line 556 is redundant because platform_get_irq() already prints an error

Related:
  https://lore.kernel.org/all/20210310131913.2802385-1-kw@linux.com/
  https://lore.kernel.org/all/20200802142601.1635926-1-kw@linux.com/

Link: https://lore.kernel.org/r/20211027112931.37182-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-06 11:38:20 +00:00
Hector Martin 75d36df680 PCI: apple: Fix REFCLK1 enable/poll logic
REFCLK1 has req/ack bits that need to be programmed, just like REFCLK0.

Link: https://lore.kernel.org/r/20211117140044.193865-1-marcan@marcan.st
Fixes: 1e33888fbe ("PCI: apple: Add initial hardware bring-up")
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
2021-12-06 10:43:13 +00:00
Manivannan Sadhasivam 3f13d611aa PCI: qcom: Use __be16 type to store return value from cpu_to_be16()
cpu_to_be16() returns __be16 value but the driver uses u16 and that's
incorrect. Fix it by using __be16 as the data type of bdf_be variable.

The issue was spotted by the below sparse warning:

sparse warnings: (new ones prefixed by >>)
>> drivers/pci/controller/dwc/pcie-qcom.c:1305:30: sparse: sparse: incorrect type in initializer (different base types) @@     expected unsigned short [usertype] bdf_be @@     got restricted __be16 [usertype] @@
   drivers/pci/controller/dwc/pcie-qcom.c:1305:30: sparse:     expected unsigned short [usertype] bdf_be
   drivers/pci/controller/dwc/pcie-qcom.c:1305:30: sparse:     got restricted __be16 [usertype]

Link: https://lore.kernel.org/r/20211130080924.266116-1-manivannan.sadhasivam@linaro.org
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
2021-12-06 10:29:43 +00:00
Pali Rohár 2070b2ddea PCI: aardvark: Fix checking for MEM resource type
IORESOURCE_MEM_64 is not a resource type but a type flag.

Remove incorrect check for type IORESOURCE_MEM_64.

Link: https://lore.kernel.org/r/20211125160148.26029-2-kabel@kernel.org
Fixes: 64f160e19e ("PCI: aardvark: Configure PCIe resources from 'ranges' DT property")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-06 10:17:16 +00:00
Christoph Hellwig b80892ca02 memremap: remove support for external pgmap refcounts
No driver is left using the external pgmap refcount, so remove the
code to support it.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20211028151017.50234-1-hch@lst.de
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-12-04 12:46:09 -08:00
Jakub Kicinski 8581fd402a treewide: Add missing includes masked by cgroup -> bpf dependency
cgroup.h (therefore swap.h, therefore half of the universe)
includes bpf.h which in turn includes module.h and slab.h.
Since we're about to get rid of that dependency we need
to clean things up.

v2: drop the cpu.h include from cacheinfo.h, it's not necessary
and it makes riscv sensitive to ordering of include files.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Acked-by: Krzysztof Wilczyński <kw@linux.com>
Acked-by: Peter Chen <peter.chen@kernel.org>
Acked-by: SeongJae Park <sj@kernel.org>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/all/20211120035253.72074-1-kuba@kernel.org/  # v1
Link: https://lore.kernel.org/all/20211120165528.197359-1-kuba@kernel.org/ # cacheinfo discussion
Link: https://lore.kernel.org/bpf/20211202203400.1208663-1-kuba@kernel.org
2021-12-03 10:58:13 -08:00
Pali Rohár fdbbe242c1 PCI: aardvark: Disable common PHY when unbinding driver
Disable the PCIe PHY when unbinding driver. This should save some power.

Link: https://lore.kernel.org/r/20211130172913.9727-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:49 +00:00
Pali Rohár 759dec2e3d PCI: aardvark: Disable link training when unbinding driver
Disable link training circuit in driver unbind sequence. We want to
leave link training in the same state as it was before the driver was
probed.

Link: https://lore.kernel.org/r/20211130172913.9727-11-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:49 +00:00
Pali Rohár 1f54391be8 PCI: aardvark: Assert PERST# when unbinding driver
Put the PCIe card into reset by asserting PERST# signal when unbinding
driver. It doesn't make sense to leave the card working if it can't
communicate with the host. This should also save some power.

Link: https://lore.kernel.org/r/20211130172913.9727-10-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:49 +00:00
Pali Rohár 2f040a17f5 PCI: aardvark: Fix memory leak in driver unbind
Free config space for emulated root bridge when unbinding driver to fix
memory leak. Do it after disabling and masking all interrupts, since
aardvark interrupt handler accesses config space of emulated root
bridge.

Link: https://lore.kernel.org/r/20211130172913.9727-9-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:49 +00:00
Pali Rohár 13bcdf07cb PCI: aardvark: Mask all interrupts when unbinding driver
Ensure that no interrupt can be triggered after driver unbind.

Link: https://lore.kernel.org/r/20211130172913.9727-8-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:49 +00:00
Pali Rohár a46f2f6dd4 PCI: aardvark: Disable bus mastering when unbinding driver
Ensure that after driver unbind PCIe cards are not able to forward
memory and I/O requests in the upstream direction.

Link: https://lore.kernel.org/r/20211130172913.9727-7-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:49 +00:00
Pali Rohár a4ca7948e1 PCI: aardvark: Comment actions in driver remove method
Add two more comments into the advk_pcie_remove() method.

Link: https://lore.kernel.org/r/20211130172913.9727-6-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:49 +00:00
Pali Rohár 7d8dc1f7cd PCI: aardvark: Clear all MSIs at setup
We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).

Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,
to ensure that we don't start receiving spurious interrupts.

Use this new mask in advk_pcie_handle_msi();

Link: https://lore.kernel.org/r/20211130172913.9727-5-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:49 +00:00
Pali Rohár 1d3e170344 PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge
PCI aardvark hardware supports access to DEVCAP2, DEVCTL2, LNKCAP2 and
LNKCTL2 configuration registers of PCIe core via PCIE_CORE_PCIEXP_CAP.
Export them via emulated software root bridge.

Link: https://lore.kernel.org/r/20211130172913.9727-4-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:48 +00:00
Pali Rohár 8ea673a8b3 PCI: pci-bridge-emul: Add definitions for missing capabilities registers
pci-bridge-emul driver already allocates buffer for capabilities up to the
PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
registers. Add these missing definitions.

Link: https://lore.kernel.org/r/20211130172913.9727-3-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:48 +00:00
Pali Rohár 9319230ac1 PCI: pci-bridge-emul: Add description for class_revision field
The current assignment to the class_revision member

  class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);

can make the reader think that class is at high 16 bits of the member and
revision at low 16 bits.

In reality, class is at high 24 bits, but the class for PCI Bridge Normal
Decode is PCI_CLASS_BRIDGE_PCI << 8.

Change the assignment and add a comment to make this clearer.

Link: https://lore.kernel.org/r/20211130172913.9727-2-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-02 09:55:48 +00:00
Tim Harvey 6e5ebc96ec PCI: dwc: Do not remap invalid res
On imx6 and perhaps others when pcie probes you get a:
imx6q-pcie 33800000.pcie: invalid resource

This occurs because the atu is not specified in the DT and as such it
should not be remapped.

Link: https://lore.kernel.org/r/20211101180243.23761-1-tharvey@gateworks.com
Fixes: 281f1f99cf ("PCI: dwc: Detect number of iATU windows")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
2021-12-02 09:41:43 +00:00
Marek Behún 39bd54d43b Revert "PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge"
This reverts commit 239edf686c.

239edf686c ("PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated
bridge") added support for the Type 1 Expansion ROM BAR at config offset
0x38, based on the register being listed in the Marvell Armada A3720 spec.
But the spec doesn't document it at all for RC mode, and there is no ROM in
the SOC, so remove this emulation for now.

The PCI bridge which represents aardvark's PCIe Root Port has an Expansion
ROM Base Address register at offset 0x30, but its meaning is different than
PCI's Expansion ROM BAR register, although the layout is the same.  (This
is why we thought it does the same thing.)

First: there is no ROM (or part of BootROM) in the A3720 SOC dedicated for
PCIe Root Port (or controller in RC mode) containing executable code that
would initialize the Root Port, suitable for execution in bootloader (this
is how Expansion ROM BAR is used on x86).

Second: in A3720 spec the register (address 0xD0070030) is not documented
at all for Root Complex mode, but similar to other BAR registers, it has an
"entangled partner" in register 0xD0075920, which does address translation
for the BAR in 0xD0070030:

  - the BAR register sets the address from the view of PCIe bus

  - the translation register sets the address from the view of the CPU

The other BAR registers also have this entangled partner, and they can be
used to:

  - in RC mode: address-checking on the receive side of the RC (they can
    define address ranges for memory accesses from remote Endpoints to the
    RC)

  - in Endpoint mode: allow the remote CPU to access memory on A3720

The Expansion ROM BAR has only the Endpoint part documented, but from the
similarities we think that it can also be used in RC mode in that way.

So either Expansion ROM BAR has different meaning (if the hypothesis above
is true), or we don't know it's meaning (since it is not documented for RC
mode).

Remove the register from the emulated bridge accessing functions.

[bhelgaas: summarize reason for removal (first paragraph)]
Fixes: 239edf686c ("PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge")
Link: https://lore.kernel.org/r/20211125160148.26029-3-kabel@kernel.org
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
2021-12-01 21:49:18 -06:00
Pali Rohár 873883f2e9 PCI: mvebu: Remove custom mvebu_pci_host_probe() function
Now after pci_ioremap_io() usage was replaced by devm_pci_remap_iospace()
function, there is no need to use custom mvebu_pci_host_probe() function.
Current implementation of mvebu_pci_host_probe() is same as standard PCI
core function pci_host_probe(). So replace mvebu_pci_host_probe() call by
pci_host_probe() and remove custom mvebu_pci_host_probe() function.

Link: https://lore.kernel.org/r/20211124154116.916-4-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-12-01 17:45:47 +00:00
Marek Vasut d2a14b5498 PCI: rcar: Check if device is runtime suspended instead of __clk_is_enabled()
Replace __clk_is_enabled() with pm_runtime_suspended(),
as __clk_is_enabled() was checking the wrong bus clock
and caused the following build error too:
  arm-linux-gnueabi-ld: drivers/pci/controller/pcie-rcar-host.o: in function `rcar_pcie_aarch32_abort_handler':
  pcie-rcar-host.c:(.text+0xdd0): undefined reference to `__clk_is_enabled'

Link: https://lore.kernel.org/r/20211115204641.12941-1-marek.vasut@gmail.com
Fixes: a115b1bd3a ("PCI: rcar: Add L1 link state fix into data abort hook")
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: linux-renesas-soc@vger.kernel.org
2021-12-01 16:22:56 +00:00
Nirmal Patel 6aab562229 PCI: vmd: Clean up domain before enumeration
During VT-d pass-through, the VMD driver occasionally fails to
enumerate underlying NVMe devices when repetitive reboots are
performed in the guest OS. The issue can be resolved by resetting
VMD root ports for proper enumeration and triggering secondary bus
reset which will also propagate reset through downstream bridges.

Link: https://lore.kernel.org/r/20211116221136.85134-1-nirmal.patel@linux.intel.com
Signed-off-by: Nirmal Patel <nirmal.patel@linux.intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Jon Derrick <jonathan.derrick@linux.dev>
2021-12-01 12:00:07 +00:00
Christophe JAILLET 61f0aa4da3 PCI: xilinx-nwl: Simplify code and fix a memory leak
Allocate space for bitmap in struct nwl_msi at probe time instead of
dynamically allocating the memory at runtime.

This simplifies code (especially error handling paths) and avoid some
open-coded arithmetic in allocator arguments.

This also fixes a potential memory leak. The bitmap was never freed. It
is now part of a managed resource.

Link: https://lore.kernel.org/r/5483f10a44b06aad55728576d489adfa16c3be91.1636279388.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
2021-12-01 09:26:51 +00:00
Hector Martin 754bb7ad29 PCI: apple: Enable clock gating
These pokes are not required to make the PCIe port work, but it sounds
like this should save some power at least.

Link: https://lore.kernel.org/r/20211117141916.197192-1-marcan@marcan.st
Tested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
2021-11-30 16:43:15 +00:00
Rob Herring c7a75d0782 PCI: xgene: Fix IB window setup
Commit 6dce5aa59e ("PCI: xgene: Use inbound resources for setup")
broke PCI support on XGene. The cause is the IB resources are now sorted
in address order instead of being in DT dma-ranges order. The result is
which inbound registers are used for each region are swapped. I don't
know the details about this h/w, but it appears that IB region 0
registers can't handle a size greater than 4GB. In any case, limiting
the size for region 0 is enough to get back to the original assignment
of dma-ranges to regions.

Link: https://lore.kernel.org/all/CA+enf=v9rY_xnZML01oEgKLmvY1NGBUUhnSJaETmXtDtXfaczA@mail.gmail.com/
Link: https://lore.kernel.org/r/20211129173637.303201-1-robh@kernel.org
Fixes: 6dce5aa59e ("PCI: xgene: Use inbound resources for setup")
Reported-by: Stéphane Graber <stgraber@ubuntu.com>
Tested-by: Stéphane Graber <stgraber@ubuntu.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Cc: stable@vger.kernel.org # v5.5+
2021-11-30 14:29:51 +00:00
Pali Rohár c1aa4b55aa PCI: mvebu: Replace pci_ioremap_io() usage by devm_pci_remap_iospace()
Now when ARM architecture code also provides standard PCI core function
pci_remap_iospace(), use its devm_pci_remap_iospace() variant in
pci-mvebu.c driver instead of old ARM-specific pci_ioremap_io() function.

Call devm_pci_remap_iospace() before adding IO resource to host bridge
structure, at the place where it should be.

Link: https://lore.kernel.org/r/20211124154116.916-3-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-11-30 11:10:11 +00:00
Christophe JAILLET 1ed9b961be PCI: xgene-msi: Use bitmap_zalloc() when applicable
'xgene_msi->bitmap' is a bitmap. So use 'bitmap_zalloc()' to simplify code,
improve the semantic and avoid some open-coded arithmetic in allocator
arguments.

Also change the corresponding 'kfree()' into 'bitmap_free()' to keep
consistency.

Link: https://lore.kernel.org/r/32f3bc1fbfbd6ee0815e565012904758ca9eff7e.1635019243.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
2021-11-29 17:29:15 +00:00
Christophe JAILLET 4e0e90539b PCI: qcom: Fix an error handling path in 'qcom_pcie_probe()'
If 'of_device_get_match_data()' fails, previous 'pm_runtime_get_sync()/
pm_runtime_enable()' should be undone.

To fix it, the easiest is to move this block of code before the memory
allocations and the pm_runtime_xxx calls.

Link: https://lore.kernel.org/r/4d03c636193f64907c8dacb17fa71ed05fd5f60c.1636220582.git.christophe.jaillet@wanadoo.fr
Fixes: b89ff41025 ("PCI: qcom: Replace ops with struct pcie_cfg in pcie match data")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
2021-11-29 13:24:24 +00:00
Jianjun Wang ab344fd43f PCI: mediatek-gen3: Disable DVFSRC voltage request
When the DVFSRC (dynamic voltage and frequency scaling resource collector)
feature is not implemented, the PCIe hardware will assert a voltage request
signal when exit from the L1 PM Substates to request a specific Vcore
voltage, but cannot receive the voltage ready signal, which will cause
the link to fail to exit the L1 PM Substates.

Disable DVFSRC voltage request by default, we need to find a common way to
enable it in the future.

Link: https://lore.kernel.org/r/20211015063602.29058-1-jianjun.wang@mediatek.com
Fixes: d3bf75b579 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192")
Tested-by: Qizhong Cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Tzung-Bi Shih <tzungbi@google.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-11-29 12:08:17 +00:00
Heikki Krogerus 0c9e032a45 PCI: Convert to device_create_managed_software_node()
In quirk_huawei_pcie_sva(), device_add_properties() is used to
inject additional device properties, but there is no
device_remove_properties() call anywhere to remove those
properties. The assumption is most likely that the device is
never removed, and the properties therefore do not also never
need to be removed.

Even though it is unlikely that the device is ever removed in
this case, it is safer to make sure that the properties are
also removed if the device ever does get unregistered.

To achieve this, instead of adding a separate quirk for the
case of device removal where device_remove_properties() is
called, using device_create_managed_software_node() instead of
device_add_properties(). Both functions create a software node
(a type of fwnode) that holds the device properties, which is
then assigned to the device very much the same way.

The difference between the two functions is, that
device_create_managed_software_node() guarantees that the
software node (together with the properties) is removed when
the device is removed. The function device_add_property() does
not guarantee that, so the properties added with it should
always be removed with device_remove_properties().

Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-11-24 15:28:01 +01:00
Saheed O. Bolarinwa fa285baf84 PCI/ASPM: Remove struct aspm_latency
The struct aspm_latency is now used only inside pcie_aspm_check_latency().

Replace struct aspm_latency variables with u32 variables and remove struct
aspm_latency.

Link: https://lore.kernel.org/r/20211119193732.12343-5-refactormyself@gmail.com
Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
2021-11-19 16:46:26 -06:00
Saheed O. Bolarinwa 6e332df7c3 PCI/ASPM: Stop caching device L0s, L1 acceptable exit latencies
Previously we calculated the device's acceptable L0s and L1 exit latencies
in pcie_aspm_cap_init() and cached them in struct pcie_link_state.

These values are only used in pcie_aspm_check_latency() where they are
compared with the actual exit latencies of the link.  This path is used
when removing or changing the D state of the device, so it's relatively low
frequency.

To reduce the amount of per-link data we store, remove the acceptable[]
arrays from struct pcie_link_state and calculate them directly from the
already-cached Device Capabilities register when needed.

[bhelgaas: use endpoint->devcap instead of reading it again]
Link: https://lore.kernel.org/r/20211119193732.12343-4-refactormyself@gmail.com
Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-19 16:46:21 -06:00
Saheed O. Bolarinwa 222578dad4 PCI/ASPM: Stop caching link L0s, L1 exit latencies
Previously we calculated the upstream and downstream L0s and L1 exit
latencies of the link in pcie_aspm_cap_init() and cached them in struct
pcie_link_state.latency_*.

These values are only used in pcie_aspm_check_latency() where they are
compared with the acceptable latencies on the link.  This path is used when
removing or changing the D state of the device, so it's relatively low
frequency.

To reduce the amount of per-link data we store, remove the latency_*
entries from struct pcie_link_state and calculate the latencies directly
where they are needed.

Link: https://lore.kernel.org/r/20211119193732.12343-3-refactormyself@gmail.com
Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-19 16:46:09 -06:00
Bolarinwa O. Saheed 43262f001b PCI/ASPM: Move pci_function_0() upward
Move pci_function_0() earlier so we can use it from other functions.

Link: https://lore.kernel.org/r/20211119193732.12343-2-refactormyself@gmail.com
Signed-off-by: Bolarinwa O. Saheed <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
2021-11-19 16:15:43 -06:00
Lukas Wunner 23584c1ed3 PCI: pciehp: Fix infinite loop in IRQ handler upon power fault
The Power Fault Detected bit in the Slot Status register differs from
all other hotplug events in that it is sticky:  It can only be cleared
after turning off slot power.  Per PCIe r5.0, sec. 6.7.1.8:

  If a power controller detects a main power fault on the hot-plug slot,
  it must automatically set its internal main power fault latch [...].
  The main power fault latch is cleared when software turns off power to
  the hot-plug slot.

The stickiness used to cause interrupt storms and infinite loops which
were fixed in 2009 by commits 5651c48cfa ("PCI pciehp: fix power fault
interrupt storm problem") and 99f0169c17 ("PCI: pciehp: enable
software notification on empty slots").

Unfortunately in 2020 the infinite loop issue was inadvertently
reintroduced by commit 8edf5332c3 ("PCI: pciehp: Fix MSI interrupt
race"):  The hardirq handler pciehp_isr() clears the PFD bit until
pciehp's power_fault_detected flag is set.  That happens in the IRQ
thread pciehp_ist(), which never learns of the event because the hardirq
handler is stuck in an infinite loop.  Fix by setting the
power_fault_detected flag already in the hardirq handler.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=214989
Link: https://lore.kernel.org/linux-pci/DM8PR11MB5702255A6A92F735D90A4446868B9@DM8PR11MB5702.namprd11.prod.outlook.com
Fixes: 8edf5332c3 ("PCI: pciehp: Fix MSI interrupt race")
Link: https://lore.kernel.org/r/66eaeef31d4997ceea357ad93259f290ededecfd.1637187226.git.lukas@wunner.de
Reported-by: Joseph Bao <joseph.bao@intel.com>
Tested-by: Joseph Bao <joseph.bao@intel.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org # v4.19+
Cc: Stuart Hayes <stuart.w.hayes@gmail.com>
2021-11-19 12:39:33 -06:00
Kelvin Cao b76521f648 PCI/switchtec: Declare local state_names[] as static
The local state_names[] array is constant and need not be allocated and
populated each time we enter stuser_set_state().  Declare it as static.

See the link below for the discussion.

  https://lore.kernel.org/r/20211014141859.11444-1-kelvin.cao@microchip.com/

[bhelgaas: simplify commit log]
Suggested-by: Krzysztof Wilczyński <kw@linux.com>
Link: https://lore.kernel.org/r/20211119003803.2333-3-kelvin.cao@microchip.com
Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
2021-11-19 12:14:02 -06:00
Kelvin Cao bb17b15813 PCI/switchtec: Add Gen4 automotive device IDs
Advertise support of the Gen4 automotive variants in module's device ID
table and add the same IDs to the list of switchtec quirks.

Link: https://lore.kernel.org/r/20211119003803.2333-2-kelvin.cao@microchip.com
Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
2021-11-19 12:13:50 -06:00
Naveen Naidu c78b9a9cbd PCI: xgene: Use PCI_ERROR_RESPONSE to identify config read errors
Include PCI_ERROR_RESPONSE along with 0xffffffff in the comment about
identifying config read errors. This makes checks for config read errors
easier to find. Comment change only.

Link: https://lore.kernel.org/r/388b9733bd55394581c447be9f3df42ca2c9759c.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-18 14:32:16 -06:00
Naveen Naidu 14e04d0d5e PCI: hv: Use PCI_ERROR_RESPONSE to identify config read errors
Include PCI_ERROR_RESPONSE along with 0xFFFFFFFF in the comment about
identifying config read errors. This makes checks for config read errors
easier to find. Comment change only.

Link: https://lore.kernel.org/r/12124f41cab7d8aa944de05f85d9567bfe157704.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-18 14:32:16 -06:00
Naveen Naidu 3cfdef7a57 PCI: keystone: Use PCI_ERROR_RESPONSE to identify config read errors
Include PCI_ERROR_RESPONSE along with 0xffffffff in the comment about
identifying config read errors. This makes checks for config read errors
easier to find. Comment change only.

Link: https://lore.kernel.org/r/6ae6b071d92052dc511407513e2a7c0035aff9e7.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-18 14:32:08 -06:00
Naveen Naidu 289e3ea3a5 PCI: Use PCI_ERROR_RESPONSE to identify config read errors
Include PCI_ERROR_RESPONSE along with 0xFFFF and 0xFFFFFFFF in the comment
about identifying config read errors. This makes checks for config read
errors easier to find. Comment change only.

Link: https://lore.kernel.org/r/866e2db544df45af70df7e64659bf02e03998ae3.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-18 14:31:43 -06:00
Naveen Naidu a18a025c2f PCI: cpqphp: Use PCI_POSSIBLE_ERROR() to check config reads
When config pci_ops.read() can detect failed PCI transactions, the data
returned to the CPU is PCI_ERROR_RESPONSE (~0 or 0xffffffff).

Obviously a successful PCI config read may *also* return that data if a
config register happens to contain ~0, so it doesn't definitively indicate
an error unless we know the register cannot contain ~0.

Use PCI_POSSIBLE_ERROR() to check the response we get when we read data
from hardware.  This unifies PCI error response checking and makes error
checks consistent and easier to find.

Link: https://lore.kernel.org/r/b12005c0d57bb9d4c8b486724d078b7bd92f8321.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-18 14:13:18 -06:00
Naveen Naidu aa66ea10ba PCI/PME: Use PCI_POSSIBLE_ERROR() to check config reads
When config pci_ops.read() can detect failed PCI transactions, the data
returned to the CPU is PCI_ERROR_RESPONSE (~0 or 0xffffffff).

Obviously a successful PCI config read may *also* return that data if a
config register happens to contain ~0, so it doesn't definitively indicate
an error unless we know the register cannot contain ~0.

Use PCI_POSSIBLE_ERROR() to check the response we get when we read data
from hardware.  This unifies PCI error response checking and makes error
checks consistent and easier to find.

Compile tested only.

Link: https://lore.kernel.org/r/679ce049bccf10df3ca9ef4918ee2c3235afdaea.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-18 14:13:18 -06:00
Naveen Naidu 0242132da2 PCI/DPC: Use PCI_POSSIBLE_ERROR() to check config reads
When config pci_ops.read() can detect failed PCI transactions, the data
returned to the CPU is PCI_ERROR_RESPONSE (~0 or 0xffffffff).

Obviously a successful PCI config read may *also* return that data if a
config register happens to contain ~0, so it doesn't definitively indicate
an error unless we know the register cannot contain ~0.

Use PCI_POSSIBLE_ERROR() to check the response we get when we read data
from hardware.  This unifies PCI error response checking and makes error
checks consistent and easier to find.

Compile tested only.

Link: https://lore.kernel.org/r/9b0632f1f183432149f495cf12bdd5a72cc597a4.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-11-18 14:13:18 -06:00
Naveen Naidu a3b0f10db1 PCI: pciehp: Use PCI_POSSIBLE_ERROR() to check config reads
When config pci_ops.read() can detect failed PCI transactions, the data
returned to the CPU is PCI_ERROR_RESPONSE (~0 or 0xffffffff).

Obviously a successful PCI config read may *also* return that data if a
config register happens to contain ~0, so it doesn't definitively indicate
an error unless we know the register cannot contain ~0.

Use PCI_POSSIBLE_ERROR() to check the response we get when we read data
from hardware.  This unifies PCI error response checking and makes error
checks consistent and easier to find.

Compile tested only.

Link: https://lore.kernel.org/r/e185b052fbfd530df703a36dd31126cb870eed95.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lukas Wunner <lukas@wunner.de>
2021-11-18 14:13:18 -06:00
Naveen Naidu 242f288e82 PCI: vmd: Use PCI_POSSIBLE_ERROR() to check config reads
When config pci_ops.read() can detect failed PCI transactions, the data
returned to the CPU is PCI_ERROR_RESPONSE (~0 or 0xffffffff).

Obviously a successful PCI config read may *also* return that data if a
config register happens to contain ~0, so it doesn't definitively indicate
an error unless we know the register cannot contain ~0.

Use PCI_POSSIBLE_ERROR() to check the response we get when we read data
from hardware.  This unifies PCI error response checking and makes error
checks consistent and easier to find.

Link: https://lore.kernel.org/r/ed01cad87a2e35f3865275b5fb34290817a1ebf8.1637243717.git.naveennaidu479@gmail.com
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Derrick <jonathan.derrick@linux.dev>
2021-11-18 14:13:18 -06:00