Add some basic documentation for LoongArch. LoongArch is a new RISC ISA,
which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit
version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version
(LA64).
Tested-by: Bagas Sanjaya <bagasdotme@gmail.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Co-developed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
ARC processors are supported in upstream kernel since v3.9
and so far there was no documentation about them except some
Device Tree bindings.
Fixing it with the simples set of docs now:
1. Overview with pointers to other informational resources
2. Autogenerated feature table
Note though it's just the very beginning, there will be more
for sure given time as there're many things worth documenting
and in fact even contents itself is avaialble but just spread
in some other places. Now we'll try to keep all here and
then maintain it looking forward to match the state of development.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Vineet Gupta <vgupta@kernel.org>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20211112065059.7273-1-abrodkin@synopsys.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
To declutter the top-level table of contents (the side bar), this
patch reduces the architecture-specfic documentation to one top-level
item, "CPU Architectures".
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20210312152804.2110703-1-j.neuschaefer@gmx.net
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Huacai Chen