Commit Graph

59 Commits

Author SHA1 Message Date
Julia Lawall dfeb693d5a drm/sun4i: constify component_ops structures
These component_ops structures are only used as the second argument to
component_add and component_del, which are declared as const, so the
structures can be declared as const as well.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@

static struct component_ops i@p = { ... };

@ok1@
identifier r.i;
expression e1;
position p;
@@

component_add(e1,&i@p)

@ok2@
identifier r.i;
expression e1;
position p;
@@

component_del(e1, &i@p)

@bad@
position p != {r.p,ok1.p,ok2.p};
identifier r.i;
struct component_ops e;
@@

e@i@p

@depends on !bad disable optional_qualifier@
identifier r.i;
@@

static
+const
 struct component_ops i = { ... };
// </smpl>

The result of the size command before the change is (arm):

   text       data         bss     dec      hex filename
   5266        236           8    5510     1586 sun4i_backend.o
   6393        236           8    6637     19ed sun4i_tcon.o
   3700        368           8    4076      fec sun4i_tv.o
   1668        108           0    1776      6f0 sun6i_drc.o

and after the change:

   text       data         bss     dec     hex filename
   5274        228           8    5510    1586 sun4i_backend.o
   6401        228           8    6637    19ed sun4i_tcon.o
   3708        360           8    4076     fec sun4i_tv.o
   1676        100           0    1776     6f0 sun6i_drc.o

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1478971198-3659-1-git-send-email-Julia.Lawall@lip6.fr
2016-11-13 11:42:48 +01:00
Maxime Ripard 47d7fbb32c drm/sun4i: Add a few formats
The planes can do more than what was previously exposed. Add support for
them.

Since we still have the issue that the primary plane cannot have any alpha
component, we will expose only the non-alpha formats in the primary
formats, and the alpha formats will be exposed in the overlays.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-11-02 19:37:37 +01:00
Chen-Yu Tsai 49c440e87c drm/sun4i: Add compatible strings for A31/A31s display pipelines
The A31's display pipeline has 2 frontends, 2 backends, and 2 TCONs. It
also has new display enhancement blocks, such as the DRC (Dynamic Range
Controller), the DEU (Display Enhancement Unit), and the CMU (Color
Management Unit). It supports HDMI, MIPI DSI, and 2 LCD/LVDS channels.

The A31s display pipeline is almost the same, just without MIPI DSI.
Only the TCON seems to be different, due to the missing mux for MIPI
DSI.

Add compatible strings for both of them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-20 17:59:56 +02:00
Maxime Ripard c222f39904 drm/sun4i: Fix formats usable by the primary plane
Even though all our planes can support the ARGB formats, the lowest plane
(ie the primary plane) cannot use the alpha component, otherwise it will
just result in the transparent area being entirely black.

Since some applications will still require the ARGB format, let's force the
format to XRGB to drop the alpha component entirely.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-09-22 10:10:54 +03:00
Wei Yongjun 9a8aa939ba drm/sun4i: backend: remove redundant dev_err call in sun4i_backend_bind()
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-09-18 21:04:15 +02:00
Maxime Ripard 440d2c7b12 drm/sun4i: backend: Handle the SAT
The A33 has an block called SAT that is part of the backend that needs to
be clocked and out of reset to be able for the backend to operate properly.

Extend the binding to have the SAT resources listed, and claim them when
the backend probes.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-08 09:29:42 +02:00
Maxime Ripard 4a408f1f63 drm/sun4i: support A33 tcon
The A33 has a significantly different pipeline, with components that differ
too.

Make sure we had compatible for them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-08 09:28:51 +02:00
Arnd Bergmann f1b78f0e75 drm: sun4i: print DMA address correctly
The newly added sun4i drm driver prints a dma address using the %x
format string, which cannot work when dma_addr_t is 64 bit,
and gcc warns about this configuration:

drm/sun4i/sun4i_backend.c: In function 'sun4i_backend_update_layer_buffer':
drm/sun4i/sun4i_backend.c:193:84: error: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'dma_addr_t {aka long long unsigned int}' [-Werror=format=]
  DRM_DEBUG_DRIVER("Using GEM @ 0x%x\n", gem->paddr);
drm/sun4i/sun4i_backend.c:201:84: error: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'dma_addr_t {aka long long unsigned int}' [-Werror=format=]
  DRM_DEBUG_DRIVER("Setting buffer address to 0x%x\n", paddr);

This changes the code to use the explicit %pad format string, which
always prints the right length.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-05-30 08:28:33 +02:00
Maxime Ripard 9026e0d122 drm: Add Allwinner A10 Display Engine support
The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.

Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually

Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-28 10:30:05 +02:00