2 Commits

Author	SHA1	Message	Date
Geert Uytterhoeven	89f1b1c614	clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions ... Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3 Hardware User's Manual rev. 0.53E. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2017-03-30 13:25:43 +02:00
Geert Uytterhoeven	9d0c3c6820	clk: shmobile: Add r8a7795 CPG Core Clock Definitions ... Add all R-Car H3 Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3 datasheet (rev. 0.5E). Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and RPCSRC) are not included, as they're used as internal clock sources only. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Magnus Damm <damm+renesas@opensource.se>	2015-10-20 20:36:00 +02:00