During Linux System suspend/resume stress test after System Sleep
enabled, system will stuck sometimes. It is because NICMIX is powered
down, which HSIOMIX(always on) is not powered down. When NICMIX
powering down, HSIOMIX will get a hardware handshake, without HSIO ROOT clk,
the handshake will lose. Then after NICMIX power on when system resume,
the access to HSIOMIX through NICMIX would be broken. So keep HSIO ROOT
always on.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20221028095211.2598312-6-peng.fan@oss.nxp.com
Per Reference Mannual System Clocks Table,
LPIT1 and TPM1 sources from bus_aon_root
LPIT2 and TPM3 sources from bus_wakeup_root
So update driver to reflect that.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20221028095211.2598312-5-peng.fan@oss.nxp.com
Per update Reference Mannual, correct the enet clock parent to
wakeup_axi_root.
Fixes: 24defbe194 ("clk: imx: add i.MX93 clk")
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20221028095211.2598312-3-peng.fan@oss.nxp.com
The anatop base is not unmapped during error handling path, fix it.
Fixes: 24defbe194 ("clk: imx: add i.MX93 clk")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20221028095211.2598312-2-peng.fan@oss.nxp.com
32K usb suspend clock gate is shared with usb_root_clk, this
shared clock gate was initially defined only for usb suspend
clock, usb suspend clk is kept on while system is active or
system sleep with usb wakeup enabled, so usb root clock is
fine with this situation; with the commit cf7f3f4fa9
("clk: imx8mp: fix usb_root_clk parent"), this clock gate is
changed to be for usb root clock, but usb root clock will
be off while usb is suspended, so usb suspend clock will be
gated too, this cause some usb functionalities will not work,
so define this clock to be a shared clock gate to conform with
the real HW status.
Fixes: 9c140d9926 ("clk: imx: Add support for i.MX8MP clock driver")
Cc: stable@vger.kernel.org # v5.19+
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/1664549663-20364-2-git-send-email-jun.li@nxp.com
Correct IMX93_CLK_FLEXSPI1_GATE CCGR setting. Otherwise the flexspi
always can't be assigned to a parent clock when dump the clock tree.
Fixes: 24defbe194 ("clk: imx: add i.MX93 clk")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/1666589199-1199-1-git-send-email-haibo.chen@nxp.com
Support BPMP_CLK_STATE_CHANGE_DENIED by not populating state changing
operations when the flag is set.
Support BPMP_CLK_RATE_PARENT_CHANGE_DENIED by not populating rate or
parent changing operations when the flag is set.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
For some reason the mod clock for the Allwinner F1C100s CIR (infrared
receiver) peripheral was not modeled in the CCU driver.
Add the clock description to the list, and wire it up in the clock list.
By assigning a new clock ID at the end, it extends the number of clocks.
This allows to use the CIR peripheral on any F1C100s series board.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-5-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Rename the header guard of ccu-sun8i-v3s.h from _CCU_SUN8I_H3_H_ to
_CCU_SUN8I_V3S_H_ what corresponding with the file name.
Fixes: d0f11d14b0 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Wei Li <liwei391@huawei.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221108094335.3597008-1-liwei391@huawei.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The RSwitch2 and EtherTSN-IF clocks were accidentally mixed up.
While at it, rename them to better match the (future) documentation.
Fixes: a3b4137a4d ("clk: renesas: r8a779f0: Add Ethernet Switch clocks")
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/99b8b41bd2c5043c9e457862ef4bc144869eca58.1668501212.git.geert+renesas@glider.be
Add support for the display clock controller found on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115155808.10899-2-konrad.dybcio@linaro.org
Add full clock controller support RK3588.
[rebase, integrate fixes from Wyon and Finley, add missing frequencies
to PLL lookup table, update commit message, add GATE_LINK clocks which
downstream handles in its own driver with one DT node per clock]
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com
[dropped module stuff after talking to Sebastian]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
of_device_get_match_data() function should not be used on the device
other than the one matched to the given driver, because it always returns
the match_data of the matched driver. In case of exynos-clkout driver,
the code matched the OF IDs on the PARENT device, so replacing it with
of_device_get_match_data() broke the driver.
This reverts commit 777aaf3d1d.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Fixes: 777aaf3d1d ("clk: samsung: exynos-clkout: Use of_device_get_match_data()")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221108213718.32076-1-m.szyprowski@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
rockchip_clk_add_lookup is only called from within the file,
so it can be made static. The additional checks are removed
with the following reasoning:
1. The data structure is initialized by rockchip_clk_init(),
which is called by all rockchip platforms before the clocks
are registered. Not doing so would result in an incomplete
clock tree at the moment, which is a fatal error. In other
parts of the kernel these kind of checks are usually
omitted, so this was done here. The alternative is adding
a pr_err to inform the kernel programmer adding a new platform
about his incorrect code. Apart from that we are also not
checking if the clock id is within the array boundings.
2. While not used so far by any rockchip platform, 0 is a valid
clock identifier. To align rockchip closer to other ARM
platforms we will start using it with rk3588.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In order to improve the main frequency of CPU, the clock path of CPU is
simplified as follows:
|--\
| \ |--\
--apll--|\ | \ | \
| |--apll_core--| \ | \
--24M---|/ |mux1 |--[gate]--|mux2|---clk_core
| / | /
--gpll--|\ | / |------| /
| |--gpll_core--| / | |--/
--24M---|/ |--/ |
|
-------apll_directly--------------|
When the CPU requests high frequency, we want to use MUX2 select the
"apll_directly".
At low frequencies use MUX1 to select “apll_core" and then MUX2 to
select "apll_core_gate".
However, in this way, the CPU frequency conversion needs to be
in the following order:
1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
sets normal_mode
3. MUX1 select "apll_core", MUX2 select "apll_directly"
So add pre_mux and post_mux options to cover this special requirements.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[rebase]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add RK3588 PLL support fully relying on lookup tables like
the other upstream supported rockchip platforms.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[rebase and modify code to avoid PLL parameter calculation]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Qualcomm SC8280XP platform has two display clock controller
instances, add support for these. Duplication between the two
implementations is reduced by reusing any constant data between the two
sets of clock data.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220926203800.16771-3-quic_bjorande@quicinc.com
The PCIe PLL locking may be unreliable under some circumstance, such as
high or low temperature. If the PLL fails to lock, reset it a try again.
This helps on the S905X4
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
[commit message amend]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/cc80cda0-4dda-2e3e-3fc8-afa97717479b@gmail.com
Currently we loop over meson_parm_read() up to 24mln times.
This results in a unpredictable timeout period. In my case
it's over 5s on a S905X4-based system. Make the timeout
period predictable and set it to 100ms.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/a801afc0-a8f2-a0a4-0f2b-a7201351d563@gmail.com
As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that is
not affected by Spread Spectrum or Fractional Multiplication.
Hence change the parent clocks for the SCIF modules from the S0D12_PER
clock to the SASYNCPERD4 clock (which has the same clock rate), cfr.
R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 24aaff6a6c ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the parent clocks for the HSCIF modules from the S0D3_PER
clock to the SASYNCPERD1 clock (which has the same clock rate), cfr.
R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 080bcd8d59 ("clk: renesas: r8a779f0: Add HSCIF clocks")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Convert the IPQ8074 GCC driver to use parent data instead of global
name matching.
Utilize ARRAY_SIZE for num_parents instead of hardcoding the value.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
SM8150 does not have any of the link_div_clk_src clocks, so
let's disable them for this SoC.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-6-robert.foss@linaro.org
SM8350 supports embedded displayport, but the clocks for this
were previously not accounted for.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-5-robert.foss@linaro.org
All SoC supported by this driver supports the RETAIN_FF_ENABLE flag,
so it should be enabled here.
This feature enables registers to maintain their state after
dis/re-enabling the GDSC.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-3-robert.foss@linaro.org
SM8350 does not have the EDP_GTC clock, so let's disable it
for this SoC.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-2-robert.foss@linaro.org
USB controllers on SM8250 doesn't work after coming back from suspend.
This can be fixed by keeping the USB GDSCs in retention mode so that
hardware can keep them ON and put into rentention mode once the parent
domain goes to a low power state.
Fixes: 3e5770921a ("clk: qcom: gcc: Add global clock controller driver for SM8250")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102091320.66007-1-manivannan.sadhasivam@linaro.org
Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to
ensure set_rate can succeed.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Fixes: 837519775f ("clk: qcom: Add display clock controller driver for SM6350")
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221010155546.73884-1-konrad.dybcio@somainline.org
Use parent_data for the last remaining entry (pll4). This clock is
provided by the lcc device.
Fixes: cb02866f9a ("clk: qcom: gcc-ipq806x: convert parent_names to parent_data")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927113826.246241-3-dmitry.baryshkov@linaro.org
We shouldn't be calling runtime PM APIs from within the genpd
enable/disable path for a couple reasons.
First, this causes an AA lockdep splat[1] because genpd can call into
genpd code again while holding the genpd lock.
WARNING: possible recursive locking detected
5.19.0-rc2-lockdep+ #7 Not tainted
--------------------------------------------
kworker/2:1/49 is trying to acquire lock:
ffffffeea0370788 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30
but task is already holding lock:
ffffffeea03710a8 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&genpd->mlock);
lock(&genpd->mlock);
*** DEADLOCK ***
May be due to missing lock nesting notation
3 locks held by kworker/2:1/49:
#0: 74ffff80811a5748 ((wq_completion)pm){+.+.}-{0:0}, at: process_one_work+0x320/0x5fc
#1: ffffffc008537cf8 ((work_completion)(&genpd->power_off_work)){+.+.}-{0:0}, at: process_one_work+0x354/0x5fc
#2: ffffffeea03710a8 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30
stack backtrace:
CPU: 2 PID: 49 Comm: kworker/2:1 Not tainted 5.19.0-rc2-lockdep+ #7
Hardware name: Google Lazor (rev3 - 8) with KB Backlight (DT)
Workqueue: pm genpd_power_off_work_fn
Call trace:
dump_backtrace+0x1a0/0x200
show_stack+0x24/0x30
dump_stack_lvl+0x7c/0xa0
dump_stack+0x18/0x44
__lock_acquire+0xb38/0x3634
lock_acquire+0x180/0x2d4
__mutex_lock_common+0x118/0xe30
mutex_lock_nested+0x70/0x7c
genpd_lock_mtx+0x24/0x30
genpd_runtime_suspend+0x2f0/0x414
__rpm_callback+0xdc/0x1b8
rpm_callback+0x4c/0xcc
rpm_suspend+0x21c/0x5f0
rpm_idle+0x17c/0x1e0
__pm_runtime_idle+0x78/0xcc
gdsc_disable+0x24c/0x26c
_genpd_power_off+0xd4/0x1c4
genpd_power_off+0x2d8/0x41c
genpd_power_off_work_fn+0x60/0x94
process_one_work+0x398/0x5fc
worker_thread+0x42c/0x6c4
kthread+0x194/0x1b4
ret_from_fork+0x10/0x20
Second, this confuses runtime PM on CoachZ for the camera devices by
causing the camera clock controller's runtime PM usage_count to go
negative after resuming from suspend. This is because runtime PM is
being used on the clock controller while runtime PM is disabled for the
device.
The reason for the negative count is because a GDSC is represented as a
genpd and each genpd that is attached to a device is resumed during the
noirq phase of system wide suspend/resume (see the noirq suspend ops
assignment in pm_genpd_init() for more details). The camera GDSCs are
attached to camera devices with the 'power-domains' property in DT.
Every device has runtime PM disabled in the late system suspend phase
via __device_suspend_late(). Runtime PM is not usable until runtime PM
is enabled in device_resume_early(). The noirq phases run after the
'late' and before the 'early' phase of suspend/resume. When the genpds
are resumed in genpd_resume_noirq(), we call down into gdsc_enable()
that calls pm_runtime_resume_and_get() and that returns -EACCES to
indicate failure to resume because runtime PM is disabled for all
devices.
Upon closer inspection, calling runtime PM APIs like this in the GDSC
driver doesn't make sense. It was intended to make sure the GDSC for the
clock controller providing other GDSCs was enabled, specifically the
MMCX GDSC for the display clk controller on SM8250 (sm8250-dispcc), so
that GDSC register accesses succeeded. That will already happen because
we make the 'dev->pm_domain' a parent domain of each GDSC we register in
gdsc_register() via pm_genpd_add_subdomain(). When any of these GDSCs
are accessed, we'll enable the parent domain (in this specific case
MMCX).
We also remove any getting of runtime PM during registration, because
when a genpd is registered it increments the count on the parent if the
genpd itself is already enabled.
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Johan Hovold <johan+linaro@kernel.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Taniya Das <quic_tdas@quicinc.com>
Cc: Satya Priya <quic_c_skakit@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Reported-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/CAE-0n52xbZeJ66RaKwggeRB57fUAwjvxGxfFMKOKJMKVyFTe+w@mail.gmail.com [1]
Fixes: 1b771839de ("clk: qcom: gdsc: enable optional power domain support")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20221103183030.3594899-1-swboyd@chromium.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
If condition (clkspec.np != pd->dev.of_node) is true, then the driver
ends up in an endless loop, forever, locking up the machine.
Fixes: aad03a66f9 ("clk: renesas: r9a06g032: Add clock domain support")
Reviewed-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Gareth Williams <gareth.williams.jx@renesas.com>
Link: https://lore.kernel.org/r/20221028113834.7496-1-marex@denx.de
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
There are cases where not all CPG_MOD clocks should be assumed to support
PM. For example on the CRU block there is a particular sequence that needs
to be followed to initialize the CSI-2 D-PHY in which individual clocks
need to be turned ON/OFF, due to which Runtime PM support wasn't used by
the CRU CSI-2 driver.
This patch adds support to allow indicating if PM is not supported by the
CPG_MOD clocks. Two new members no_pm_mod_clks and num_no_pm_mod_clks are
added to struct rzg2l_cpg_info so that MOD clocks which do not support PM
can be passed by no_pm_mod_clks[] array and when the driver uses Runtime
PM support the clk ID is matched against the no_pm_mod_clks[] array to see
if the clk is needed to be included as part of Runtime PM.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221026014227.162121-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
We'll need the clock IDs in more drivers than just the clock driver from
now on, so let's move them in the firmware header.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220815-rpi-fix-4k-60-v5-2-fe9e7ac8b111@cerno.tech
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
There are few GPU clocks which are powering up the memories
and thus enable the FORCE_MEM_PERIPH always for these clocks
to force the periph_on signal to remain active during halt
state of the clock.
Fixes: a3cc092196 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Fixes: 3e0f01d6c7 ("clk: qcom: Add graphics clock controller driver for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com>
Link: https://lore.kernel.org/r/1666159535-6447-1-git-send-email-quic_c_skakit@quicinc.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Since commit b46fd8dbe8 ("clk: Zero the clk_rate_request structure"),
the clk_core_init_rate_req() function clears the struct clk_rate_request
passed as argument.
However, the default value for max_rate isn't 0 but ULONG_MAX, and we
end up creating a clk_rate_request instance where the maximum rate is 0.
Let's initialize max_rate to ULONG_MAX properly.
Fixes: b46fd8dbe8 ("clk: Zero the clk_rate_request structure")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v1-3-f3ef80518140@cerno.tech
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Since commit c35e84b097 ("clk: Introduce clk_hw_init_rate_request()"),
users that used to initialize their clk_rate_request by initializing
their local structure now rely on clk_hw_init_rate_request().
This function is backed by clk_core_init_rate_req(), which will skip the
initialization if either the pointer to struct clk_core or to struct
clk_rate_request are NULL.
However, the core->parent pointer might be NULL because the clock is
orphan, and we will thus end up with our local struct clk_rate_request
left untouched.
And since clk_hw_init_rate_request() doesn't return an error, we will
then call a determine_rate variant with that unitialized structure.
In order to avoid this, let's clear our clk_rate_request if the pointer
to it is valid but the pointer to struct clk_core isn't.
Fixes: c35e84b097 ("clk: Introduce clk_hw_init_rate_request()")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v1-2-f3ef80518140@cerno.tech
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
If a clock has CLK_SET_RATE_PARENT, but core->parent is NULL (most
likely because it's orphan), callers of clk_core_init_rate_req() will
blindly call this function leading to a very verbose warning.
Since it's a fairly common situation, let's just remove the WARN_ON but
keep the check that prevents us from dereferencing the pointer.
Interestingly, it fixes a regression on the Mediatek MT8195 where the
GPU would stall during a clk_set_rate for its main clock. We couldn't
come up with a proper explanation since the condition is essentially the
same.
It was then assumed that it could be timing related since printing the
warning stacktrace takes a while, but we couldn't replicate the failure
by using fairly large (10ms) mdelays.
Fixes: 262ca38f4b ("clk: Stop forwarding clk_rate_requests to the parent")
Reported-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v1-1-f3ef80518140@cerno.tech
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Make ethrx_src array static, this is local to clk-stm32mp1.c
Fixes: e9ed1ef18a ("clk: stm32mp1: Add parent_data to ETHRX clock")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20221023164607.556118-1-marex@denx.de
Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Remove redundant -1 entries from the parents array and fix
a couple indentation / whitespace issues.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-7-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The X1000's CGU supplies the I2S system clock to the AIC module
and ultimately the audio codec, represented by the "i2s" clock.
It is a simple mux which can either pass through EXCLK or a PLL
multiplied by a fractional divider (the "i2s_pll" clock).
The AIC contains a separate 1/N divider controlled by the I2S
driver, which generates the bit clock from the system clock.
The frame clock is always fixed to 1/64th of the bit clock.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-6-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The set rate hook is called immediately after updating the clock
register but before the spinlock is released. This allows another
register to be updated alongside the main one, which is needed to
handle the I2S divider on some SoCs.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-4-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When the enable bit is undefined, the clock is assumed to be always
on and enable/disable is a no-op. When the stable bit is undefined,
the PLL stable check is a no-op.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-3-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for defining PLL clocks with od_bits = 0, meaning that
OD is fixed to 1 and there is no OD field in the register. In this
case od_max must also be 0, which is enforced with BUG_ON().
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-2-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add a driver for the CPU pll/ARM pll/MIPS pll that is present
in MStar SoCs.
Currently there is no documentation for this block so it's possible
this driver isn't entirely correct.
Only tested on the version of this IP in the MStar/SigmaStar
ARMv7 SoCs.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Co-developed-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Link: https://lore.kernel.org/r/20221022133404.3832-2-romain.perier@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Commit 036177310b ("clk: mxl: Switch from direct readl/writel based IO
to regmap based IO") introduced code resulting in below warning issued
by the smatch static checker.
drivers/clk/x86/clk-lgm.c:441 lgm_cgu_probe() warn: passing zero to 'PTR_ERR'
Fix the warning by replacing incorrect IS_ERR_OR_NULL() with IS_ERR().
Fixes: 036177310b ("clk: mxl: Switch from direct readl/writel based IO to regmap based IO")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/49e339d4739e4ae4c92b00c1b2918af0755d4122.1666695221.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Correct the parent clocks for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC.
Note that HSCIF0 is used for the serial console on the White-Hawk
development board.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCY1kNmwAKCRCKwlD9ZEnx
cHGMAP90gnxw9QtkoODnLu2MbcdNNoB/AFeY4O6snbGcwJTYEQD9GqBXxZ3rhZtR
t34KBpENqFdv5HByIxKQ0OT+yYRZew0=
=oXTL
-----END PGP SIGNATURE-----
Merge tag 'renesas-clk-fixes-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-fixes
Pull Renesas clk driver fixes from Geert Uytterhoeven:
- Correct the parent clocks for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC.
Note that HSCIF0 is used for the serial console on the White-Hawk
development board.
* tag 'renesas-clk-fixes-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779g0: Fix HSCIF parent clocks
clk: renesas: r8a779g0: Add SASYNCPER clocks
Fix typo pll5_mux_dsi_div_params -> mux_dsi_div_params
Fixes the below warning (make W=1):
drivers/clk/renesas/rzg2l-cpg.c:115: warning: Function parameter or member 'mux_dsi_div_params' not described in 'rzg2l_cpg_priv'
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221026012123.159790-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF)
on the Renesas R-Car V4H (R8A779G0) SoC.
While at it, fix table alignment in the definition of the related
RPCSRC internal clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f0609c82e742865be753b67a0a6080f193f405ad.1665583328.git.geert+renesas@glider.be
Add the SASYNCPER internal clock, which is the clock source of the
various SASYNCPERD[124] clocks, to match the clock tree diagram in the
documentation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/18e6765bfc3bf7c3ee5ce93a370d377c1d17728e.1665558014.git.geert+renesas@glider.be
WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if
used from CA55 CPU would result in an unexpected behaviour. Hence drop
WDT2 clock and reset entries.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009231253.15592-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if
used from CA55 CPU would result in an unexpected behaviour. Hence drop
WDT2 clock and reset entries.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009231013.14791-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
- Correct the parent clocks for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC.
Note that HSCIF0 is used for the serial console on the White-Hawk
development board.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCY1kNmwAKCRCKwlD9ZEnx
cHGMAP90gnxw9QtkoODnLu2MbcdNNoB/AFeY4O6snbGcwJTYEQD9GqBXxZ3rhZtR
t34KBpENqFdv5HByIxKQ0OT+yYRZew0=
=oXTL
-----END PGP SIGNATURE-----
Merge tag 'renesas-clk-fixes-for-v6.1-tag1'
clk: renesas: Fixes for v6.1
- Correct the parent clocks for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC.
Note that HSCIF0 is used for the serial console on the White-Hawk
development board.
As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) is clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the parent clocks for the HSCIF modules from the S0D3_PER
clock to the SASYNCPERD1 clock (which has the same clock rate), cfr.
R-Car V4H Hardware User's Manual rev. 0.54.
Fixes: 0ab55cf183 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/b7928abc8b9f53d5b06ec8624342f449de3d24ec.1665147497.git.geert+renesas@glider.be
"div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
2 to achieve a by 4 division, thus their parents are the respective
"div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
This leads to the kernel thinking "div4"s and everything under them run
at 2x the clock speed. Fix this.
Fixes: 45bd8166a1 ("clk: samsung: Add initial Exynos7885 clock driver")
Signed-off-by: David Virag <virag.david003@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20221013151341.151208-1-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
On R-Car V4H, all PLLs except PLL5 support Spread Spectrum and/or
Fractional Multiplication to reduce electromagnetic interference.
Add the SASYNCPER and SASYNCPERD[124] clocks, which are used as clock
sources for modules that must not be affected by Spread Spectrum and/or
Fractional Multiplication.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/d0f35c35e1f96c5a649ab477e7ba5d8025957cd0.1665147497.git.geert+renesas@glider.be
Simplify the driver using devm_regulator_get_enable() instead of
open-coding the devm_add_action_or_reset().
A (minor?) functional change is that we don't print an error in case of a
deferred probe. Now we also print the error no matter which of the
involved calls caused the failure.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Link: https://lore.kernel.org/r/1f46b06be44527a93cd0bfd5de2fa8e2899524ab.1660934107.git.mazziesaccount@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This entire Kconfig file is only included within the if COMMON_CLK
section of the drivers/clk/Kconfig file. That makes the depends on
COMMON_CLK here redundant. Remove it.
Cc: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20221003203103.2705007-1-sboyd@kernel.org
One of the clock entry "dcl" clk has some HW limitations. One is that
its rate can only by changed by changing its parent clk's rate & two is
that HW does not support enable/disable for this clk.
Handle above two limitations by adding relevant flags. Add standard flag
CLK_SET_RATE_PARENT to handle rate change and add driver internal flag
DIV_CLK_NO_MASK to handle enable/disable.
Fixes: d058fd9e89 ("clk: intel: Add CGU clock driver for a new SoC")
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/a4770e7225f8a0c03c8ab2ba80434a4e8e9afb17.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In MxL's LGM SoC, gate clocks can be controlled either from CGU clk driver
i.e. this driver or directly from power management driver/daemon. It is
dependent on the power policy/profile requirements of the end product.
To support such use cases, provide option to override gate clks enable/disable
by adding a flag GATE_CLK_HW which controls if these gate clks are controlled
by HW i.e. this driver or overridden in order to allow it to be controlled
by power profiles instead.
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/bdc9c89317b5d338a6c4f1d49386b696e947a672.1665642720.git.rtanwar@maxlinear.com
[sboyd@kernel.org: Add braces on many line if-else]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Patch 1/4 of this patch series switches from direct readl/writel
based register access to regmap based register access. Instead
of using direct readl/writel, regmap API's are used to read, write
& read-modify-write clk registers. Regmap API's already use their
own spinlocks to serialize the register accesses across multiple
cores in which case additional driver spinlocks becomes redundant.
Hence, remove redundant spinlocks from driver in this patch 2/4.
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/a8a02c8773b88924503a9fdaacd37dd2e6488bf3.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Earlier version of driver used direct io remapped register read
writes using readl/writel. But we need secure boot access which
is only possible when registers are read & written using regmap.
This is because the security bus/hook is written & coupled only
with regmap layer.
Switch the driver from direct readl/writel based register accesses
to regmap based register accesses.
Additionally, update the license headers to latest status.
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/2610331918206e0e3bd18babb39393a558fb34f9.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
If devm_clk_hw_register_mux() fails in clk_mt8195_topck_probe(), it should return
error code.
Fixes: deeb2af77c ("clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20221009025056.35311-1-yangyingliang@huawei.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
With the aim of dropping direct selects of drivers from Kconfig.socs,
default the SiFive clock drivers to the value of SOC_SIFIVE.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221005171348.167476-2-conor@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add custom I2C accessors to this driver, since the regular I2C regmap ones
do not generate the exact I2C transfers required by the chip. On I2C write,
it is mandatory to send transfer length first, on read the chip returns the
transfer length in first byte. Instead of always reading back 8 bytes, which
is the default and also the size of the entire register file, set BCP register
to 1 to read out 1 byte which is less wasteful.
Fixes: 892e0ddea1 ("clk: rs9: Add Renesas 9-series PCIe clock generator driver")
Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20220929195521.284497-1-marex@denx.de
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Currently, determine_rate() is not doing any round operation
and due to this it always selects a lower clock source compared
to the closest higher one.
Support sd clk mux round operation by passing
CLK_MUX_ROUND_CLOSEST flag to clk_mux_determine_rate_flags().
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220919084110.3065156-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The clk rate range series needed another week to fully bake. Maxime
fixed the bug that broke clk notifiers and prevented this from being
included in the first pull request. He also added a unit test on top to
make sure it doesn't break so easily again. The majority of the series
fixes up how the clk_set_rate_*() APIs work, particularly around when
the rate constraints are dropped and how they move around when
reparenting clks. Overall it's a much needed improvement to the clk rate
range APIs that used to be pretty broken if you looked sideways.
Beyond the core changes there are a few driver fixes for a compilation
issue or improper data causing clks to fail to register or have the
wrong parents. These are good to get in before the first -rc so that the
system actually boots on the affected devices.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmNLfwARHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSW1uhAA0QMgI8Ywv18PfZi2vWGpAO9sB62DfmdU
sbmsXrfEHdJmXmqT66Ydr8area6loeCagK4Vm/dEcgsf2DwI/xCdDra/ARZjLU49
9VjgC332YLZzk6bHXsY2eqCA2TS6nV4ZoVsonkQv2vezYNLNk7FTgByzIcWpYiY8
RuKEVHnp2yWwk5HrX+pELR0dMDCLTB3p+WVHmnQpyYVK+rcfaSNuDxLTSNXb3yEl
tGTUu4eL09FMwyRZ4iGmRXpvzIacbthYmnGmEtnOYDeFV3k3wBwHPbEizstvS0MI
vv89aHdsOnGgTdzPUZtA6UppByajyoDKbYzb3hw8pUPNNykbq6XmaeBTV7U2O9De
ihfeHVlDjN2HCv1HXfDsCaqlD6WM25T+pmKPT45Zj9b+rKkxloVxsOBuLmMzDgNd
fa1X3qfGfzm5jpZ1SVSTLdRSqOT5Q00nzAgQailUiDoumgdTSN5ZDNPHcIv/Crvn
me+pabVldp0tgYvuNWYr46u7ugwnzUMBVJfnQ+xZTl8xqLQ/yRmkkhB/rsS5RDY1
z6NZ66JyHpSwnaev4Ozjyj8GlRdgDUVHGa/4Vm1jJSbUb7THZGSzjCklZXPxkn8I
VqHNJN+luzaf6bKe85yrgUJKOi8NMZZS//MKWDnOdhDqgqtI0pM4hJX+Tvb2Bc4B
2SA7XzHesKg=
=ZG8Y
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull more clk updates from Stephen Boyd:
"This is the final part of the clk patches for this merge window.
The clk rate range series needed another week to fully bake. Maxime
fixed the bug that broke clk notifiers and prevented this from being
included in the first pull request. He also added a unit test on top
to make sure it doesn't break so easily again. The majority of the
series fixes up how the clk_set_rate_*() APIs work, particularly
around when the rate constraints are dropped and how they move around
when reparenting clks. Overall it's a much needed improvement to the
clk rate range APIs that used to be pretty broken if you looked
sideways.
Beyond the core changes there are a few driver fixes for a compilation
issue or improper data causing clks to fail to register or have the
wrong parents. These are good to get in before the first -rc so that
the system actually boots on the affected devices"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (31 commits)
clk: tegra: Fix Tegra PWM parent clock
clk: at91: fix the build with binutils 2.27
clk: qcom: gcc-msm8660: Drop hardcoded fixed board clocks
clk: mediatek: clk-mux: Add .determine_rate() callback
clk: tests: Add tests for notifiers
clk: Update req_rate on __clk_recalc_rates()
clk: tests: Add missing test case for ranges
clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d
clk: Introduce the clk_hw_get_rate_range function
clk: Zero the clk_rate_request structure
clk: Stop forwarding clk_rate_requests to the parent
clk: Constify clk_has_parent()
clk: Introduce clk_core_has_parent()
clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock
clk: Add our request boundaries in clk_core_init_rate_req
clk: Introduce clk_hw_init_rate_request()
clk: Move clk_core_init_rate_req() from clk_core_round_rate_nolock() to its caller
clk: Change clk_core_init_rate_req prototype
clk: Set req_rate on reparenting
clk: Take into account uncached clocks in clk_set_rate_range()
...
These are three fixes for build warnings that came in during the
merge window.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmNJxugACgkQmmx57+YA
GNmFXxAAnjfruTyGp5zM0SyNxnVI6cncTiS4KjfANYXxPCZmU7frxxzjYB+dk8x8
U8AUjJvupdQ7m1DuAR3708h70GBiRttmvw5wZgB8ln3SX+KuEHo+2O/WkxqR+rYg
IXCUdZCs+20638hahXpedHh9jTNPbXfgkzxFbhQX7uSNfwhAIgHd55JbT4lrqdIk
6Eguls15Zlm94O/v9oWW07jQIIxts2VjSaH13llG0tVyMQiRX4ExI3Wra/JWI9Tv
nqJD6E6Nmv55ei0uAVBS7KHS/kUOtRNJGH2CcM/CN1+2o38mRuC+0gda5Lk2tzzB
saxh7BjXOzJtw8Jrh9FBTptyAUKS5FwvFqnSOwq5Wt9VqFYchYxarv2D/xKPP7FN
77bn3Ea36kICRLL10Z3khaiabyRbS2vyUBgLGgGSZ21F//GU0GyIRy4hPCA8NATu
8a4iAxYs80eNdGl2qLQsvvfh7xe9swwvfm34vm75LbUTonn9+KE2p9K4Hry1KwhO
ZNrrO6MXjcCN3S0UhL1d9/fh8yBsKgP5c9IKLVbAlQzpdxTW81LYz4UKGytHI0Mi
7vPEmz5mvrr9Fpo7+HesjXzwhNu1yo2R4DL24hmApwwm5cxPcfkhW7X1WmMNFqPx
kwnad5ONLDdL5Fum7j/OluqAHalP1uKvuWS5Rou1MnEYV9Dkvhk=
=HTmF
-----END PGP SIGNATURE-----
Merge tag 'arm-fixes-6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"These are three fixes for build warnings that came in during the merge
window"
* tag 'arm-fixes-6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: mmp: Make some symbols static
ARM: spear6xx: Staticize few definitions
clk: spear: Move prototype to accessible header
- Various clk rate range fixes
- Drop clk rate range constraints on clk_put() (redux)
* clk-rate-range: (28 commits)
clk: mediatek: clk-mux: Add .determine_rate() callback
clk: tests: Add tests for notifiers
clk: Update req_rate on __clk_recalc_rates()
clk: tests: Add missing test case for ranges
clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d
clk: Introduce the clk_hw_get_rate_range function
clk: Zero the clk_rate_request structure
clk: Stop forwarding clk_rate_requests to the parent
clk: Constify clk_has_parent()
clk: Introduce clk_core_has_parent()
clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock
clk: Add our request boundaries in clk_core_init_rate_req
clk: Introduce clk_hw_init_rate_request()
clk: Move clk_core_init_rate_req() from clk_core_round_rate_nolock() to its caller
clk: Change clk_core_init_rate_req prototype
clk: Set req_rate on reparenting
clk: Take into account uncached clocks in clk_set_rate_range()
clk: tests: Add some tests for orphan with multiple parents
clk: tests: Add tests for mux with multiple parents
clk: tests: Add tests for single parent mux
...
Commit 8c193f4714 ("pwm: tegra: Optimize period calculation") updated
the period calculation in the Tegra PWM driver and now returns an error
if the period requested is less than minimum period supported. This is
breaking PWM support on various Tegra platforms. For example, on the
Tegra210 Jetson Nano platform this is breaking the PWM fan support and
probing the PWM fan driver now fails ...
pwm-fan pwm-fan: Failed to configure PWM: -22
pwm-fan: probe of pwm-fan failed with error -22
The problem is that the default parent clock for the PWM on Tegra210 is
a 32kHz clock and is unable to support the requested PWM period.
Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.
Fixes: 8c193f4714 ("pwm: tegra: Optimize period calculation")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # TF101 T20
Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # TF201 T30
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # TF700T T3
Link: https://lore.kernel.org/r/20221010100046.6477-1-jonathanh@nvidia.com
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
These two clocks are now registered in the device tree as fixed clocks,
causing a regression in the driver as the clock already exists with
e.g. the name "pxo_board" as the MSM8660 GCC driver probes.
Fix this by just not hard-coding this anymore and everything works
like a charm.
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: baecbda529 ("ARM: dts: qcom: msm8660: fix node names for fixed clocks")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221013140745.7801-1-linus.walleij@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Since commit 262ca38f4b ("clk: Stop forwarding clk_rate_requests
to the parent"), the clk_rate_request is .. as the title says, not
forwarded anymore to the parent: this produces an issue with the
MediaTek clock MUX driver during GPU DVFS on MT8195, but not on
MT8192 or others.
This is because, differently from others, like MT8192 where all of
the clocks in the MFG parents tree are of mtk_mux type, but in the
parent tree of MT8195's MFG clock, we have one mtk_mux clock and
one (clk framework generic) mux clock, like so:
names: mfg_bg3d -> mfg_ck_fast_ref -> top_mfg_core_tmp (or) mfgpll
types: mtk_gate -> mux -> mtk_mux (or) mtk_pll
To solve this issue and also keep the GPU DVFS clocks code working
as expected, wire up a .determine_rate() callback for the mtk_mux
ops; for that, the standard clk_mux_determine_rate_flags() was used
as it was possible to.
This commit was successfully tested on MT6795 Xperia M5, MT8173 Elm,
MT8192 Spherion and MT8195 Tomato; no regressions were seen.
For the sake of some more documentation about this issue here's the
trace of it:
[ 12.211587] ------------[ cut here ]------------
[ 12.211589] WARNING: CPU: 6 PID: 78 at drivers/clk/clk.c:1462 clk_core_init_rate_req+0x84/0x90
[ 12.211593] Modules linked in: stp crct10dif_ce mtk_adsp_common llc rfkill snd_sof_xtensa_dsp
panfrost(+) sbs_battery cros_ec_lid_angle cros_ec_sensors snd_sof_of
cros_ec_sensors_core hid_multitouch cros_usbpd_logger snd_sof gpu_sched
snd_sof_utils fuse ipv6
[ 12.211614] CPU: 6 PID: 78 Comm: kworker/u16:2 Tainted: G W 6.0.0-next-20221011+ #58
[ 12.211616] Hardware name: Acer Tomato (rev2) board (DT)
[ 12.211617] Workqueue: devfreq_wq devfreq_monitor
[ 12.211620] pstate: 40400009 (nZcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 12.211622] pc : clk_core_init_rate_req+0x84/0x90
[ 12.211625] lr : clk_core_forward_rate_req+0xa4/0xe4
[ 12.211627] sp : ffff80000893b8e0
[ 12.211628] x29: ffff80000893b8e0 x28: ffffdddf92f9b000 x27: ffff46a2c0e8bc05
[ 12.211632] x26: ffff46a2c1041200 x25: 0000000000000000 x24: 00000000173eed80
[ 12.211636] x23: ffff80000893b9c0 x22: ffff80000893b940 x21: 0000000000000000
[ 12.211641] x20: ffff46a2c1039f00 x19: ffff46a2c1039f00 x18: 0000000000000000
[ 12.211645] x17: 0000000000000038 x16: 000000000000d904 x15: 0000000000000003
[ 12.211649] x14: ffffdddf9357ce48 x13: ffffdddf935e71c8 x12: 000000000004803c
[ 12.211653] x11: 00000000a867d7ad x10: 00000000a867d7ad x9 : ffffdddf90c28df4
[ 12.211657] x8 : ffffdddf9357a980 x7 : 0000000000000000 x6 : 0000000000000004
[ 12.211661] x5 : ffffffffffffffc8 x4 : 00000000173eed80 x3 : ffff80000893b940
[ 12.211665] x2 : 00000000173eed80 x1 : ffff80000893b940 x0 : 0000000000000000
[ 12.211669] Call trace:
[ 12.211670] clk_core_init_rate_req+0x84/0x90
[ 12.211673] clk_core_round_rate_nolock+0xe8/0x10c
[ 12.211675] clk_mux_determine_rate_flags+0x174/0x1f0
[ 12.211677] clk_mux_determine_rate+0x1c/0x30
[ 12.211680] clk_core_determine_round_nolock+0x74/0x130
[ 12.211682] clk_core_round_rate_nolock+0x58/0x10c
[ 12.211684] clk_core_round_rate_nolock+0xf4/0x10c
[ 12.211686] clk_core_set_rate_nolock+0x194/0x2ac
[ 12.211688] clk_set_rate+0x40/0x94
[ 12.211691] _opp_config_clk_single+0x38/0xa0
[ 12.211693] _set_opp+0x1b0/0x500
[ 12.211695] dev_pm_opp_set_rate+0x120/0x290
[ 12.211697] panfrost_devfreq_target+0x3c/0x50 [panfrost]
[ 12.211705] devfreq_set_target+0x8c/0x2d0
[ 12.211707] devfreq_update_target+0xcc/0xf4
[ 12.211708] devfreq_monitor+0x40/0x1d0
[ 12.211710] process_one_work+0x294/0x664
[ 12.211712] worker_thread+0x7c/0x45c
[ 12.211713] kthread+0x104/0x110
[ 12.211716] ret_from_fork+0x10/0x20
[ 12.211718] irq event stamp: 7102
[ 12.211719] hardirqs last enabled at (7101): [<ffffdddf904ea5a0>] finish_task_switch.isra.0+0xec/0x2f0
[ 12.211723] hardirqs last disabled at (7102): [<ffffdddf91794b74>] el1_dbg+0x24/0x90
[ 12.211726] softirqs last enabled at (6716): [<ffffdddf90410be4>] __do_softirq+0x414/0x588
[ 12.211728] softirqs last disabled at (6507): [<ffffdddf904171d8>] ____do_softirq+0x18/0x24
[ 12.211730] ---[ end trace 0000000000000000 ]---
Fixes: 262ca38f4b ("clk: Stop forwarding clk_rate_requests to the parent")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221011135548.318323-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
We're recently encountered a regression due to the rates reported
through the clk_notifier_data being off when changing parents.
Let's add a test suite and a test to make sure that we do get notified
and with the proper rates.
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221010-rpi-clk-fixes-again-v1-2-d87ba82ac404@cerno.tech
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Commit cb1b1dd962 ("clk: Set req_rate on reparenting") introduced a
new function, clk_core_update_orphan_child_rates(), that updates the
req_rate field on reparenting.
It turns out that that function will interfere with the clock notifying
done by __clk_recalc_rates(). This ends up reporting the new rate in
both the old_rate and new_rate fields of struct clk_notifier_data.
Since clk_core_update_orphan_child_rates() is basically
__clk_recalc_rates() without the notifiers, and with the req_rate field
update, we can drop clk_core_update_orphan_child_rates() entirely, and
make __clk_recalc_rates() update req_rate.
However, __clk_recalc_rates() is being called in several code paths:
when retrieving a rate (most likely through clk_get_rate()), when changing
parents (through clk_set_rate() or clk_hw_reparent()), or when updating
the orphan status (through clk_core_reparent_orphans_nolock(), called at
registration).
Updating req_rate on reparenting or initialisation makes sense, but we
shouldn't do it on clk_get_rate(). Thus an extra flag has been added to
update or not req_rate depending on the context.
Fixes: cb1b1dd962 ("clk: Set req_rate on reparenting")
Link: https://lore.kernel.org/linux-clk/0acc7217-762c-7c0d-45a0-55c384824ce4@samsung.com/
Link: https://lore.kernel.org/linux-clk/Y0QNSx+ZgqKSvPOC@sirena.org.uk/
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Mark Brown <broonie@kernel.org>
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221010-rpi-clk-fixes-again-v1-1-d87ba82ac404@cerno.tech
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Fixes the following W=1 kernel build warning(s):
drivers/clk/spear/spear6xx_clock.c:116:13: warning: no previous prototype for function 'spear6xx_clk_init' [-Wmissing-prototypes]
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
late breaking reports that a patch series to rework clk rate range
support broke boot on some devices, so I've left that branch out of this
PR. Hopefully we can get to that next week, or punt on it and let it
bake another cycle. That means we don't really have any changes to the
core framework this time around besides a few typo fixes. Instead this
is all clk driver updates and fixes.
The usual suspects are here (again), with Qualcomm dominating the
diffstat. We look to have gained support for quite a few new Qualcomm
SoCs and Dmitry worked on updating many of the existing Qualcomm drivers
to use clk_parent_data. After that we have MediaTek drivers getting some
much needed updates, in particular to support GPU DVFS. There are also
quite a few Samsung clk driver patches, but that's mostly because there
was a maintainer change and so last release we missed some of those
patches.
Overall things look normal, but I'm slowly reviewing core framework code
nowadays and that shows given the rate range patches had to be yanked
last minute. Let's hope this situation changes soon.
New Drivers:
- Support for Renesas VersaClock7 clock generator family
- Add Spreadtrum UMS512 SoC clk support
- New clock drivers for MediaTek Helio X10 MT6795
- Display clks for Qualcomm SM6115, SM8450
- GPU clks for Qualcomm SC8280XP
- Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
Deleted Drivers:
- Remove DaVinci DM644x and DM646x clk driver support
Updates:
- Convert Baikal-T1 CCU driver to platform driver
- Split reset support out of primary Baikal-T1 CCU driver
- Add some missing clks required for RPiVid Video Decoder on RaspberryPi
- Mark PLLC critical on bcm2835
- More devm helpers for fixed rate registration
- Various PXA168 clk driver fixes
- Add resets for MediaTek MT8195 PCIe and USB
- Miscellaneous of_node_put() fixes
- Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
- Convert gpio-clk-gate binding to YAML
- Various fixes to AMD/Xilinx Zynqmp clk driver
- Graduate AMD/Xilinx "clocking wizard" driver from staging
- Add missing DPI1_HDMI clock in MT8195 VDOSYS1
- Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
- Fix GPU clock topology on MT8195
- Propogate rate changes from GPU clock gate up the tree
- Clock mux notifiers for GPU-related PLLs
- Conversion of more "simple" drivers to mtk_clk_simple_probe()
- Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
- Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek
- Shrink MT8192 clock driver by deduplicating clock parent lists
- Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
clocks for i.MX8MP
- Drop unnecessary newline in i.MX8MM dt-bindings
- Add more MU1 and SAI clocks dt-bindings Ids
- Introduce slice busy bit check for i.MX93 composite clock
- Introduce white list bit check for i.MX93 composite clock
- Add new i.MX93 clock gate
- Add MU1 and MU2 clocks to i.MX93 clock provider
- Add SAI IPG clocks to i.MX93 clock provider
- add generic clocks for U(S)ART available on SAMA5D2 SoCs
- reset controller support for Polarfire clocks
- .round_rate and .set rate support for clk-mpfs
- code cleanup for clk-mpfs
- PLL support for PolarFire SoC's Clock Conditioning Circuitry
- Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H
- Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
- Add I2C clocks and resets on RZ/V2M
- Document clock support for the RZ/Five SoC
- mux-variant clock using the table variant to select parents
- clock controller for the rv1126 soc
- conversion of rk3128 to yaml and relicensing of the yaml bindings
to gpl2+MIT (following dt-binding guildelines)
- Exynos7885: add FSYS, TREX and MFC clock controllers
- Exynos850: add IS and AUD (audio) clock controllers with bindings
- ExynosAutov9: add FSYS clock controllers with bindings
- ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
controllers, due to duplicated entries. This is an acceptable ABI
break: recently developed/added platform so without legacies, acked
by known users/developers
- ExynosAutov9: add few missing Peric 0/1 gates
- ExynosAutov9: correct register offsets of few Peric 0/1 clocks
- Minor code improvements (use of_device_get_match_data() helper, code
style)
- Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
already maintainers that architecture/platform
- Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention
issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP
- Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
- Qualcomm SDM660 SDCC1 moved to floor clk ops
- Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was
added/fixed
- The Qualcomm MSM8996 CPU clocks are updated with support for ACD
- Support for Qualcomm SDM670 GCC and RPMh clks was added
- Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for many Qualcomm SoCs
- Support for per-reset defined delay on Qualcomm was introduced
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmM/trwRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSUEoA/+LiftbrF8Xtu7lGdxRjqLzRftUmHaUQWO
d0cadtzMsgxzFJsxp99IiJBVJoaYCBOGlnZDx8p/JGv+mmdhl5+yHgKQbR8nEmTk
5A+bdA1okOdm8SPBPMcLvuMjsgmx+DHkuxvnC2hT8ZGfQDoa+6PnObpP30LJkHT0
oVY8g8ScEuHI5eJcNz3UgxAetKeJd+WRQPxKCrjsOeyhWuNAJ7wdTVQjjzH49X4C
RS3fjeHvhr2VZm23IgildY++a6hPO72gtBjEpDRoFwnmWAVqUtxiwptoJJNkC5kB
toD/ndQHOLh/XOJFKgksS20L4JHtSp5F3Ma8sIuOjAXmDCyqMdTQhydnl5Pyrow+
ct8BMUGkx0Sw8pXBJYINtHpwTtIxvLu/sBNqBb/lRCWd8byrPlUnKvF/COcoxp27
miZTwJI28fHU5a2K/46iWZCI5YUvVcnBSz8WbEWWvOltIT8S0JvZozA3KuRm5vys
/k2HaQwO2I0QWQzPjfg6SRlTTWH6p+Hc47fSg7LSM6Scsb7ZraajTM2QOvgn7Mgp
m/136q7jr9mvuLqqy1fBY3F2hDZYNSJX+UfmIFcpCyxvht0GVFN9YCc+Ibgyl2vQ
P3b9LXV2OqhtDJg6ds7v8aPgAGUwUFO8GTPBG1cuom7z5u/kdIpjKaFAyr8wWSuJ
wqPIFevggsA=
=9jI+
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have some late breaking reports that a patch series to rework clk
rate range support broke boot on some devices, so I've left that
branch out of this. Hopefully we can get to that next week, or punt on
it and let it bake another cycle. That means we don't really have any
changes to the core framework this time around besides a few typo
fixes. Instead this is all clk driver updates and fixes.
The usual suspects are here (again), with Qualcomm dominating the
diffstat. We look to have gained support for quite a few new Qualcomm
SoCs and Dmitry worked on updating many of the existing Qualcomm
drivers to use clk_parent_data. After that we have MediaTek drivers
getting some much needed updates, in particular to support GPU DVFS.
There are also quite a few Samsung clk driver patches, but that's
mostly because there was a maintainer change and so last release we
missed some of those patches.
Overall things look normal, but I'm slowly reviewing core framework
code nowadays and that shows given the rate range patches had to be
yanked last minute. Let's hope this situation changes soon.
New Drivers:
- Support for Renesas VersaClock7 clock generator family
- Add Spreadtrum UMS512 SoC clk support
- New clock drivers for MediaTek Helio X10 MT6795
- Display clks for Qualcomm SM6115, SM8450
- GPU clks for Qualcomm SC8280XP
- Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
Deleted Drivers:
- Remove DaVinci DM644x and DM646x clk driver support
Updates:
- Convert Baikal-T1 CCU driver to platform driver
- Split reset support out of primary Baikal-T1 CCU driver
- Add some missing clks required for RPiVid Video Decoder on
RaspberryPi
- Mark PLLC critical on bcm2835
- More devm helpers for fixed rate registration
- Various PXA168 clk driver fixes
- Add resets for MediaTek MT8195 PCIe and USB
- Miscellaneous of_node_put() fixes
- Nuke dt-bindings/clk path (again) by moving headers to
dt-bindings/clock
- Convert gpio-clk-gate binding to YAML
- Various fixes to AMD/Xilinx Zynqmp clk driver
- Graduate AMD/Xilinx "clocking wizard" driver from staging
- Add missing DPI1_HDMI clock in MT8195 VDOSYS1
- Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
- Fix GPU clock topology on MT8195
- Propogate rate changes from GPU clock gate up the tree
- Clock mux notifiers for GPU-related PLLs
- Conversion of more "simple" drivers to mtk_clk_simple_probe()
- Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
- Fixes to previous |struct clk| to |struct clk_hw| conversion on
MediaTek
- Shrink MT8192 clock driver by deduplicating clock parent lists
- Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
clocks for i.MX8MP
- Drop unnecessary newline in i.MX8MM dt-bindings
- Add more MU1 and SAI clocks dt-bindings Ids
- Introduce slice busy bit check for i.MX93 composite clock
- Introduce white list bit check for i.MX93 composite clock
- Add new i.MX93 clock gate
- Add MU1 and MU2 clocks to i.MX93 clock provider
- Add SAI IPG clocks to i.MX93 clock provider
- add generic clocks for U(S)ART available on SAMA5D2 SoCs
- reset controller support for Polarfire clocks
- .round_rate and .set rate support for clk-mpfs
- code cleanup for clk-mpfs
- PLL support for PolarFire SoC's Clock Conditioning Circuitry
- Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car
V4H
- Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
- Add I2C clocks and resets on RZ/V2M
- Document clock support for the RZ/Five SoC
- mux-variant clock using the table variant to select parents
- clock controller for the rv1126 soc
- conversion of rk3128 to yaml and relicensing of the yaml bindings
to gpl2+MIT (following dt-binding guildelines)
- Exynos7885: add FSYS, TREX and MFC clock controllers
- Exynos850: add IS and AUD (audio) clock controllers with bindings
- ExynosAutov9: add FSYS clock controllers with bindings
- ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
controllers, due to duplicated entries. This is an acceptable ABI
break: recently developed/added platform so without legacies, acked
by known users/developers
- ExynosAutov9: add few missing Peric 0/1 gates
- ExynosAutov9: correct register offsets of few Peric 0/1 clocks
- Minor code improvements (use of_device_get_match_data() helper,
code style)
- Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as
he already maintainers that architecture/platform
- Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving
retention issues during suspend of USB on Qualcomm sc7180/sc7280
and SC8280XP
- Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
- Qualcomm SDM660 SDCC1 moved to floor clk ops
- Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018
was added/fixed
- The Qualcomm MSM8996 CPU clocks are updated with support for ACD
- Support for Qualcomm SDM670 GCC and RPMh clks was added
- Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for many Qualcomm SoCs
- Support for per-reset defined delay on Qualcomm was introduced"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits)
clk: qcom: gcc-sm6375: Ensure unsigned long type
clk: qcom: gcc-sm6375: Remove unused variables
clk: qcom: kpss-xcc: convert to parent data API
clk: introduce (devm_)hw_register_mux_parent_data_table API
clk: allow building lan966x as a module
clk: clk-xgene: simplify if-if to if-else
clk: ast2600: BCLK comes from EPLL
clk: clocking-wizard: Depend on HAS_IOMEM
clk: clocking-wizard: Use dev_err_probe() helper
clk: nxp: fix typo in comment
clk: pxa: add a check for the return value of kzalloc()
clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
dt-bindings: clock: vc5: Add 5P49V6975
clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
clk: Renesas versaclock7 ccf device driver
dt-bindings: Renesas versaclock7 device tree bindings
clk: ti: Balance of_node_get() calls for of_find_node_by_name()
clk: imx: scu: fix memleak on platform_device_add() fails
clk: vc5: Use regmap_{set,clear}_bits() where appropriate
...
fixes all over the tree. Other subsystems depending on this change
have been asked to pull an immutable topic branch for this.
* new driver for Microchip PCI1xxxx switch
* heavy refactoring of the Mellanox BlueField driver
* we prefer async probe in the i801 driver now
* the rest is usual driver updates (support for more SoCs, some
refactoring, some feature additions)
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEOZGx6rniZ1Gk92RdFA3kzBSgKbYFAmM7T3IACgkQFA3kzBSg
KbYnAxAAn2SXzpUuuJ05hhk/y89RWHhzSilU+7d+egYfQJlbXUl2WzYx/Wu1BSZM
ciyXuJFIiTywdUiX1r1VeMO80zmQQZXAUG7VygAtOSk7iPSd/qTyL+7J+k1DXADI
hGR+pZLBVfTFyY3d1qHnwKFkzByvQjc2raARv9g7kDxkSQa8xI/sXScmhGYtrLch
DUYUK1F3Sdqbk0FsudJ5Jvd7bZCSS+n+jSR+mrZaOXbkUD4JmDUauW8pAS6UI9in
CxnjZoOLMHdAmC9ADanLeDRXxKz23uNU/9vdZ1/DMYnNsF/TnyWl6Rz/3BFE3YFk
Vq7A1XAK4b3oJAgM92mdvKSkmzBIzkmj02vaVyuNPtRgHZo5MsIcEnWiBhymZY5g
W6BPrjt/8YKRKeNlP/nrZmageklepsXZbUrNQt1ws8i4bbT+CKInKbjKLnBfDgVz
5VSd8M9+y2Jd/JaJhMt9TBNmP0W2RrThxLF06Hux1ue7k4maE7Eljvkzcd4GJ6Un
HYePZMhwCx3aeYsFmFT/V3kHFsfyHUlIFy/vgXTEICsKUpyj/dX96ANWhe+tJdcX
Cknmc+XOVGPm0LPPju4M8WScMjSqNODm1yfDWUe2cRKlxzI45v6x4Oxl8rWD9hb4
KKMGXit0LOtWETlHALffwFCifs6DdaaA0IMUtMQUj8egvys0enE=
=arni
-----END PGP SIGNATURE-----
Merge tag 'i2c-for-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang:
- 'remove' callback converted to return void. Big change with trivial
fixes all over the tree. Other subsystems depending on this change
have been asked to pull an immutable topic branch for this.
- new driver for Microchip PCI1xxxx switch
- heavy refactoring of the Mellanox BlueField driver
- we prefer async probe in the i801 driver now
- the rest is usual driver updates (support for more SoCs, some
refactoring, some feature additions)
* tag 'i2c-for-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (37 commits)
i2c: pci1xxxx: prevent signed integer overflow
i2c: acpi: Replace zero-length array with DECLARE_FLEX_ARRAY() helper
i2c: i801: Prefer async probe
i2c: designware-pci: Use standard pattern for memory allocation
i2c: designware-pci: Group AMD NAVI quirk parts together
i2c: microchip: pci1xxxx: Add driver for I2C host controller in multifunction endpoint of pci1xxxx switch
docs: i2c: slave-interface: return errno when handle I2C_SLAVE_WRITE_REQUESTED
i2c: mlxbf: remove device tree support
i2c: mlxbf: support BlueField-3 SoC
i2c: cadence: Add standard bus recovery support
i2c: mlxbf: add multi slave functionality
i2c: mlxbf: support lock mechanism
macintosh/ams: Adapt declaration of ams_i2c_remove() to earlier change
i2c: riic: Use devm_platform_ioremap_resource()
i2c: mlxbf: remove IRQF_ONESHOT
dt-bindings: i2c: rockchip: add rockchip,rk3128-i2c
dt-bindings: i2c: renesas,rcar-i2c: Add r8a779g0 support
i2c: tegra: Add GPCDMA support
i2c: scmi: Convert to be a platform driver
i2c: rk3x: Add rv1126 support
...
- Miscellaneous of_node_put() fixes
- Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
- Convert gpio-clk-gate binding to YAML
- Various fixes to AMD/Xilinx Zynqmp clk driver
- Graduate AMD/Xilinx "clocking wizard" driver from staging
* clk-ofnode:
clk: ti: Balance of_node_get() calls for of_find_node_by_name()
clk: tegra20: Fix refcount leak in tegra20_clock_init
clk: tegra: Fix refcount leak in tegra114_clock_init
clk: tegra: Fix refcount leak in tegra210_clock_init
clk: sprd: Hold reference returned by of_get_parent()
clk: berlin: Add of_node_put() for of_get_parent()
clk: at91: dt-compat: Hold reference returned by of_get_parent()
clk: qoriq: Hold reference returned by of_get_parent()
clk: oxnas: Hold reference returned by of_get_parent()
clk: st: Hold reference returned by of_get_parent()
clk: tegra: Add missing of_node_put()
clk: meson: Hold reference returned by of_get_parent()
clk: nomadik: Add missing of_node_put()
* clk-bindings:
dt-bindings: clock: drop minItems equal to maxItems
dt-bindings: clock: gpio-gate-clock: Convert to json-schema
dt-bindings: clock: Move versaclock.h to dt-bindings/clock
dt-bindings: clock: Move lochnagar.h to dt-bindings/clock
* clk-cleanup:
clk: allow building lan966x as a module
clk: clk-xgene: simplify if-if to if-else
clk: nxp: fix typo in comment
clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
clkdev: Simplify devm_clk_hw_register_clkdev() function
clkdev: Remove never used devm_clk_release_clkdev()
clk: Remove never used devm_of_clk_del_provider()
clk: pistachio: Fix initconst confusion
clk: clk-npcm7xx: Remove unused struct npcm7xx_clk_gate_data and npcm7xx_clk_div_fixed_data
clk: do not initialize ret
clk: remove extra empty line
clk: Fix comment typo
clk: move from strlcpy with unused retval to strscpy
* clk-zynq:
clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
clk: zynqmp: Check the return type zynqmp_pm_query_data
clk: zynqmp: Add a check for NULL pointer
clk: zynqmp: Replaced strncpy() with strscpy()
clk: zynqmp: Fix stack-out-of-bounds in strncpy`
clk: zynqmp: make bestdiv unsigned
* clk-xilinx:
clk: clocking-wizard: Depend on HAS_IOMEM
clk: clocking-wizard: Use dev_err_probe() helper
clk: clocking-wizard: Update the compatible
clk: clocking-wizard: Fix the reconfig for 5.2
clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs
clk: clocking-wizard: Move clocking-wizard out
dt-bindings: add documentation of xilinx clocking wizard
This PLL frequency needs a UL postfix to avoid compiler warnings on
32-bit architectures.
Fixes: 184fdd873d ("clk: qcom: Add global clock controller driver for SM6375")
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
gcc_parent_data_15 and gcc_parent_map_15 are not used in this driver.
Remove them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20221003211438.25691-1-konrad.dybcio@somainline.org
Fixes: 184fdd873d ("clk: qcom: Add global clock controller driver for SM6375")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the driver to parent data API. From the Documentation pll8_vote
and pxo should be declared in the DTS so fw_name can be used instead of
parent_names. .name is changed to the legacy pxo_board following how
it's declared in other drivers.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20220914144743.17369-2-ansuelsmth@gmail.com
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Set the COMMON_CLK_LAN966X option as a tristate and switch from
builtin_platform_driver() to module_platform_driver() to allow building
and using this driver as a module.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Link: https://lore.kernel.org/r/20220617103306.489466-1-clement.leger@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Replace `if (!pclk->param.csr_reg)` with `else` for simplification
and add curly brackets according to the kernel coding style:
"Do not unnecessarily use braces where a single statement will do."
...
"This does not apply if only one branch of a conditional statement is
a single statement; in the latter case use braces in both branches"
Please refer to:
https://www.kernel.org/doc/html/v5.17-rc8/process/coding-style.html
Signed-off-by: Yihao Han <hanyihao@vivo.com>
Link: https://lore.kernel.org/r/20220408130617.14963-1-hanyihao@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This correction was made in the u-boot SDK recently. There are no
in-tree users of this clock so the impact is minimal.
Fixes: d3d04f6c33 ("clk: Add support for AST2600 SoC")
Link: 8ad54a5ae1
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220421040426.171256-1-joel@jms.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Reimplement acpi_get_pci_dev() using the list of physical devices
associated with the given ACPI device object (Rafael Wysocki).
- Rename ACPI device object reference counting functions (Rafael
Wysocki).
- Rearrange ACPI device object initialization code (Rafael Wysocki).
- Drop parent field from struct acpi_device (Rafael Wysocki).
- Extend the the int3472-tps68470 driver to support multiple consumers
of a single TPS68470 along with the requisite framework-level
support (Daniel Scally).
- Filter out non-memory resources in is_memory(), add a helper
function to find all memory type resources of an ACPI device object
and use that function in 3 places (Heikki Krogerus).
- Add IRQ override quirks for Asus Vivobook K3402ZA/K3502ZA and ASUS
model S5402ZA (Tamim Khan, Kellen Renshaw).
- Fix acpi_dev_state_d0() kerneldoc (Sakari Ailus).
- Fix up suspend-to-idle support on ASUS Rembrandt laptops (Mario
Limonciello).
- Clean up ACPI platform devices support code (Andy Shevchenko, John
Garry).
- Clean up ACPI bus management code (Andy Shevchenko, ye xingchen).
- Add support for multiple DMA windows with different offsets to the
ACPI device enumeration code and use it on LoongArch (Jianmin Lv).
- Clean up the ACPI LPSS (Intel SoC) driver (Andy Shevchenko).
- Add a quirk for Dell Inspiron 14 2-in-1 for StorageD3Enable (Mario
Limonciello).
- Drop unused dev_fmt() and redundant 'HMAT' prefix from the HMAT
parsing code (Liu Shixin).
- Make ACPI FPDT parsing code avoid calling acpi_os_map_memory() on
invalid physical addresses (Hans de Goede).
- Silence missing-declarations warning related to Apple device
properties management (Lukas Wunner).
- Disable frequency invariance in the CPPC library if registers used
by cppc_get_perf_ctrs() are accessed via PCC (Jeremy Linton).
- Add ACPI disabled check to acpi_cpc_valid() (Perry Yuan).
- Fix Tx acknowledge in the PCC address space handler (Huisong Li).
- Use wait_for_completion_timeout() for PCC mailbox operations (Huisong
Li).
- Release resources on PCC address space setup failure path (Rafael
Mendonca).
- Remove unneeded result variables from APEI code (ye xingchen).
- Print total number of records found during BERT log parsing (Dmitry
Monakhov).
- Drop support for 3 _OSI strings that should not be necessary any
more and update documentation on custom _OSI strings so that adding
new ones is not encouraged any more (Mario Limonciello).
- Drop unneeded result variable from ec_write() (ye xingchen).
- Remove the leftover struct acpi_ac_bl from the ACPI AC driver (Hanjun
Guo).
- Reorder symbols to get rid of a few forward declarations in the ACPI
fan driver (Uwe Kleine-König).
- Add Toshiba Satellite/Portege Z830 ACPI backlight quirk (Arvid
Norlander).
- Add ARM DMA-330 controller to the supported list in the ACPI AMBA
driver (Vijayenthiran Subramaniam).
- Drop references to non-functional 01.org/linux-acpi web site from
MAINTAINERS and Kconfig help texts (Rafael Wysocki).
- Replace strlcpy() with unused retval with strscpy() in the ACPI
support code (Wolfram Sang).
- Do not initialize ret in main() in the pfrut utility (Shi junming).
- Drop useless ACPI DSDT override documentation (Rafael Wysocki).
- Fix a few typos and wording mistakes in the ACPI device enumeration
documentation (Jean Delvare).
- Introduce acpi_dev_uid_to_integer() to convert a _UID string into an
integer value (Andy Shevchenko).
- Use acpi_dev_uid_to_integer() in several places to unify _UID
handling (Andy Shevchenko).
- Drop unused pnpid32_to_pnpid() declaration from PNP code (Gaosheng
Cui).
-----BEGIN PGP SIGNATURE-----
iQJGBAABCAAwFiEE4fcc61cGeeHD/fCwgsRv/nhiVHEFAmM7OhkSHHJqd0Byand5
c29ja2kubmV0AAoJEILEb/54YlRx/TkQALQ4TN451dPSj9jcYSNY6qZ/9b4P9Iym
TmRf3wO3+IVZQ8JajeKKRuVKNsW3sC0RcFkJJVmgZkydJBr1Uui2L0ZLzi8axGNy
RlbZm5NyBeFnlP0fA8Gb2iRMXVAUcRIx+RvZCulxxFmgQ8UhoU4wlVZWlEcko4TQ
hGp++lJYcRHR1NbVLSXZhFvzopKLdhGL6vB1Awsjb/I7TVqn23+k4jVRV1DYkIQ7
qgFM+Z7osRVZiVQbaPoOgdykeSa43qXu7Vgs7F/QeJuIiUYx59xDh0/WCJBxnuDM
cHGiaNnvuJghKmCg43X8+joaHEH/jCFyvBVGfiSzRvjz03WOPRs1XztwdEiCi+py
RcZGzrPaXmkCjNeytPRooiifyqm95HT7aMBN/aTvKBXDaGRrfPheXF+i2idl24HM
NrHqMaa0+5qoDGHLUEaf5znlCHfS+3lwq6+lGVrq/UGf6B3cP+9HwOyevEW493JX
4nuv69Y517moR9W3mBU8sAn5mUjshcka7pghRj7QnuoqRqWLbU3lIz8oUDHr84cI
ixpIPvt2KlZ5UjnN9aqu/6k70JkJvy4SrKjnx4iqu03ePmMrRc0Hcpy7+VMlgumD
tgN9aW+YDgy0/Z5QmO1MOvFodVmA5sX6+gnX1neAjuDdIo3LkJptlkO1fCx2jfQu
cgPQk1CtPOos
=xyUK
-----END PGP SIGNATURE-----
Merge tag 'acpi-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull ACPI updates from Rafael Wysocki:
"ACPI and PNP updates for 6.1-rc1.
These rearrange the ACPI device object initialization code (to get rid
of a redundant parent pointer from struct acpi_device among other
things), unify the _UID handling, drop support for some _OSI strings
that should not be necessary any more, add new IDs to support more
hardware and some more quirks, fix a few issues and clean up code all
over.
Specifics:
- Reimplement acpi_get_pci_dev() using the list of physical devices
associated with the given ACPI device object (Rafael Wysocki)
- Rename ACPI device object reference counting functions (Rafael
Wysocki)
- Rearrange ACPI device object initialization code (Rafael Wysocki)
- Drop parent field from struct acpi_device (Rafael Wysocki)
- Extend the the int3472-tps68470 driver to support multiple
consumers of a single TPS68470 along with the requisite
framework-level support (Daniel Scally)
- Filter out non-memory resources in is_memory(), add a helper
function to find all memory type resources of an ACPI device object
and use that function in 3 places (Heikki Krogerus)
- Add IRQ override quirks for Asus Vivobook K3402ZA/K3502ZA and ASUS
model S5402ZA (Tamim Khan, Kellen Renshaw)
- Fix acpi_dev_state_d0() kerneldoc (Sakari Ailus)
- Fix up suspend-to-idle support on ASUS Rembrandt laptops (Mario
Limonciello)
- Clean up ACPI platform devices support code (Andy Shevchenko, John
Garry)
- Clean up ACPI bus management code (Andy Shevchenko, ye xingchen)
- Add support for multiple DMA windows with different offsets to the
ACPI device enumeration code and use it on LoongArch (Jianmin Lv)
- Clean up the ACPI LPSS (Intel SoC) driver (Andy Shevchenko)
- Add a quirk for Dell Inspiron 14 2-in-1 for StorageD3Enable (Mario
Limonciello)
- Drop unused dev_fmt() and redundant 'HMAT' prefix from the HMAT
parsing code (Liu Shixin)
- Make ACPI FPDT parsing code avoid calling acpi_os_map_memory() on
invalid physical addresses (Hans de Goede)
- Silence missing-declarations warning related to Apple device
properties management (Lukas Wunner)
- Disable frequency invariance in the CPPC library if registers used
by cppc_get_perf_ctrs() are accessed via PCC (Jeremy Linton)
- Add ACPI disabled check to acpi_cpc_valid() (Perry Yuan)
- Fix Tx acknowledge in the PCC address space handler (Huisong Li)
- Use wait_for_completion_timeout() for PCC mailbox operations
(Huisong Li)
- Release resources on PCC address space setup failure path (Rafael
Mendonca)
- Remove unneeded result variables from APEI code (ye xingchen)
- Print total number of records found during BERT log parsing (Dmitry
Monakhov)
- Drop support for 3 _OSI strings that should not be necessary any
more and update documentation on custom _OSI strings so that adding
new ones is not encouraged any more (Mario Limonciello)
- Drop unneeded result variable from ec_write() (ye xingchen)
- Remove the leftover struct acpi_ac_bl from the ACPI AC driver
(Hanjun Guo)
- Reorder symbols to get rid of a few forward declarations in the
ACPI fan driver (Uwe Kleine-König)
- Add Toshiba Satellite/Portege Z830 ACPI backlight quirk (Arvid
Norlander)
- Add ARM DMA-330 controller to the supported list in the ACPI AMBA
driver (Vijayenthiran Subramaniam)
- Drop references to non-functional 01.org/linux-acpi web site from
MAINTAINERS and Kconfig help texts (Rafael Wysocki)
- Replace strlcpy() with unused retval with strscpy() in the ACPI
support code (Wolfram Sang)
- Do not initialize ret in main() in the pfrut utility (Shi junming)
- Drop useless ACPI DSDT override documentation (Rafael Wysocki)
- Fix a few typos and wording mistakes in the ACPI device enumeration
documentation (Jean Delvare)
- Introduce acpi_dev_uid_to_integer() to convert a _UID string into
an integer value (Andy Shevchenko)
- Use acpi_dev_uid_to_integer() in several places to unify _UID
handling (Andy Shevchenko)
- Drop unused pnpid32_to_pnpid() declaration from PNP code (Gaosheng
Cui)"
* tag 'acpi-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (79 commits)
ACPI: LPSS: Deduplicate skipping device in acpi_lpss_create_device()
ACPI: LPSS: Replace loop with first entry retrieval
ACPI: x86: s2idle: Add another ID to s2idle_dmi_table
ACPI: x86: s2idle: Fix a NULL pointer dereference
MAINTAINERS: Drop records pointing to 01.org/linux-acpi
ACPI: Kconfig: Drop link to https://01.org/linux-acpi
ACPI: docs: Drop useless DSDT override documentation
ACPI: DPTF: Drop stale link from Kconfig help
ACPI: x86: s2idle: Add a quirk for ASUSTeK COMPUTER INC. ROG Flow X13
ACPI: x86: s2idle: Add a quirk for Lenovo Slim 7 Pro 14ARH7
ACPI: x86: s2idle: Add a quirk for ASUS ROG Zephyrus G14
ACPI: x86: s2idle: Add a quirk for ASUS TUF Gaming A17 FA707RE
ACPI: x86: s2idle: Add module parameter to prefer Microsoft GUID
ACPI: x86: s2idle: If a new AMD _HID is missing assume Rembrandt
ACPI: x86: s2idle: Move _HID handling for AMD systems into structures
platform/x86: int3472: Add board data for Surface Go2 IR camera
platform/x86: int3472: Support multiple gpio lookups in board data
platform/x86: int3472: Support multiple clock consumers
ACPI: bus: Add iterator for dependent devices
ACPI: scan: Add acpi_dev_get_next_consumer_dev()
...
Spelling mistake (triple letters) in comment.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/20220521111145.81697-42-Julia.Lawall@inria.fr
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
kzalloc() is a memory allocation function which can return NULL when
some internal memory errors happen. So it is better to check it to
prevent potential wrong memory access.
Signed-off-by: Xiaoke Wang <xkernel.wang@foxmail.com>
Link: https://lore.kernel.org/r/tencent_2B9817738F38B02844C245946EFF3B407E09@qq.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Update IDT VersaClock 5 driver to support 5P49V6975. The 5P49V6975 is a
member of the VersaClock 6E family and supports four fractional dividers
(FODs), five clock outputs and an internal oscillator.
Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
Link: https://lore.kernel.org/r/20220511053455.360335-2-matthias.fend@emfend.at
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Return the value of_clk_add_hw_provider() directly instead of storing it
in another redundant variable.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Link: https://lore.kernel.org/r/20220906072322.337253-1-ye.xingchen@zte.com.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
pm_runtime_get_sync() will increment pm usage counter.
Forgetting to putting operation will result in reference leak.
Add missing pm_runtime_put_sync in some error paths.
Fixes: 9ac33b0ce8 ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220602030838.52057-1-linmq006@gmail.com
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Renesas Versaclock7 is a family of configurable clock generator ICs
with fractional and integer dividers. This driver has basic support
for the RC21008A device, a clock synthesizer with a crystal input and
8 outputs. The supports changing the FOD and IOD rates, and each
output can be gated.
Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com>
Link: https://lore.kernel.org/r/20220912183613.22213-3-alexander.helms.jy@renesas.com
Tested-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In ti_find_clock_provider(), of_find_node_by_name() will call
of_node_put() for the 'from' argument, possibly putting the node one too
many times. Let's maintain the of_node_get() from the previous search
and only put when we're exiting the function early. This should avoid a
misbalanced reference count on the node.
Fixes: 51f661ef9a ("clk: ti: Add ti_find_clock_provider() to use clock-output-names")
Signed-off-by: Liang He <windhl@126.com>
Link: https://lore.kernel.org/r/20220915031121.4003589-1-windhl@126.com
[sboyd@kernel.org: Rewrite commit text, maintain reference instead of
get again]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
No error handling is performed when platform_device_add()
fails. Add error processing before return, and modified
the return value.
Fixes: 77d8f3068c ("clk: imx: scu: add two cells binding support")
Signed-off-by: Lin Yujun <linyujun809@huawei.com>
Link: https://lore.kernel.org/r/20220914033206.98046-1-linyujun809@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
regmap_set_bits() and regmap_clear_bits() are variations of
regmap_update_bits() that can be used if all bits of the mask have to be
set to either 1 or 0 respectively.
Update the versaclk driver to use regmap_set_bits() and regmap_clear_bits()
where appropriate. This results in slightly more compact code and also
makes the intention of the code clearer which can help with review.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20220719094637.844946-2-lars@metafoo.de
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The devices of the versaclk clock generator family use an I2C control bus.
IO access on an I2C bus can fail for various reasons.
The driver currently ignores the return value of most IO operations. This
results in silent failure. To avoid this check the return value and in case
of an error abort the operation and propagate the error code to the caller.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20220719094637.844946-1-lars@metafoo.de
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
To make clk-mt8365 compilable as a module there are a few function
symbols missing. This patch adds the required EXPORT_SYMBOL_GPL to the
functions.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20220822152652.3499972-4-msp@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Provide a helper that replaces the kzalloc with devm_kzalloc so error
handling gets easier.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20220822152652.3499972-3-msp@baylibre.com
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use devm_add_action_or_reset() instead of devres_alloc() and
devres_add(), which works the same. This will simplify the
code. There is no functional changes.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220623115719.52683-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Platform driver clk-bcm2835 gets an inaccurate clock for VEC (107MHz).
Export VEC clock trough clk-raspberrypi which uses the right PLL to
get an accurate 108MHz.
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
[iivanov: Adapted on top of v5.17-rc6]
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Link: https://lore.kernel.org/r/20220829152154.147250-4-iivanov@suse.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The clk-bcm2835 handling of the pixel clock does not function
correctly when the HDMI power domain is disabled.
The firmware supports it correctly, so add it to the
firmware clock driver.
Acked-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Link: https://lore.kernel.org/r/20220829152154.147250-3-iivanov@suse.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Export clock required for RPiVid video decoder hardware.
Cc: Dom Cobley <popcornmix@gmail.com>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Link: https://lore.kernel.org/r/20220829152154.147250-2-iivanov@suse.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The return value of bcm2835_clock_rate_from_divisor is always unsigned
and also all caller expect this. So fix the declaration accordingly.
Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Link: https://lore.kernel.org/r/20220904141037.38816-1-stefan.wahren@i2se.com
Reviewed-by: Ivan T. Ivanov <iivanov@suse.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It was reported that RPi3[1] and RPi Zero 2W boards have issues with
the Bluetooth. It turns out that when switching from initial to
operation speed host and device no longer can talk each other because
host uses incorrect UART baud rate.
The UART driver used in this case is amba-pl011. Original fix, see
below Github link[2], was inside pl011 module, but somehow it didn't
look as the right place to fix. Beside that this original rounding
function is not exactly perfect for all possible clock values. So I
deiced to move the hack to the platform which actually need it.
The UART clock is initialised to be as close to the requested
frequency as possible without exceeding it. Now that there is a
clock manager that returns the actual frequencies, an expected
48MHz clock is reported as 47999625. If the requested baud rate
== requested clock/16, there is no headroom and the slight
reduction in actual clock rate results in failure.
If increasing a clock by less than 0.1% changes it from ..999..
to ..000.., round it up.
[1] https://bugzilla.suse.com/show_bug.cgi?id=1188238
[2] ab3f1b3953
Cc: Phil Elwell <phil@raspberrypi.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com>
Link: https://lore.kernel.org/r/20220912081306.24662-1-iivanov@suse.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When testing for a series affecting the VEC, it was discovered that
turning off and on the VEC clock is crashing the system.
It turns out that, when disabling the VEC clock, it's the only child of
the PLLC-per clock which will also get disabled. The source of the crash
is PLLC-per being disabled.
It's likely that some other device might not take a clock reference that
it actually needs, but it's unclear which at this point. Let's make
PLLC-per critical so that we don't have that crash.
Reported-by: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220926084509.12233-1-maxime@cerno.tech
Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In accordance with the way the MIPS platform is normally design there are
only six clock sources which need to be available on the kernel start in
order to one end up booting correctly:
+ CPU PLL: needed by the r4k and MIPS GIC timer drivers. The former one is
initialized by the arch code, while the later one is implemented in the
mips-gic-timer.c driver as the OF-declared timer.
+ PCIe PLL: required as a parental clock source for the APB/timer domains.
+ APB clock: needed in order to access all the SoC CSRs at least for the
timer OF-declared drivers.
+ APB Timer{0-2} clocks: these are the DW APB timers which drivers
dw_apb_timer_of.c are implemented as the OF-declared timers.
So as long as the clocks above are available early the kernel will
normally work. Let's convert the Baikal-T1 CCU drivers to the platform
device drivers keeping that in mind.
Generally speaking the conversion isn't that complicated since the driver
infrastructure has been designed as flexible enough for that. First we
need to add a new PLL/Divider clock features flag which indicates the
corresponding clock source as a basic one and that clock sources will be
available on the kernel early boot stages. Second the internal PLL/Divider
descriptors need to be initialized with -EPROBE_DEFER value as the
corresponding clock source is unavailable at the early stages. They will
be allocated and initialized on the Baikal-T1 clock platform driver probe
procedure. Finally the already available PLL/Divider init functions need
to be split up into two ones: init procedure performed in the framework of
the OF-declared clock initialization (of_clk_init()), and the probe
procedure called by the platform devices bus driver. Note the later method
will just continue the system clocks initialization started in the former
one.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20220929225402.9696-9-Sergey.Semin@baikalelectronics.ru
[sboyd@kernel.org: Remove module things because the Kconfig is still
bool]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Aside with a set of the trigger-like resets Baikal-T1 CCU provides two
additional blocks with directly controlled reset signals. In particular it
concerns DDR full and initial resets and various PCIe sub-domains resets.
Let's add the direct reset assertion/de-assertion of the corresponding
flags support into the Baikal-T1 CCU driver then. It will be required at
least for the PCIe platform driver. Obviously the DDR controller isn't
supposed to be fully reset in the kernel, so the corresponding controls
are added just for the sake of the interface implementation completeness.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20220929225402.9696-8-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Before adding the directly controlled resets support it's reasonable to
move the existing resets control functionality into a dedicated object for
the sake of the CCU dividers clock driver simplification. After the new
functionality was added clk-ccu-div.c would have got to a mixture of the
weakly dependent clocks and resets methods. Splitting the methods up into
the two objects will make the code easier to read and maintain. It shall
also improve the code scalability (though hopefully we won't need this
part that much in the future).
The reset control functionality is now implemented in the framework of a
single unit since splitting it up doesn't make much sense due to
relatively simple reset operations. The ccu-rst.c has been designed to be
looking like ccu-div.c or ccu-pll.c with two globally available methods
for the sake of the code unification and better code readability.
This commit doesn't provide any change in the CCU reset implementation
semantics. As before the driver will support the trigger-like CCU resets
only, which are responsible for the AXI-bus, APB-bus and SATA-ref blocks
reset. The assert/de-assert-capable reset controls support will be added
in the next commit.
Note the CCU Clock dividers and resets functionality split up was possible
due to not having any side-effects (at least we didn't found ones) of the
regmap-based concurrent access of the common CCU dividers/reset CSRs.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20220929225402.9696-6-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It turns out the internal SATA reference clock signal will stay
unavailable for the SATA interface consumer until the buffer on it's way
is ungated. So aside with having the actual clock divider enabled we need
to ungate a buffer placed on the signal way to the SATA controller (most
likely some rudiment from the initial SoC release). Seeing the switch flag
is placed in the same register as the SATA-ref clock divider at a
non-standard ffset, let's implement it as a separate clock controller with
the set-rate propagation to the parental clock divider wrapper. As such
we'll be able to disable/enable and still change the original clock source
rate.
Fixes: 353afa3a8d ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20220929225402.9696-5-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC
PTP clocks are generated by two different wrappers with the same constant
divider thus each producing a 156.25 MHz signal. But for some reason both
of these clock sources are gated by a single switch-flag in the CCU
registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks
handled independently we need to define a shared parental gate so the base
clock signal would be switched off only if both of the child-clocks are
disabled.
Note the ID is intentionally set to -2 since we are going to add a one
more internal clock identifier in the next commit.
Fixes: 353afa3a8d ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20220929225402.9696-4-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Most likely due to copy-paste mistake the divider has been set to 10 while
according to the SoC reference manual it's supposed to be 8 thus having
PTP clock frequency of 156.25 MHz.
Fixes: 353afa3a8d ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20220929225402.9696-3-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
We have discovered random glitches during the system boot up procedure.
The problem investigation led us to the weird outcomes: when none of the
Renesas 5P49V6901 ports are explicitly enabled by the kernel driver, the
glitches disappeared. It was a mystery since the SoC external clock
domains were fed with different 5P49V6901 outputs. The driver code didn't
seem like bogus either. We almost despaired to find out a root cause when
the solution has been found for a more modern revision of the chip. It
turned out the 5P49V6901 clock generator stopped its output for a short
period of time during the VC5_OUT_DIV_CONTROL register writing. The same
problem was found for the 5P49V6965 revision of the chip and was
successfully fixed in commit fc336ae622 ("clk: vc5: fix output disabling
when enabling a FOD") by enabling the "bypass_sync" flag hidden inside
"Unused Factory Reserved Register". Even though the 5P49V6901 registers
description and programming guide doesn't provide any intel regarding that
flag, setting it up anyway in the officially unused register completely
eliminated the denoted glitches. Thus let's activate the functionality
submitted in commit fc336ae622 ("clk: vc5: fix output disabling when
enabling a FOD") for the Renesas 5P49V6901 chip too in order to remove the
ports implicit inter-dependency.
Fixes: dbf6b16f56 ("clk: vc5: Add support for IDT VersaClock 5P49V6901")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20220929225402.9696-2-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dev_err() can be replace with dev_err_probe() which will check if error
code is -EPROBE_DEFER.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20220913032228.985852-1-yangyingliang@huawei.com
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The PXA168 has a peculiar setup with the AXI clock enable control for
the SDHC controllers. The bits in the SDH0 register control the AXI
clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2
register control both SDH2 and SDH3. This is modeled with two new
parentless clocks that control the shared bits.
Previously, SDH0 had to be enabled in order for SDH1 to be used, and
when SDH1 was enabled, unused bits in the SDH1 register were being
controlled. This fixes those issues. A future commit will add support
for these new shared clocks to be enabled by the PXA168 SDHC driver.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-13-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
According to the datasheet, only bit 0 of APBC_GPIO should be controlled
for the clock enable. Bit 1 is marked as reserved (always write 0).
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-9-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The TWSI, KPC, PWM, and DFC peripherals didn't have their muxes modeled
in the code, but the PXA168 datasheet shows that they are indeed muxed:
- TWSI can be 31.2 MHz or 62.4 MHz
- KPC can be 32 kHz, 16 kHz, or 26 MHz
- PWM can be 13 MHz or 32 kHz
- DFC can be 156 MHz or 78 MHz
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-8-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The UART, SDHC, LCD, and CCIC peripherals' muxed parent clocks didn't
match the information provided by the PXA168 datasheet:
- The UART clocks can be 58.5 MHz or the UART PLL. Previously, the first
mux option was being calculated as 117 MHz, confirmed on hardware to
be incorrect.
- The SDHC clocks can be 48 MHz, 52 MHz, or 78 MHz. Previously, 48 MHz
and 52 MHz were swapped. 78 MHz wasn't listed as an option.
- The LCD clock can be 624 MHz or 312 Mhz. Previously, it was being
calculated as 312 MHz or 52 MHz.
- The CCIC clock can be 156 MHz or 78 MHz. Previously, it was being
calculated as 312 MHz or 52 MHz.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-7-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jacky Bai