Commit Graph

7 Commits

Author SHA1 Message Date
Andrew Jeffery 5b468cc4b8 dt-bindings: clock: Add AST2500 RMII RCLK definitions
The AST2500 has an explicit gate for the RMII RCLK for each of the two
MACs.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:01:10 +10:30
Lei YU cd88259a72 clk: aspeed: Fix SDCLK name
The SDCLK was named SDCLKCLK, and no one has used this yet.
Fix it.

Signed-off-by: Lei YU <mine260309@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 13:56:06 -07:00
Stephen Boyd fff2e33717 Merge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-next
* clk-imx6sx:
  clk: imx6sl: correct ocram_podf clock type
  clk: imx6sx: disable unnecessary clocks during clock initialization
  clk: imx6sx: add missing lvds2 clock to the clock tree

* clk-imx7d-enet:
  ARM: dts: imx7: correct enet ipg clock
  clk: imx7d: correct enet clock CCGR registers
  clk: imx7d: correct enet phy ref clock gates

* clk-aspeed-24:
  clk: aspeed: Add 24MHz fixed clock
2018-06-04 12:32:24 -07:00
Lei YU 67b6e5cfdb clk: aspeed: Add 24MHz fixed clock
Add a 24MHz fixed clock.
This clock will be used for certain devices, e.g. pwm.

Signed-off-by: Lei YU <mine260309@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01 12:18:42 -07:00
Jae Hyun Yoo e76e56823a clk:aspeed: Fix reset bits for PCI/VGA and PECI
This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.

Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f8 ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15 15:02:23 -07:00
Joel Stanley dcb899c47d clk: aspeed: Support second reset register
The ast2500 has an additional reset register that contains resets not
present in the ast2400. This enables support for this register, and adds
the one reset line that is controlled by it.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-15 14:59:35 -07:00
Joel Stanley 70dad67ab1 dt-bindings: clock: Add ASPEED constants
These will be used by the clock driver and device trees.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-12-21 14:03:04 +10:30