Commit Graph

39 Commits

Author SHA1 Message Date
Qii Wang 63ce8e3df8 i2c: mediatek: Fix send master code at more than 1MHz
There are some omissions in the previous patch about replacing
I2C_MAX_FAST_MODE__FREQ with I2C_MAX_FAST_MODE_PLUS_FREQ and
need to fix it.

Fixes: b44658e755b5("i2c: mediatek: Send i2c master code at more than 1MHz")
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-04-17 22:04:57 +02:00
Qii Wang de96c3943f i2c: mediatek: Move suspend and resume handling to NOIRQ phase
Some i2c device driver indirectly uses I2C driver when it is now
being suspended. The i2c devices driver is suspended during the
NOIRQ phase and this cannot be changed due to other dependencies.
Therefore, we also need to move the suspend handling for the I2C
controller driver to the NOIRQ phase as well.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-01-28 10:54:45 +01:00
Qii Wang 05f6f7271a i2c: mediatek: Fix apdma and i2c hand-shake timeout
With the apdma remove hand-shake signal, it requirs special
operation timing to reset i2c manually, otherwise the interrupt
will not be triggered, i2c transmission will be timeout.

Fixes: 8426fe70cfa4("i2c: mediatek: Add apdma sync in i2c driver")
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-01-05 10:54:37 +01:00
Qii Wang aafced673c i2c: mediatek: move dma reset before i2c reset
The i2c driver default do dma reset after i2c reset, but sometimes
i2c reset will trigger dma tx2rx, then apdma write data to dram
which has been i2c_put_dma_safe_msg_buf(kfree). Move dma reset
before i2c reset in mtk_i2c_init_hw to fix it.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-11-03 22:13:10 +01:00
Qii Wang b44658e755 i2c: mediatek: Send i2c master code at more than 1MHz
The master code needs to being sent when the speed is more than
I2C_MAX_FAST_MODE_PLUS_FREQ, not I2C_MAX_FAST_MODE_FREQ in the
latest I2C-bus specification and user manual.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-09-18 22:50:42 +02:00
Qii Wang ff6f3aff46 i2c: mediatek: Fix generic definitions for bus frequency
The max frequency of mediatek i2c controller driver is
I2C_MAX_HIGH_SPEED_MODE_FREQ, not I2C_MAX_FAST_MODE_PLUS_FREQ.
Fix it.

Fixes: 90224e6468 ("i2c: drivers: Use generic definitions for bus frequencies")
Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-09-18 22:49:24 +02:00
Matthias Brugger b0102a890f i2c: mediatek: Fix i2c_spec_values description
The struct i2c_spec_values have it's members documented but is
missing the starting '@', which leads to warings like:

drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_low_ns' not described in 'i2c_spec_values'

We also delete min_high_ns member as it is not used in the code.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-08-10 11:39:35 +02:00
Qii Wang 789e67ba54 i2c: mediatek: Add i2c compatible for MediaTek MT8192
Add i2c compatible for MT8192. Compare to MT8183 i2c controller,
MT8192 support more then 8GB DMA mode.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-08-05 23:40:49 +02:00
Qii Wang 908d984336 i2c: mediatek: Add access to more than 8GB dram in i2c driver
Newer MTK chip support more than 8GB of dram. Replace support_33bits
with more general dma_max_support and remove mtk_i2c_set_4g_mode.

Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-08-05 23:39:26 +02:00
Qii Wang 8426fe70cf i2c: mediatek: Add apdma sync in i2c driver
With the apdma remove hand-shake signal, it need to keep i2c and
apdma in sync manually.

Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-08-05 23:39:08 +02:00
Qii Wang be5ce0e97c i2c: mediatek: Add i2c ac-timing adjust support
This patch adds a algorithm to calculate some ac-timing parameters
which can fully meet I2C Spec.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-05-20 15:25:55 +02:00
Andy Shevchenko 90224e6468 i2c: drivers: Use generic definitions for bus frequencies
Since we have generic definitions for bus frequencies, let's use them.

Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Robert Richter <rrichter@marvell.com>
Reviewed-by: Thor Thayer <thor.thayer@linux.intel.com>
Acked-by: Elie Morisse <syniurge@gmail.com>
Acked-by: Nehal Shah <nehal-bakulchandra.shah@amd.com>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Oleksij Rempel <o.rempel@pengutronix.de>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
Reviewed-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-03-24 22:36:59 +01:00
Fabien Parent 62931ac2f9 i2c: mt65xx: fix NULL ptr dereference
Since commit abf4923e97 ("i2c: mediatek: disable zero-length transfers
for mt8183"), there is a NULL pointer dereference for all the SoCs
that don't have any quirk. mtk_i2c_functionality is not checking that
the quirks pointer is not NULL before starting to use it.

This commit add a call to i2c_check_quirks which will check whether
the quirks pointer is set, and if so will check if the IP has the
NO_ZERO_LEN quirk.

Fixes: abf4923e97 ("i2c: mediatek: disable zero-length transfers for mt8183")
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Cengiz Can <cengiz@kernel.wtf>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Tested-by: Ulrich Hecht <uli@fpond.eu>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-10-24 20:52:11 +02:00
Hsin-Yi Wang abf4923e97 i2c: mediatek: disable zero-length transfers for mt8183
Quoting from mt8183 datasheet, the number of transfers to be
transferred in one transaction should be set to bigger than 1,
so we should forbid zero-length transfer and update functionality.

Reported-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
[wsa: shortened commit message a little]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-08-30 15:06:17 +02:00
Thomas Gleixner 1802d0beec treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:41 -07:00
Qii Wang 25708278f8 i2c: mediatek: Add i2c support for MediaTek MT8183
Add i2c compatible for MT8183. Compare to MT2712 i2c controller,
MT8183 has different register offsets. Ltiming_reg is added to
adjust low width of SCL. Arb clock and dma_sync are needed.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-04-15 13:40:43 +02:00
Qii Wang a15c91bac6 i2c: mediatek: Add i2c and apdma sync in i2c driver
When i2c and apdma use different source clocks, we should enable
synchronization between them.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-04-15 13:40:42 +02:00
Qii Wang cad6dc5d28 i2c: mediatek: Add arb clock in i2c driver
When two i2c controllers are internally connected to the same
GPIO pins, the arb clock is needed to ensure that the waveforms
do not interfere with each other. And we also need to enable
the interrupt to find arb lost, old i2c controllers also have
the bit.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-04-15 13:40:42 +02:00
Qii Wang bc6eaf1709 i2c: mediatek: Add offsets array for new i2c registers
New i2c registers would have different offsets, so we use different
offsets array to distinguish different i2c registers version.

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-04-15 13:39:52 +02:00
Hsin-Yi Wang bc1a7f75c8 i2c: mediatek: modify threshold passed to i2c_get_dma_safe_msg_buf()
DMA with zero-length transfers doesn't make sense and this HW doesn't
support them at all, so increase the threshold.

Fixes: fc66b39fe3 ("i2c: mediatek: Use DMA safe buffers for i2c transactions")
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
[wsa: reworded commit message]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-03-12 14:09:15 +01:00
qii wang 0056a54b33 i2c: mediatek: remove completion_done()
Completion_done() is useless when we don't use its return value,
so we remove it.

Signed-off-by: qii wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05 14:11:46 +01:00
qii wang 93caa0dab7 i2c: mediatek: speeds is replaced by macros definitions
Different speeds have been defined by macros,
so we use macros definitions.

Signed-off-by: qii wang <qii.wang@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05 14:10:43 +01:00
Jun Gao fc66b39fe3 i2c: mediatek: Use DMA safe buffers for i2c transactions
DMA mode will always be used in i2c transactions, try to allocate
a DMA safe buffer if the buf of struct i2c_msg used is not DMA safe.

Signed-off-by: Jun Gao <jun.gao@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-09-06 20:33:15 +02:00
Ryder Lee 6e29577fc2 i2c: mediatek: use of_device_get_match_data()
The usage of of_device_get_match_data() reduce the code size a bit.

Also, the only way to call mtk_i2c_probe() is to match an entry in
mtk_i2c_of_match[], so of_id cannot be NULL.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-04-30 10:39:28 +02:00
Jun Gao f6762cedbe i2c: mediatek: Enable i2c module clock before i2c registers access.
Make sure i2c module clock has been enabled before i2c registers
access.

Signed-off-by: Jun Gao <jun.gao@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-01-04 00:54:02 +01:00
Jun Gao 5a10e7d7aa i2c: mediatek: Add i2c compatible for MediaTek MT2712
Add i2c compatible for MT2712. Compare to MT8173 i2c controller,
internal divider of i2c source clock need to be configured for
MT2712 i2c speed calculation.

Signed-off-by: Jun Gao <jun.gao@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-01-04 00:53:26 +01:00
Jun Gao 1304fe0916 i2c: mediatek: Add i2c compatible for MediaTek MT7622
Add i2c compatible for MT7622. Compare to MT8173 i2c controller,
MT7622 limits message numbers to 255, and does not support 4GB
DMA mode.

Signed-off-by: Jun Gao <jun.gao@mediatek.com>
Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2017-08-27 15:31:00 +02:00
Jun Gao f2326401b8 i2c: mediatek: send i2c master code at 400k
The speed of sending i2c master code in high-speed mode depends on
source clock, clock-div and TIMING register. The source clock and
clock-div of different SoC are not all the same. In order to send
i2c master code at 400k in high-speed mode, a appropriate value
should be set to TIMING register for a certain source clock and
clock-div.

Signed-off-by: Jun Gao <jun.gao@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2017-07-31 16:02:59 +02:00
Wolfram Sang 1945250d97 i2c: m65xx: drop superfluous quirk structure
All length fields in Linux I2C are u16, so a HW length limitation of 16
bit lengths is not a limitation. Remove the quirk structure.

Tested-by: Jun Gao <jun.gao@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2017-03-08 18:03:41 +01:00
Wolfram Sang ea734404f3 i2c: don't print error when adding adapter fails
The core will do this for us now.

Signed-off-by: Wolfram Sang <wsa-dev@sang-engineering.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Peter Korsgaard <peter@korsgaard.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Neil Horman <nhorman@tuxdriver.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Ray Jui <ray.jui@broadcom.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-08-22 08:19:55 +02:00
Wolfram Sang 0d47ce210a i2c: mt65xx: use new 8 bit address helper function
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-04-11 18:54:59 +02:00
Liguo Zhang f4f4fed626 i2c: mt65xx: add 4GB DMA mode support in i2c driver
If 4GB mode is enabled, we should add 4GB DMA mode support in i2c
driver. Set 4GB mode register to support 4GB mode.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
[wsa: updated commit message]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-12 20:40:15 +01:00
Liguo Zhang 8378d01f60 i2c: mediatek: fix i2c multi transfer issue in high speed mode
For mt8173 platform with auto restart support, when doing i2c multi
transfer in high speed, we should ignore the first restart irq after
the master code, otherwise the first transfer will be discarded.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Reviewed-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-01-03 19:38:22 +01:00
Liguo Zhang 173b77e8d8 i2c: mediatek: add i2c first write then read optimization
For platform with auto restart support, between every transfer,
i2c controller will trigger an interrupt and SW need to handle
it to start new transfer. When doing write-then-read transfer,
instead of restart mechanism, using WRRD mode to have controller
send both transfer in one request to reduce latency.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Reviewed-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-12-01 01:55:45 +01:00
Liguo Zhang 09027e08ac i2c: mediatek: add i2c resume support
mt65xx i2c controller initial setting will be cleared after system suspend,
so we should init mt65xx i2c controller again when system resume.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-10-23 21:58:32 +02:00
Eddie Huang 28c0a8433d i2c: mediatek: Fixup i2c ack error interrupt handling
When occur i2c ack error, i2c controller generate two interrupts,
first is the ack error interrupt, then the complete interrupt.
i2c interrupt handler should keep the two interrupt value, and only
call complete() for the complete interrupt.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-08-11 16:54:47 +02:00
Eddie Huang ea89ef1f7b i2c: mediatek: Reset DMA engine in hardware init function
Reset DMA in hardware init function to avoid unknown hardware state
before do any I2C operation.

Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-08-11 16:53:11 +02:00
Eddie Huang b2ed11e224 I2C: mediatek: Add driver for MediaTek MT8173 I2C controller
Add mediatek MT8173 I2C controller driver. Compare to I2C controller
of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
also increase message size to 64kb.

Signed-off-by: Xudong Chen <xudong.chen@mediatek.com>
Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-01 08:28:23 +09:00
Xudong Chen ce38815d39 I2C: mediatek: Add driver for MediaTek I2C controller
The mediatek SoCs have I2C controller that handle I2C transfer.
This patch include common I2C bus driver.
This driver is compatible with I2C controller on mt65xx/mt81xx.

Signed-off-by: Xudong Chen <xudong.chen@mediatek.com>
Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-01 08:28:09 +09:00