Commit Graph

8 Commits

Author SHA1 Message Date
Chen-Yu Tsai 3b2bd70f03 clk: sunxi: Add support for A80 basic bus clocks
The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new "GT" bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.

As far as I can tell, the GT bus and CCI400 bus clock must be
protected.

This patch adds driver support for peripheral related PLLs and
bus clocks on the A80. The GT and CCI400 clocks are added as well
as these 2 along with the PLLs they are clocked from must not be
disabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:45:48 +02:00
Chen-Yu Tsai 9c8176bfb6 clk: sunxi: Add sun8i MBUS clock support
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-09-27 09:05:43 +02:00
Maxime Ripard 992a56e489 clk: sunxi: Move mod0 clock to a file of its own
Since we know have the ability to declare factors clock outside of clk-sunxi,
create a new mod0 driver to deal with the mod0 clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:03 +02:00
Chen-Yu Tsai 57a1fbf284 clk: sunxi: Add A23 APB0 divider clock support
The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.

This patch adds a separate sun8i-a23-apb0-clk driver to support it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-07 10:46:21 +02:00
Boris BREZILLON c8a76cac19 clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support
The PRCM (Power/Reset/Clock Management) unit provides several clock
devices:
- AR100 clk: used to clock the Power Management co-processor
- AHB0 clk: used to clock the AHB0 bus
- APB0 clk and gates: used to clk peripherals connected to the APB0 bus

Add support for these clks in a separate driver so that they can be probed
as platform devices instead of registered during early init.
This is needed to be able to probe PRCM MFD subdevices.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:02 +02:00
Maxime Ripard 59cb10e32a clk: sunxi: Move the GMAC clock to a file of its own
Since we have a folder of our own, we can actually make use of it by
splitting the huge clock file into several sub drivers.

The gmac clock is pretty easy to deal with, since it's pretty much
isolated and doesn't have any dependency on the other clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:44 +02:00
Maxime Ripard ff01df28e5 clk: sunxi: Move the 24M oscillator to a file of its own
Since we have a folder of our own, we can actually make use of it by
splitting the huge clock file into several sub drivers.

The main oscillator is pretty easy to deal with, since it's pretty much
isolated.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:44 +02:00
Emilio López e874a66977 clk: arm: sunxi: Add a new clock driver for sunxi SOCs
This commit implements the base CPU clocks for sunxi devices. It has
been tested using a slightly modified cpufreq driver from the
linux-sunxi 3.0 tree.

Additionally, document the new bindings introduced by this patch.

Idling:
    / # cat /sys/kernel/debug/clk/clk_summary
       clock                        enable_cnt  prepare_cnt  rate
    ---------------------------------------------------------------------
     osc32k                         0           0            32768
     osc24M_fixed                   0           0            24000000
        osc24M                      0           0            24000000
           apb1_mux                 0           0            24000000
              apb1                  0           0            24000000
           pll1                     0           0            60000000
              cpu                   0           0            60000000
                 axi                0           0            60000000
                    ahb             0           0            60000000
                       apb0         0           0            30000000
     dummy                          0           0            0

After "yes >/dev/null &":
    / # cat /sys/kernel/debug/clk/clk_summary
       clock                        enable_cnt  prepare_cnt  rate
    ---------------------------------------------------------------------
     osc32k                         0           0            32768
     osc24M_fixed                   0           0            24000000
        osc24M                      0           0            24000000
           apb1_mux                 0           0            24000000
              apb1                  0           0            24000000
           pll1                     0           0            1008000000
              cpu                   0           0            1008000000
                 axi                0           0            336000000
                    ahb             0           0            168000000
                       apb0         0           0            84000000
     dummy                          0           0            0

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-27 08:35:34 -07:00