This patch adds the Phytium Multimedia Card Interface (MCI) driver.
Signed-off-by: Cheng Quan <chengquan@phytium.com.cn>
Signed-off-by: Lai Xueyu <laixueyu1280@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
(cherry picked from commit ea9baaf77c)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Add support for the Phytium SD host controller driver.
Signed-off-by: Cheng Quan <chengquan@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
(cherry picked from commit e5d35c5590)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Signed-off-by: Feng Jun <fengjun@phytium.com.cn>
Signed-off-by: Song Wenting <songwenting@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
(cherry picked from commit 89e4af5b21)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Phytium Pe220x SoCs includes an 8-channel, 10-bit single ended ADC
This patch add this ADC driver support
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit 0b1dadff13)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
This patch adds support for the 1-wire master interface of Phytium.
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit 06cac346ea)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
This patch adds support for Phytium keypad controller driver on Phytium SoCs.
Signed-off-by: Song Wenting <songwenting@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Signed-off-by: Shuo Li <lishuo@phytium.com.cn>
(cherry picked from commit 8fe5729e2d)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
add new spi-nor flash support
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit 6ab4f737d9)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
add Phytium hwspinlock support for E-series Socs
verifyed on Phytium E2000D
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit effffb8226)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Support for the Phytium JPEG Encoder Engine embedded in the Phytium SOCs.The engine can capture and compress video data from digital or analog sources.
Reviewed-by:maohongbo<maohongbo@phytium.com.cn>
Signed-off-by: Wang Min <wangmin@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
(cherry picked from commit 6f9e10130c)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
adds a simple device driver to expose the BT interface
on Phytium SoC as a character device. Such SOCs are commonly
used as BMCs (BaseBoard Management Controllers) and this driver
implements the BMC side of the BT interface.
(cherry picked from commit ccb23948d0)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Conflicts:
drivers/char/ipmi/Kconfig
drivers/char/ipmi/Makefile
add support for the Phytium QuadSPI controller driver
verifyed on Phytium D2000
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit bce2cf32f3)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Since current Phytium Px210 xHCI host controller does not support
USB Gen2(10Gbps) well, add the XHCI_SLOWDOWN_QUIRK quirk and
modify the limited speed to 5Gbps.
Signed-off-by: Feng Jun <fengjun@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
(cherry picked from commit 50f3eecbba)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Add a driver for fan tachometer and capture counter of Phytium SoCs.
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit cf09b9c0f0)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Add an standalone irqchip driver to handle Phytium PCI legacy interrupt.
When processing legacy INTx interrupts on some Phytium SoCs, the interrupt
status registers have be cleared by software explicitly. We introduce this
standalone irqchip which sits between the PCI legacy interrupt and the GIC,
applying hierarchical irqdomain to integrate the ack in the existing INTx
processing flow.
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit aa66828d35)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
When mapping a LPI, the ITS driver picks the first possible
affinity, which is in most cases CPU0, assuming that if
that's not suitable, someone will come and set the affinity
to something more interesting.
It apparently isn't the case, and people complain of poor
performance when many interrupts are glued to the same CPU.
So let's place the interrupts by finding the "least loaded"
CPU (that is, the one that has the fewer LPIs mapped to it).
So called 'managed' interrupts are an interesting case where
the affinity is actually dictated by the kernel itself, and
we should honor this.
Reported-by: John Garry <john.garry@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: John Garry <john.garry@huawei.com>
Link: https://lore.kernel.org/r/1575642904-58295-1-git-send-email-john.garry@huawei.com
Link: https://lore.kernel.org/r/20200515165752.121296-3-maz@kernel.org
(cherry picked from commit 840775cad1)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
In order to improve the distribution of LPIs among CPUs, let start by
tracking the number of LPIs assigned to CPUs, both for managed and
non-managed interrupts (as separate counters).
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: John Garry <john.garry@huawei.com>
Link: https://lore.kernel.org/r/20200515165752.121296-2-maz@kernel.org
(cherry picked from commit aca60b181c)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
This patch adds the Phytium USBHS DRD controller support.
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit 8e4291c455)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Add XHCI_RESET_ON_RESUME quirk for Phytium Pe220x
Phytium Pe220x xHCI host controller does not have suspend/resume
support. Therefore, use of the XHCI_RESET_ON_RESUME quirk is
mandatory in order to avoid failures after resume.
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit 33d50ca483)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Add initial device tree for Phytium Pe220x SoCs. Phytium Pe220x
series has three specs (Pe2201/Pe2202/Pe2204), distinguished by
the number of CPU core. Besides CPU cores, on-chip peripherals
also vary. Thus, we split them into three separate DTBs.
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit 1d5bb1d501)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
SPI platform driver for Phytium desktop CPUs, such as FT-2000/4 and D2000.
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit 555ae1361a)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
OPTEE driver support for Phytium CPUs, such as FT2000/4 and D2000.
From: Chen Baozi <chenbaozi@phytium.com.cn>
Signed-off-by: Tian wei <tianwei@phytium.com.cn>
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit a0f9867a4d)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
GPIO dirver fix patch. Support Phytiumm Desktop and Embedded CPUs, such as D2000 and E2000.
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit c2a5e2beae)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
SoC's on-chip RGMII.
Signed-off-by: wangzhimin <wangzhimin1179@phytium.com.cn>
(cherry picked from commit 4611897533)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
RTC driver function fix patch Support Phytium desktop and embedded processors, such as D2000 and E2000
Reviewed-by: Wang Nan <wangnan1505@phytium.com.cn>
(cherry picked from commit 00f079b210)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
serial driver function fix patch. Support Phytium desktop and embedded processors, such as D2000.
Reviewed-by:JianChao Sheng <shengjianchao@phytium.com.cn>
(cherry picked from commit 92e0f87830)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Mailbox driver function patch. Support Phytium desktop and embedded processors, such as D2000 and E2000.
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit f6e90a3999)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
maintainer.
Signed-off-by: Chen siyu <chensiyu1321@phytium.com.cn>
(cherry picked from commit 98728ad782)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
I2C driver function fix patch. Support Phytium desktop and embedded processors, such as D2000 and E2000.
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit 5ec3d87d62)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
Long irq latency will affect other latency, such as answer a net
packet. Add a ko to debug long irq latency, account the delay
and show the stack.
Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
(cherry picked from commit 9056a7a86e)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
When compile UnixBench, using command as below:
gcc -o pgms/float -Wall -pedantic -O0 -march=native -mtune=native -I ./src -DTIME -Ddatum=float src/arith.c
It will have an error:
src/arith.c: In function ‘dumb_stuff’:
src/arith.c:89:5: error: ‘+nofp’ feature modifier is incompatible with floating-point code
The root cause is that gcc will read /proc/cpuinfo, get supported features from the line begin with 'Features'.
But tk4 haven't 'Features', it using 'flags' instead, which causing gcc can't get the supported features.
The correct usage is "Features:" always, just a buggy patch change it to
'flags' stupidly. Now change it back.
Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
Signed-off-by: Alex Shi <alexsshi@tencent.com>
commit opencloudos.
In this code snippet, there is a potential risk when cmd is
FUSE_DEV_IOC_RECOVERY, and either fud or fud->fc is empty. This
could lead to severe null pointer issues, so we perform a non-null
check before using them.
Fixes: e1c207b3e7cdfd98("fuse: add a dev ioctl for recovery")
Signed-off-by: Xinghui Li <korantli@tencent.com>
commit 2c88d45edb uptream.
Commit 1340ccfa9a ("x86,sched: Allow topologies where NUMA nodes
share an LLC") added a vendor and model specific check to never
call topology_sane() for Intel Skylake Server systems where NUMA
nodes share an LLC.
Intel Ice Lake and Sapphire Rapids CPUs also enumerate an LLC that is
shared by multiple NUMA nodes. The LLC on these CPUs is shared for
off-package data access but private to the NUMA node for on-package
access. Rather than managing a list of allowable SNC topologies, make
this SNC topology the default, and treat Intel's Cluster-On-Die (COD)
topology as the exception.
In SNC mode, Sky Lake, Ice Lake, and Sapphire Rapids servers do not
emit this warning:
sched: CPU #3's llc-sibling CPU #0 is not on the same node! [node: 1 != 0]. Ignoring dependency.
Intel-SIG: commit 2c88d45edb x86, sched: Treat Intel SNC topology as default,
COD as exception.
Backport for avoiding smpboot warning with SNC mode.
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20210310190233.31752-1-alison.schofield@intel.com
[ Huaisheng Ye amend commit log ]
Signed-off-by: Huaisheng Ye <huaisheng.ye@intel.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
commit e8dbd6445d upstream.
>From Intel IAA spec [1], Intel IAA does not support batch processing.
Two batch related default values for IAA are incorrect in current code:
(1) The max batch size of device is set during device initialization,
that indicates batch is supported. It should be always 0 on IAA.
(2) The max batch size of work queue is set to WQ_DEFAULT_MAX_BATCH (32)
as the default value regardless of Intel DSA or IAA device during
work queue setup and cleanup. It should be always 0 on IAA.
Fix the issues by setting the max batch size of device and max batch
size of work queue to 0 on IAA device, that means batch is not
supported.
[1]: https://cdrdv2.intel.com/v1/dl/getContent/721858
【【SPR内核开发】SPR系列patch合入kernel+kvm】http://tapd.oa.com/Virtualization/prong/stories/view/1020422237869387499
--story=869387499 【SPR内核开发】SPR系列patch合入kernel+kvm
Fixes: 23084545db ("dmaengine: idxd: set max_xfer and max_batch for RO device")
Fixes: 92452a72eb ("dmaengine: idxd: set defaults for wq configs")
Fixes: bfe1d56091 ("dmaengine: idxd: Init and probe for Intel data accelerators")
Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fenghua Yu <fenghua.yu@intel.com>
Link: https://lore.kernel.org/r/20220930201528.18621-2-xiaochen.shen@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Chen Zhuo <sagazchen@tencent.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
commit e130816164 upstream.
Add a macro to test if entry is pointing to the head of the list which is
useful in cases like:
list_for_each_entry(pos, &head, member) {
if (cond)
break;
}
if (list_entry_is_head(pos, &head, member))
return -ERRNO;
that allows to avoid additional variable to be added to track if loop has
not been stopped in the middle.
While here, convert list_for_each_entry*() family of macros to use a new one.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Reviewed-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lkml.kernel.org/r/20200929134342.51489-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Xinghui Li <korantli@tencent.com>
commit 32451614da upstream.
With Architectural Performance Monitoring Version 5, CPUID 10.ECX cpu
leaf indicates the fixed counter enumeration. This extends the previous
count to a bitmap which allows disabling even lower fixed counters.
It could be used by a Hypervisor.
The existing intel_ctrl variable is used to remember the bitmask of the
counters. All code that reads all counters is fixed to check this extra
bitmask.
Intel-SIG: commit 32451614da perf/x86/intel: Support CPUID 10.ECX to
disable fixed counters
Backport for Sapphire Rapids core PMU support.
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Originally-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1611873611-156687-6-git-send-email-kan.liang@linux.intel.com
[ Yunying Sun: amend commit log ]
Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
commit 61b985e3e7 upstream.
Add perf core PMU support for the Intel Sapphire Rapids server, which is
the successor of the Intel Ice Lake server. The enabling code is based
on Ice Lake, but there are several new features introduced.
The event encoding is changed and simplified, e.g., the event codes
which are below 0x90 are restricted to counters 0-3. The event codes
which above 0x90 are likely to have no restrictions. The event
constraints, extra_regs(), and hardware cache events table are changed
accordingly.
A new Precise Distribution (PDist) facility is introduced, which
further minimizes the skid when a precise event is programmed on the GP
counter 0. Enable the Precise Distribution (PDist) facility with :ppp
event. For this facility to work, the period must be initialized with a
value larger than 127. Add spr_limit_period() to apply the limit for
:ppp event.
Two new data source fields, data block & address block, are added in the
PEBS Memory Info Record for the load latency event. To enable the
feature,
- An auxiliary event has to be enabled together with the load latency
event on Sapphire Rapids. A new flag PMU_FL_MEM_LOADS_AUX is
introduced to indicate the case. A new event, mem-loads-aux, is
exposed to sysfs for the user tool.
Add a check in hw_config(). If the auxiliary event is not detected,
return an unique error -ENODATA.
- The union perf_mem_data_src is extended to support the new fields.
- Ice Lake and earlier models do not support block information, but the
fields may be set by HW on some machines. Add pebs_no_block to
explicitly indicate the previous platforms which don't support the new
block fields. Accessing the new block fields are ignored on those
platforms.
A new store Latency facility is introduced, which leverages the PEBS
facility where it can provide additional information about sampled
stores. The additional information includes the data address, memory
auxiliary info (e.g. Data Source, STLB miss) and the latency of the
store access. To enable the facility, the new event (0x02cd) has to be
programed on the GP counter 0. A new flag PERF_X86_EVENT_PEBS_STLAT is
introduced to indicate the event. The store_latency_data() is introduced
to parse the memory auxiliary info.
The layout of access latency field of PEBS Memory Info Record has been
changed. Two latency, instruction latency (bit 15:0) and cache access
latency (bit 47:32) are recorded.
- The cache access latency is similar to previous memory access latency.
For loads, the latency starts by the actual cache access until the
data is returned by the memory subsystem.
For stores, the latency starts when the demand write accesses the L1
data cache and lasts until the cacheline write is completed in the
memory subsystem.
The cache access latency is stored in low 32bits of the sample type
PERF_SAMPLE_WEIGHT_STRUCT.
- The instruction latency starts by the dispatch of the load operation
for execution and lasts until completion of the instruction it belongs
to.
Add a new flag PMU_FL_INSTR_LATENCY to indicate the instruction
latency support. The instruction latency is stored in the bit 47:32
of the sample type PERF_SAMPLE_WEIGHT_STRUCT.
Extends the PERF_METRICS MSR to feature TMA method level 2 metrics. The
lower half of the register is the TMA level 1 metrics (legacy). The
upper half is also divided into four 8-bit fields for the new level 2
metrics. Expose all eight Topdown metrics events to user space.
The full description for the SPR features can be found at Intel
Architecture Instruction Set Extensions and Future Features
Programming Reference, 319433-041.
Intel-SIG: commit 61b985e3e7 perf/x86/intel: Add perf core PMU
support for Sapphire Rapids
Backport for Sapphire Rapids core PMU support.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1611873611-156687-5-git-send-email-kan.liang@linux.intel.com
[ Yunying Sun: amend commit log ]
Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
commit 1ab5f235c1 upstream.
Intel Sapphire Rapids server will introduce 8 metrics events. Intel
Ice Lake only supports 4 metrics events. A perf tool user may mistakenly
use the unsupported events via RAW format on Ice Lake. The user can
still get a value from the unsupported Topdown metrics event once the
following Sapphire Rapids enabling patch is applied.
To enable the 8 metrics events on Intel Sapphire Rapids, the
INTEL_TD_METRIC_MAX has to be updated, which impacts the
is_metric_event(). The is_metric_event() is a generic function.
On Ice Lake, the newly added SPR metrics events will be mistakenly
accepted as metric events on creation. At runtime, the unsupported
Topdown metrics events will be updated.
Add a variable num_topdown_events in x86_pmu to indicate the available
number of the Topdown metrics event on the platform. Apply the number
into is_metric_event(). Only the supported Topdown metrics events
should be created as metrics events.
Apply the num_topdown_events in icl_update_topdown_event() as well. The
function can be reused by the following patch.
Intel-SIG: commit 1ab5f235c1 perf/x86/intel: Filter unsupported
Topdown metrics event
Backport for Sapphire Rapids core PMU support.
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1611873611-156687-4-git-send-email-kan.liang@linux.intel.com
[ Yunying Sun: amend commit log ]
Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
commit 628d923a3c upstream.
Similar to Ice Lake, Intel Sapphire Rapids server also supports the
topdown performance metrics feature. The difference is that Intel
Sapphire Rapids server extends the PERF_METRICS MSR to feature TMA
method level two metrics, which will introduce 8 metrics events. Current
icl_update_topdown_event() only check 4 level one metrics events.
Factor out intel_update_topdown_event() to facilitate the code sharing
between Ice Lake and Sapphire Rapids.
Intel-SIG: commit 628d923a3c perf/x86/intel: Factor out
intel_update_topdown_event()
Backport for Sapphire Rapids core PMU support.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1611873611-156687-3-git-send-email-kan.liang@linux.intel.com
[ Yunying Sun: amend commit log ]
Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
commit 2a6c6b7d7a upstream.
Current PERF_SAMPLE_WEIGHT sample type is very useful to expresses the
cost of an action represented by the sample. This allows the profiler
to scale the samples to be more informative to the programmer. It could
also help to locate a hotspot, e.g., when profiling by memory latencies,
the expensive load appear higher up in the histograms. But current
PERF_SAMPLE_WEIGHT sample type is solely determined by one factor. This
could be a problem, if users want two or more factors to contribute to
the weight. For example, Golden Cove core PMU can provide both the
instruction latency and the cache Latency information as factors for the
memory profiling.
For current X86 platforms, although meminfo::latency is defined as a
u64, only the lower 32 bits include the valid data in practice (No
memory access could last than 4G cycles). The higher 32 bits can be used
to store new factors.
Add a new sample type, PERF_SAMPLE_WEIGHT_STRUCT, to indicate the new
sample weight structure. It shares the same space as the
PERF_SAMPLE_WEIGHT sample type.
Users can apply either the PERF_SAMPLE_WEIGHT sample type or the
PERF_SAMPLE_WEIGHT_STRUCT sample type to retrieve the sample weight, but
they cannot apply both sample types simultaneously.
Currently, only X86 and PowerPC use the PERF_SAMPLE_WEIGHT sample type.
- For PowerPC, there is nothing changed for the PERF_SAMPLE_WEIGHT
sample type. There is no effect for the new PERF_SAMPLE_WEIGHT_STRUCT
sample type. PowerPC can re-struct the weight field similarly later.
- For X86, the same value will be dumped for the PERF_SAMPLE_WEIGHT
sample type or the PERF_SAMPLE_WEIGHT_STRUCT sample type for now.
The following patches will apply the new factors for the
PERF_SAMPLE_WEIGHT_STRUCT sample type.
The field in the union perf_sample_weight should be shared among
different architectures. A generic name is required, but it's hard to
abstract a name that applies to all architectures. For example, on X86,
the fields are to store all kinds of latency. While on PowerPC, it
stores MMCRA[TECX/TECM], which should not be latency. So a general name
prefix 'var$NUM' is used here.
Intel-SIG: commit 2a6c6b7d7a perf/core: Add PERF_SAMPLE_WEIGHT_STRUCT
Backport for Sapphire Rapids core PMU support.
Note: This backported patch has some deviations from upstream version.
To avoid enum hole in perf_event_sample_format struct, we added
PERF_SAMPLE_{AUX,CGROUP,DATA_PAGE_SIZE,CODE_PAGE_SIZE} to file
include/uapi/linux/perf_event.h, but didn't backport the full patchsets
that introducing these enumeration values. To avoid mishandling of these
sampling formats, we added check to perf_copy_attr() in
kernel/events/core.c, to make sure -EINVAL always being returned for
these lack-of-kernel-support sampling formats.
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1611873611-156687-2-git-send-email-kan.liang@linux.intel.com
[ Yunying Sun: amend commit log ]
Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Xinghui Li <korantli@tencent.com>
Jiakun Shuai
Chen Baozi