Commit Graph

53 Commits

Author SHA1 Message Date
Daniel Lezcano f1ebef9e55 dtpm/soc/rk3399: Add the ability to unload the module
The dtpm hierarchy can now be removed with the
dtpm_destroy_hierarchy() function. Add the module_exit() callback so
the module can be unloaded by removing the previously created
hierarchy.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20220130210210.549877-7-daniel.lezcano@linaro.org
2022-02-23 19:46:29 +01:00
Daniel Lezcano b9d6c47a2b rockchip/soc/drivers: Add DTPM description for rk3399
The DTPM framework does support now the hierarchy description.

The platform specific code can call the hierarchy creation function
with an array of struct dtpm_node pointing to their parent.

This patch provides a description of the big / Little CPUs and the
GPU and tie them together under a virtual 'package' name. Only rk3399 is
described now.

The description could be extended in the future with the memory
controller with devfreq.

The description is always a module and it describes the soft
dependencies. The userspace has to load the softdeps module in the
right order.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by; Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220128163537.212248-6-daniel.lezcano@linaro.org
2022-02-04 17:38:09 +01:00
Jiapeng Chong 9e5747c578 soc: rockchip: io-domain: Remove unneeded semicolon
Fix the following coccicheck warnings:

./drivers/soc/rockchip/io-domain.c:118:2-3: Unneeded semicolon.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Link: https://lore.kernel.org/r/1629361749-97977-1-git-send-email-jiapeng.chong@linux.alibaba.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-08-19 23:56:38 +02:00
Jianqun Xu 28b05a64e4 soc: rockchip: io-domain: add rk3568 support
The io-domain registers on RK3568 SoCs have three separated bits to
enable/disable the 1.8v/2.5v/3.3v power.

This patch make the write to be a operation, allow rk3568 uses a private
register set function.

Since the 2.5v mode hasn't been fully validated yet, the driver only sets
1.8v [enable] + 3.3v [disable] for 1.8v mode
1.8v [disable] + 3.3v [enable] for 3.3v mode

There is not register order requirement which has been cleared by our IC
team.

For future reference the full usage matrix including the 2.5V setting is:
case  V33  V25  V18  result
0     0    0    0    IO safe, but cannot work
1     0    0    1    IO require 1.8V, should < 1.98V, otherwise IO may damage
2     0    1    0    IO require 2.5V, should < 2.75V, otherwise IO may damage
3     0    1    1    Invalid state, should avoid
4     1    0    0    IO require 3.3V, should < 3.63V, otherwise IO may damage
5     1    0    1    IO require 1.8V, should < 1.98V, otherwise IO may damage
6     1    1    0    IO require 2.5V, should < 2.75V, otherwise IO may damage
7     1    1    1    Invalid state, should avoid

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
[added mode clarification from Jay]
Link: https://lore.kernel.org/r/20210805120107.27007-3-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-08-14 08:23:47 +02:00
Geert Uytterhoeven 2a1c55d476 soc: rockchip: ROCKCHIP_GRF should not default to y, unconditionally
Merely enabling CONFIG_COMPILE_TEST should not enable additional code.
To fix this, restrict the automatic enabling of ROCKCHIP_GRF to
ARCH_ROCKCHIP, and ask the user in case of compile-testing.

Fixes: 4c58063d42 ("soc: rockchip: add driver handling grf setup")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210208143855.418374-1-geert+renesas@glider.be
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-07-12 13:29:09 +02:00
Elaine Zhang 1782c87b44 soc: rockchip: power-domain: add rk3568 powerdomains
Add power-domains found on rk3568 socs.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210417112952.8516-16-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-05-11 12:07:04 +02:00
Elaine Zhang 0a69452e03 soc: rockchip: power-domain: Add a meaningful power domain name
Add the power domains names to the power domain info struct so we
have meaningful name for every power domain.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210417112952.8516-10-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-05-10 09:30:12 +02:00
Zhang Changzhong c2867b2e71 soc: rockchip: io-domain: Fix error return code in rockchip_iodomain_probe()
Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.

Fixes: e943c43b32 ("PM: AVS: rockchip-io: Move the driver to the rockchip specific drivers")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhang Changzhong <zhangchangzhong@huawei.com>
Link: https://lore.kernel.org/r/1607070805-33038-1-git-send-email-zhangchangzhong@huawei.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-12-04 11:20:47 +01:00
Lee Jones a6a3a24c12 soc: rockchip: io-domain: Remove incorrect and incomplete comment header
Fixes the following W=1 kernel build warning(s):

 drivers/soc/rockchip/io-domain.c:57: warning: Cannot understand  * @supplies: voltage settings matching the register bits.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: linux-rockchip@lists.infradead.org
Link: https://lore.kernel.org/r/20201103152838.1290217-6-lee.jones@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-12 12:15:06 +01:00
Ulf Hansson e943c43b32 PM: AVS: rockchip-io: Move the driver to the rockchip specific drivers
The avs drivers are all SoC specific drivers that doesn't share any code.
Instead they are located in a directory, mostly to keep similar
functionality together. From a maintenance point of view, it makes better
sense to collect SoC specific drivers like these, into the SoC specific
directories.

Therefore, let's move the rockchip-io driver to the rockchip directory.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-10-16 18:23:15 +02:00
Linus Torvalds 8362fd64f0 ARM: SoC-related driver updates
Various driver updates for platforms and a couple of the small driver
 subsystems we merge through our tree:
 
  - A driver for SCU (system control) on NXP i.MX8QXP
  - Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
  - Qualcomm PM support for MSM8998
  - Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
  - Reset controller support for Bitmain BM1880
  - TI SCI (System Control Interface) support for CPU control on AM654
    processors
  - More TI sysc refactoring and rework
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl0yK3YPHG9sb2ZAbGl4
 b20ubmV0AAoJEIwa5zzehBx3WdUQAJEFRzY4+8VfsUspKmGwzHsrk7t1038JUEDE
 VL3yYlvSGeHg5a58AI5PCR5ZCsyPK7Yw9cAcYexd0frFR7BCwKWrjqem0Lb5ovdK
 CYM517DRtYPSBMF08Xw4pbZlT0yg65F1e9cf6BlUpkUZ6lJn4gUy8Y4BE6Aw/zuF
 QKtQNs6Q8BUZqS3uoOpJ/PY4JiUmLPQPO4Lry7Lud8Z7qgArCC326paC3wwqjLoC
 TpoMqb6izt7Vzo4BtTo5TUCyiEFZDlb/thhDySVlYRE7DQJusHBvRO9qgjI2ahOo
 1/935q1fJO7S6+Yvc8DIzrD/DrIUOvOshi31F/J6iWKkQkTUxtQwsVReZKaiOfSD
 fYxNVCgTcMS6ailKQSMQ0SYgXDa2gWdV3tS9XU8qML3tnDthi1nDmZks0QAAnFPS
 bXRcWGtgqeQJ+QJ7yyKrsD9POeaq3Hc5/f1DN34H//Cyn0ip/fD6fkLCMIfUDwmu
 TmO2Mnj6/fG/iBK+ToF+DaJ0/u3RiV2MC2vCE+0m3cVI9jtq9iA1y3UlmoaKUhhC
 t9znA+u8/Jc5S2zNQriI2Ja5q8nKfihL7Jf68ENvGzLc7YuAqP6yx1LMg1g6Wshc
 nLT+kHOF6DCUC3W7a8VuNyaxCwVtTbNTti+nvQVOmV6eaGiD5vzpXkHBWMbOJ7Lh
 YOBwGyb4
 =ek+j
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC-related driver updates from Olof Johansson:
 "Various driver updates for platforms and a couple of the small driver
  subsystems we merge through our tree:

   - A driver for SCU (system control) on NXP i.MX8QXP

   - Qualcomm Always-on Subsystem messaging driver (AOSS QMP)

   - Qualcomm PM support for MSM8998

   - Support for a newer version of DRAM PHY driver for Broadcom (DPFE)

   - Reset controller support for Bitmain BM1880

   - TI SCI (System Control Interface) support for CPU control on AM654
     processors

   - More TI sysc refactoring and rework"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
  reset: remove redundant null check on pointer dev
  soc: rockchip: work around clang warning
  dt-bindings: reset: imx7: Fix the spelling of 'indices'
  soc: imx: Add i.MX8MN SoC driver support
  soc: aspeed: lpc-ctrl: Fix probe error handling
  soc: qcom: geni: Add support for ACPI
  firmware: ti_sci: Fix gcc unused-but-set-variable warning
  firmware: ti_sci: Use the correct style for SPDX License Identifier
  soc: imx8: Use existing of_root directly
  soc: imx8: Fix potential kernel dump in error path
  firmware/psci: psci_checker: Park kthreads before stopping them
  memory: move jedec_ddr.h from include/memory to drivers/memory/
  memory: move jedec_ddr_data.c from lib/ to drivers/memory/
  MAINTAINERS: Remove myself as qcom maintainer
  soc: aspeed: lpc-ctrl: make parameter optional
  soc: qcom: apr: Don't use reg for domain id
  soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
  memory: tegra: Fix -Wunused-const-variable
  firmware: tegra: Early resume BPMP
  soc/tegra: Select pinctrl for Tegra194
  ...
2019-07-19 17:13:56 -07:00
Arnd Bergmann b27aca2e55 soc: rockchip: work around clang warning
clang emits a warning about a negative shift count for an
unused part of a conditional constant expression:

drivers/soc/rockchip/pm_domains.c:795:21: error: shift count is negative [-Werror,-Wshift-count-negative]
        [RK3328_PD_VIO]         = DOMAIN_RK3328(-1, 8, 8, false),
                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/soc/rockchip/pm_domains.c:129:2: note: expanded from macro 'DOMAIN_RK3328'
        DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup)
        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/soc/rockchip/pm_domains.c:105:33: note: expanded from macro 'DOMAIN_M'
        .status_mask = (status >= 0) ? BIT(status) : 0, \
                                       ^~~~~~~~~~~
include/linux/bits.h:6:24: note: expanded from macro 'BIT'

This is a bug in clang that will be fixed in the future, but in order
to build cleanly with clang-8, it would be helpful to shut up this
warning. This file is the only instance reported by kernelci at the
moment.

The best solution I could come up with is to move the BIT() usage
out of the macro into the instantiation, so we can avoid using
BIT(-1).

Link: https://lore.kernel.org/r/20190703153112.2767411-1-arnd@arndb.de
Link: https://bugs.llvm.org/show_bug.cgi?id=38789
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-07-03 19:20:19 -07:00
Thomas Gleixner d2912cb15b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19 17:09:55 +02:00
Thomas Gleixner ec8f24b7fa treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 10:50:46 +02:00
Douglas Anderson bbdc00a7de soc: rockchip: Set the proper PWM for rk3288
The rk3288 SoC has two PWM implementations available, the "old"
implementation and the "new" one.  You can switch between the two of
them by flipping a bit in the grf.

The "old" implementation is the default at chip power up but isn't the
one that's officially supposed to be used.  ...and, in fact, the
driver that gets selected in Linux using the rk3288 device tree only
supports the "new" implementation.

Long ago I tried to get a switch to the right IP block landed in the
PWM driver (search for "rk3288: Switch to use the proper PWM IP") but
that got rejected.  In the mean time the grf has grown a full-fledged
driver that already sets other random bits like this.  That means we
can now get the fix landed.

For those wondering how things could have possibly worked for the last
4.5 years, folks have mostly been relying on the bootloader to set
this bit.  ...but occasionally folks have pointed back to my old patch
series [1] in downstream kernels.

[1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1391597.html

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11 13:40:32 +02:00
Heiko Stuebner 24869610e8 soc: rockchip: power-domain: add rk3066 powerdomains
Add power-domains found on rk3066 socs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-06 14:13:32 +01:00
Heiko Stuebner a0d5e7d499 soc: rockchip: power-domain: add rk3188 powerdomains
Add power-domains found on rk3188 socs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-05 09:40:03 +01:00
Rob Herring dc37a25252 soc: Convert to using %pOFn instead of device_node.name
In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.

Cc: Li Yang <leoyang.li@nxp.com>
Cc: David Brown <david.brown@linaro.org>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Santosh Shilimkar <ssantosh@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-soc@vger.kernel.org
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Qiang Zhao <qiang.zhao@nxp.com>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
2018-10-04 14:16:01 -05:00
Linus Torvalds 32bcbf8b6d ARM: SoC driver updates
This branch contains platform-related driver updates for ARM and ARM64.
 
 Highlights:
  - ARM SCMI (System Control & Management Interface) driver cleanups
  - Hisilicon support for LPC bus w/ ACPI
  - Reset driver updates for several platforms: Uniphier,
  - Rockchip power domain bindings and hardware descriptions for several SoCs.
  - Tegra memory controller reset improvements
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlsfB94PHG9sb2ZAbGl4
 b20ubmV0AAoJEIwa5zzehBx3k2IP/i9T71QoanZ3k6o/d+YUqmTuUiA+EJWFANry
 8KSjBKmYDON/GLgRCiNZR8P0NZ3d1LgFk5gZDdhMrOtoGtd8k8q0KyqLxjKAWHt6
 opSrGucmE1gy9FvJdUkK+y148vM+Ea4SXRVOZxbLV5qm3inPwnopJjgKAfnhIn4X
 QmkSca90CyEc3kPdBdfMeAKL+7SRb4mbFHAXXVE7QiWvjrEjUkvtNVTazf5Nroc4
 PbI97zSFrmSFO4ZK0jZHCd4R2xhsJwzDQ/UKHC9C9/IdFMLfnJ7dxIf97QYn41Kl
 H46FneMZZZ1FibN+Mj5hC/tByE8FrMtWh636z031s6kkamSqLiBAZFlGpHABxQJs
 3tN1vBP40R7hzm76yQAC4Uopr5xOtmLr6KBMBBRr+Axf9jHMS4m/WP1chwZFpFjI
 Awxc0VCjBUm+haHvK85J4eHrzbWPjG+8aV5Ar5DHVo8et3MzCdX0ycoDeUT787qc
 qzEcCjGPbXHBR1aXUX8stRW5x8zoGH/4IUYMo5IGadiFuXSna6ERG9IHq3fAU5Fp
 ZzNNKedtodn9NoMr3NJJk1ndyrUr0lpXwlVqFeksRTa+INk2FHKd0cQfxwV33kS9
 wHXw+v323uxa3Tz2TXKS7PavY5yr6fZ0dLC2+xEDqHq6bsLxo1DnBEnaola+Jg+u
 9hKEuSff
 =xs+f
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "This contains platform-related driver updates for ARM and ARM64.

  Highlights:

   - ARM SCMI (System Control & Management Interface) driver cleanups

   - Hisilicon support for LPC bus w/ ACPI

   - Reset driver updates for several platforms: Uniphier,

   - Rockchip power domain bindings and hardware descriptions for
     several SoCs.

   - Tegra memory controller reset improvements"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (59 commits)
  ARM: tegra: fix compile-testing PCI host driver
  soc: rockchip: power-domain: add power domain support for px30
  dt-bindings: power: add binding for px30 power domains
  dt-bindings: power: add PX30 SoCs header for power-domain
  soc: rockchip: power-domain: add power domain support for rk3228
  dt-bindings: power: add binding for rk3228 power domains
  dt-bindings: power: add RK3228 SoCs header for power-domain
  soc: rockchip: power-domain: add power domain support for rk3128
  dt-bindings: power: add binding for rk3128 power domains
  dt-bindings: power: add RK3128 SoCs header for power-domain
  soc: rockchip: power-domain: add power domain support for rk3036
  dt-bindings: power: add binding for rk3036 power domains
  dt-bindings: power: add RK3036 SoCs header for power-domain
  dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions
  memory: tegra: Remove Tegra114 SATA and AFI reset definitions
  memory: tegra: Register SMMU after MC driver became ready
  soc: mediatek: remove unneeded semicolon
  soc: mediatek: add a fixed wait for SRAM stable
  soc: mediatek: introduce a CAPS flag for scp_domain_data
  soc: mediatek: reuse regmap_read_poll_timeout helpers
  ...
2018-06-11 18:15:22 -07:00
Linus Torvalds 6419945e33 This time we have a good set of changes to the core framework that do some
general cleanups, but nothing too major. The majority of the diff goes to
 two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for
 Actions Semi so it takes up some lines to add all the different types, and
 the Qualcomm diff is there because we add support for two SoCs and it's quite
 a bit of data.
 
 Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And
 then the long tail of driver updates for various fixes and stuff follows
 after that.
 
 Core:
  - debugfs cleanups removing error checking and an unused provider API
  - Removal of a clk init typedef that isn't used
  - Usage of match_string() to simplify parent string name matching
  - OF clk helpers moved to their own file (linux/of_clk.h)
  - Make clk warnings more readable across kernel versions
 
 New Drivers:
  - Qualcomm SDM845 GCC and Video clk controllers
  - Qualcomm MSM8998 GCC
  - Actions Semi S900 SoC support
  - Nuvoton npcm750 microcontroller clks
  - Amlogic axg AO clock controller
 
 Removed Drivers:
  - Deprecated Rockchip clk-gate driver
 
 Updates:
  - debugfs functions stopped checking return values
  - Support for the MSIOF module clocks on Rensas R-Car M3-N
  - Support for the new Rensas RZ/G1C and R-Car E3 SoCs
  - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs
  - Berlin and Amlogic SPDX tagging
  - Usage of of_clk_get_parent_count() in more places
  - Proper implementation of the CDEV1/2 clocks on Tegra20
  - Allwinner H6 PRCM clock support and R40 EMAC support
  - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet
  - Round closest support for meson's mpll driver
  - Support for meson8b nand clocks and gxbb video decoder clocks
  - Mediatek mali clks
  - STM32MP1 fixes
  - Uniphier LD11/LD20 stream demux system clock
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlsWxugACgkQrQKIl8bk
 lSVs2A/9HOMsWeiYx1MESrXw6N2UknWeqeT/b1v8L/VOiptJg+OTExPbzmSylngv
 AXJAfIkCpguSMh9b310pA3DAzk5docmbQ4zL977yY+KXmOcDooCd34aG5a+tB3ie
 ugC8T2bQLrJdMp3hsqaKZsYzqe7LoW2NJgoliXDMA/QUBLpvHq+fcu2zOawingTA
 GNc3LGqP5Op7p09aPK30gtQNqLK5qGpHASa/AY7Y0PXlUeTZ8rmF06fcEAg5shkC
 CT57Zy2rSFB2RorEJarYXDPLRHMw/jxXtpMVXEy7zuz/3ajvvRiZDHv75+NaBru9
 hDt1rzslzexEN4fYzj4AtGYRKyBrHbDaxG1qdIWPWVyoE0CEb+dZ1gH7/Ski5r+s
 z5D28NogC0T0sey6yWssyG3RLvkPJ5nxUhL++siHm1lbyo16LmhB1+nFvxrlzmBB
 0V1xqEa7feYpD+JD66lJFb5ornHLwGtVYBpeiY+hrDR3ddWEe1IxaYGR2p9nHwSS
 Us/ZQdHIYBVEqoo3+BWnTn+HSQzmd/sqHqWnLlVWUHoomm5nXx18PeS87vFbcPv9
 dMr+FFJ3Elubzcy5UZJPfNw+pb+teE7tYGQkQ3nbLRxT1YZOoIJZJDqNKxM1cgne
 6c/VXJMEyBBn/w7Iru/3eWCZVQJGlmYS47DFDzduFvd3LMfmKIM=
 =KK/v
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This time we have a good set of changes to the core framework that do
  some general cleanups, but nothing too major. The majority of the diff
  goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is
  introduced for Actions Semi so it takes up some lines to add all the
  different types, and the Qualcomm diff is there because we add support
  for two SoCs and it's quite a bit of data.

  Otherwise the big driver updates are on TI Davinci and Amlogic
  platforms. And then the long tail of driver updates for various fixes
  and stuff follows after that.

  Core:
   - debugfs cleanups removing error checking and an unused provider API
   - Removal of a clk init typedef that isn't used
   - Usage of match_string() to simplify parent string name matching
   - OF clk helpers moved to their own file (linux/of_clk.h)
   - Make clk warnings more readable across kernel versions

  New Drivers:
   - Qualcomm SDM845 GCC and Video clk controllers
   - Qualcomm MSM8998 GCC
   - Actions Semi S900 SoC support
   - Nuvoton npcm750 microcontroller clks
   - Amlogic axg AO clock controller

  Removed Drivers:
   - Deprecated Rockchip clk-gate driver

  Updates:
   - debugfs functions stopped checking return values
   - Support for the MSIOF module clocks on Rensas R-Car M3-N
   - Support for the new Rensas RZ/G1C and R-Car E3 SoCs
   - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs
   - Berlin and Amlogic SPDX tagging
   - Usage of of_clk_get_parent_count() in more places
   - Proper implementation of the CDEV1/2 clocks on Tegra20
   - Allwinner H6 PRCM clock support and R40 EMAC support
   - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet
   - Round closest support for meson's mpll driver
   - Support for meson8b nand clocks and gxbb video decoder clocks
   - Mediatek mali clks
   - STM32MP1 fixes
   - Uniphier LD11/LD20 stream demux system clock"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
  clk: qcom: Export clk_fabia_pll_configure()
  clk: bcm: Update and add Stingray clock entries
  dt-bindings: clk: Update Stingray binding doc
  clk-si544: Properly round requested frequency to nearest match
  clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
  clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
  clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
  clk: ingenic: jz4770: Change OTG from custom to standard gated clock
  clk: ingenic: Support specifying "wait for clock stable" delay
  clk: ingenic: Add support for clocks whose gate bit is inverted
  clk: use match_string() helper
  clk: bcm2835: use match_string() helper
  clk: Return void from debug_init op
  clk: remove clk_debugfs_add_file()
  clk: tegra: no need to check return value of debugfs_create functions
  clk: davinci: no need to check return value of debugfs_create functions
  clk: bcm2835: no need to check return value of debugfs_create functions
  clk: no need to check return value of debugfs_create functions
  clk: imx6: add EPIT clock support
  clk: mvebu: use correct bit for 98DX3236 NAND
  ...
2018-06-09 12:06:24 -07:00
Kees Cook 0ed2dd03b9 treewide: Use struct_size() for devm_kmalloc() and friends
Replaces open-coded struct size calculations with struct_size() for
devm_*, f2fs_*, and sock_* allocations. Automatically generated (and
manually adjusted) from the following Coccinelle script:

// Direct reference to struct field.
@@
identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
identifier VAR, ELEMENT;
expression COUNT;
@@

- alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP)
+ alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)

// mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL);
@@
identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
identifier VAR, ELEMENT;
expression COUNT;
@@

- alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP)
+ alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)

// Same pattern, but can't trivially locate the trailing element name,
// or variable name.
@@
identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
expression SOMETHING, COUNT, ELEMENT;
@@

- alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP)
+ alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP)

Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-06 11:15:43 -07:00
Finley Xiao 9bdf401bf4 soc: rockchip: power-domain: add power domain support for px30
This driver is modified to support PX30 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23 20:47:57 +02:00
Elaine Zhang 2dacbd1046 soc: rockchip: power-domain: add power domain support for rk3228
This driver is modified to support RK3228 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23 20:47:57 +02:00
Elaine Zhang 277535f7b6 soc: rockchip: power-domain: add power domain support for rk3128
This driver is modified to support RK3128 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23 20:47:57 +02:00
Caesar Wang 6f686e85ed soc: rockchip: power-domain: add power domain support for rk3036
This driver is modified to support RK3036 SoC.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-23 20:47:57 +02:00
Finley Xiao 9e59c5f66c soc: rockchip: power-domain: Fix wrong value when power up pd with writemask
Solve the pd could only ever turn off but never turn them on again,
if the pd registers have the writemask bits.

So far this affects the rk3328 only.

Fixes: 79bb17ce8e ("soc: rockchip: power-domain: Support domain control in hiword-registers")
Cc: stable@vger.kernel.org
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-05-14 11:53:26 +02:00
Geert Uytterhoeven 54d52ad940 soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding
As of_clk_get_parent_count() returns zero on failure, while
of_count_phandle_with_args() might return a negative error code, this
also fixes the issue of possibly using a negative number in the
allocation below.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-02 08:33:52 -07:00
Jeffy Chen b1271993aa soc: rockchip: power-domain: Add a sanity check on pd->num_clks
The of_count_phandle_with_args() can fail and return error(for example,
rk3399 pd_vio doesn't have clocks). That would break the pd probe.

Add a sanity check on pd->num_clks to avoid that.

Fixes: 65084121d59d ("soc: rockchip: power-domain: use clk_bulk APIs")
Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-05 19:42:29 +01:00
Jeffy Chen d909072d05 soc: rockchip: power-domain: use clk_bulk APIs
Use clk_bulk APIs, and also add error handling for clk enable.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-05 19:42:28 +01:00
Xiao Yao 6e61c891a0 soc: rockchip: disable jtag switching for RK3128 SoCs
Disable IO function switching between sdmmc and jtag
for RK3128 SoCs.

Signed-off-by: Xiao Yao <xiaoyao@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-05 19:42:23 +01:00
Shawn Lin e17ee5f08b soc: rockchip: disable jtag switching for RK3228/RK3229 SoCs
Disable IO function switching between sdmmc and jtag
for RK3228 and RK3229 SoCs.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-02-12 09:39:11 +01:00
Geert Uytterhoeven 89c7aea915 soc: rockchip: power-domain: Use GENPD_FLAG_ACTIVE_WAKEUP
Set the newly introduced GENPD_FLAG_ACTIVE_WAKEUP, which allows to
remove the driver's own flag-based callback.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2017-11-08 01:00:47 +01:00
Elaine Zhang bd85f4b769 soc: rockchip: power-domain: add power domain support for rk3366
This driver is modified to support RK3366 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-20 22:42:19 +02:00
Shawn Lin 887758c325 soc: rockchip: disable jtag switching for RK3328 Soc
Disable IO function switching between sdmmc and jtag
for RK3328 Soc.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16 17:08:12 +02:00
Heiko Stuebner 4c58063d42 soc: rockchip: add driver handling grf setup
The General Register Files are an area of registers containing a lot
of single-bit settings for numerous components as well full components
like usbphy control. Therefore all used components are accessed
via the syscon provided by the grf nodes or from the sub-devices
created through the simple-mfd created from the grf node.

Some settings are not used by anything but will need to be set up
according to expectations on the kernel side.

Best example is the force_jtag setting, which defaults to on and
results in the soc switching the pin-outputs between jtag and sdmmc
automatically depending on the card-detect status. This conflicts
heavily with how the dw_mmc driver expects to do its work and also
with the clock-controller, which has most likely deactivated the
jtag clock due to it being unused.

So far the handling of this setting was living in the mach-rockchip
code for the arm32-based rk3288 but that of course doesn't work
for arm64 socs and would also look ugly for further arm32 socs.

Also always disabling this setting is quite specific to linux and
its subsystems, other operating systems might prefer other settings,
so that the bootloader cannot really set a sane default for all.

So introduce a top-level driver for the grf that handles these
settings that need to be a certain way but nobody cares about.

Other needed settings might surface in the future and can then
be added here, but only as a last option. Ideally general GRF
settings should be handled in the driver needing them.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2017-01-06 10:28:19 +01:00
Elaine Zhang e9284603d8 soc: rockchip: power-domain: add power domain support for rk3328
The rk3328 uses the newly introduced support for power-domain control
in hiword-mask registers.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-05 14:35:09 +01:00
Elaine Zhang 79bb17ce8e soc: rockchip: power-domain: Support domain control in hiword-registers
New Rockchips SoCs may have their power-domain control in registers
using a writemask-based access scheme (upper 16bit being the write
mask). So add a DOMAIN_M type and handle this case accordingly.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-05 14:29:55 +01:00
Tomeu Vizoso dabc0259db soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell
It was a bit surprising that the device was reported to have probed just
fine, but the provider hadn't been registered.

So handle any errors when registering the provider and fail the probe
accordingly.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-11 02:14:59 +01:00
Heiko Stuebner 79d12b7a7f soc: rockchip: power-domain: use pm_genpd_remove in error cleanup
The newly introduced pm_genpd_remove reverts the initialization done
by pm_genpd_init and is necessary in the error path of the rockchip
power-domain driver.

Without it the driver will in the error case cleanup the devm-allocated
structures including the elements referenced in the gpd_list thus making
deactivation of unused domains (and probably later genpd accesses as
well) fail by accessing invalid pointers.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-11 02:14:59 +01:00
Caesar Wang e4c8cd82d5 soc: rockchip: power-domain: avoid infinite loop
In some cases, we have met the infinite loop in
rockchip_pmu_set_idle_request() or rockchip_do_pmu_set_power_domain().

As the crosbug.com/p/57351 reported, the boot hangs right after this
[1.629163] bootconsole [uart8250] disabled
[1.639286] [drm:drm_core_init] Initialized drm 1.1.0 20060810
[1.645926] [drm:drm_get_platform_dev] Initialized vgem 1.0.0 20120112..
[1.654558] iommu: Adding device ff8f0000.vop to group 0
[1.660569] iommu: Adding device ff900000.vop to group 1
<hang>

This patch adds the error message and timeout to avoid infinite loop if
it fails to get the ack.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-02 00:17:59 +01:00
Douglas Anderson 3f2fe461c7 soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts
On rk3288 it was important that powerdown and powerup counts for the
CPU/GPU in the kernel because:
* The power on default was crazy long.
* We couldn't rely on the firmware to set this up because really this
  wasn't the firmware's job--the kernel was the only one that really
  cared about bringing up / down CPUs and the GPU and doing suspend /
  resume (which involves bringing up / down CPUs).

On newer ARM systems (like rk3399) ARM Trusted Firmware is in charge of
bringing up and down the CPUs and it really should be in charge of
setting all these counts right.  After all ATF is in charge of suspend /
resume and CPU up / down.  Let's get out of the way and let ATF do its
job.

A few other motivations for doing this:
* Depending on another configuration (PMU_24M_EN_CFG) these counts can
  be either in 24M or 32k cycles.  Thus, though ATF isn't really so
  involved in bringing up the GPU, ATF should probably manage the counts
  for everything so it can also manage the 24M / 32k choice.
* It turns out that (right now) 24M mode is broken on rk3399 and not
  being used.  That means that the count the kernel was programming
  in (24) was not 1 us (which it seems was intended) but was actually
  .75 ms
* On rk3399 there are actually 2 separate registers for setting CPU
  up/down time plus 1 register for GPU up/down time.  The curent kernel
  code actually was putting the register for the "little" cores in the
  "CPU" slot and the register for the "big" cores in the "GPU" slot.  It
  was never initting the GPU counts.

Note: this change assumes that ATF will actually set these values at
boot, as I'm proposing in <http://crosreview.com/372381>.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
[ATF change has landed]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-16 02:42:29 +02:00
Elaine Zhang 6f27ab3e42 soc: rockchip: support active_wakeup for rockchip power-domains
Register gpd_dev_ops.active_wakeup function to support keep power
during suspend state. And add flag to each power domain to
decide whether keep power during suspend or not.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-19 00:37:20 +02:00
Elaine Zhang 074c6a422d soc: rockchip: power-domain: support qos save and restore
support qos save and restore when power domain on/off.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-21 23:02:16 +02:00
Shawn Lin 4506697d9f soc: rockchip: power-domain: check the existing of regmap
Check return value of syscon_node_to_regmap for
rockchip_pm_domain_probe. If err value is returned, probe
procedure should abort.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-12 03:28:08 +02:00
Elaine Zhang fd8b62cc38 soc: rockchip: power-domain: Modify power domain driver for rk3399
This driver is modified to support RK3399 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[small indentation fixups]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28 13:16:45 +02:00
Elaine Zhang 6be05b5ec1 soc: rockchip: power-domain: add support for sub-power domains
This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences,
which needs to have more than one power domain enabled to be operational.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[restructured error handling in subdomain-addition]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28 12:57:45 +02:00
Elaine Zhang 1fe767a56c soc: rockchip: power-domain: allow domains only handling idle requests
On some Rockchip SoC there exist child-domains only handling their
idle state with the actual power-state handled by a (shared) parent-
domain.

So allow such types of domains. For them, we can determine their
state (on/off) by checking the inverse idle-state instead.

There exist one special case if both idle as well power handling
were set as not present, but as the domain-data is defined in the
code itself, we can expect the reasonable developer to define them
in a correct way, without adding more checks.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28 12:06:43 +02:00
Elaine Zhang 6aa841c809 soc: rockchip: power-domain: make idle handling optional
Not all new socs need to handle idle states on domain state changes,
so add the possibility to make them optional.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-28 12:03:29 +02:00
Shawn Lin 1d961f11a1 soc: rockchip: power-domain: fix err handle while probing
If we fail to probe the driver, we should not directly break
from the for_each_available_child_of_node since it calls of_node_get
while iterating. This patch add of_node_put to fix the unbalanced
call pair.

Fixes: 7c696693a4 ("soc: rockchip: power-domain: Add power domain driver")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-02 22:18:31 +01:00
zhangqing 8c20b67f28 soc: rockchip: power-domain: Modify power domain driver for rk3368
This driver is modified to support RK3368 SoC.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25 15:15:19 +01:00