The socfpga.dtsi explicitly enabled MMC support, but not all boards are
equiped with an MMC card. There are setups which only have QSPI NOR.
Therefore, disable the MMC support on socfpga.dtsi level and enable it
on per-board basis.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alan Tull <atull@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Thor Thayer <tthayer@altera.com>
Cc: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The sorting policy for this file is alphabetically.
Reorder all nodes, that are out of place.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add FPGA manager to device tree for SoCFPGA.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
- Add DTS property "altr,modrst-offset" for reset driver to
use
- Add updated reset defines for the reset driver
- Add reset property for EMACs on Arria10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVyBZjAAoJEBmUBAuBoyj0IWEP/jlmY2g+/lloIRI7Yu49wncy
xOnFX5+1N6NoKaPvSiNO9w2i4QMMw9nCs/+UccQqbjiOS2ggFuU12ODxSw91PadI
FbDuMgsjXzeCcUK4p9sv+S3YK0FnajLuuB4EI9UhCn1nOnGi8Qs6QKKLnwwCvF+X
1JB5cWcEz48SRl9p1K7ZmxvBJIjrhghl16sIBfNPWNzin+yjDBCvf2qtLJyzMz+z
bG+Q3aztrr0vtt7EgEUNaeEZHmseuKtFVLFzL+d4L/HtpnczcNNmbhZDjZZuZjmc
1jLMHZO7/W28njkmU4rYlQPeA4skKn1/a0BQ6S/UEC/RBNsFgkRGBgfsloslofuO
kSaTW02g1ekxRPnZZNU+iqFZ3zHTbq609aCF/x48vbl5Ti6xB+RH5g7XGJSxFeRC
4aEIMaLxyrCTkqN2bh6I4ABLAJnzD4+IcofnLioLiDJOlo0BqEI0mh9KMBHDBoKM
uvltqwaVuWdMxzJue7SITAobsThkp3IS7ZU05JqKM/y1Qpu7DofplYTSQVN/oaWP
3XS8M+ZMgAz9o8E67hv/54NX3PM8zw1fbBW1brCKeXdFqGhcww75aLlcfwBTLVaU
hYDBRMMj2YkRCGjc2mFqlPozy4ovuqQ2ILKAh6/cqWiww1dV0hIw7mP50On7sLU8
Ip/H2H5Q5OCk1but68iq
=dKt6
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v4.3, take 2
- Add DTS property "altr,modrst-offset" for reset driver to
use
- Add updated reset defines for the reset driver
- Add reset property for EMACs on Arria10
* tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: socfpga: dts: Add resets for EMACs on Arria10
ARM: socfpga: dts: add "altr,modrst-offset" property
dt-bindings: Add reset manager offsets for Arria10
Signed-off-by: Olof Johansson <olof@lixom.net>
The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The gates for the clocks coming out of the sdram pll
were missing. The change adds the missing nodes to
the device tree.
Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The l3_sp_clk's parent should be the l3_mp_clk. This will account for
the extra divider that is present for the l3_mp_clk.
The dbg_clk's parent should be the dbg_at_clk. This will account for
the extra divider that is present for the dbg_at_clk.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Just in case the firmware did not enable data and instruction prefetch in
the L2 cache controller, we enable it in the kernel.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
- Add a DTS node for the A9 SCU
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVU1L4AAoJEBmUBAuBoyj05zEP/02UJVcqCHT2P/z/1XJnIwed
hZgO0Oej4ZEc+futAIx6IeMEkgNoIDZX1rdijiQe3Uv2QK8niC7R8yOjwcZrM8jZ
ws/jyKWpCBsV0J+lzZevxa3DpxMHPmcx0W9gAqYpikrwgbXt0Dyy62CQkp+XKZ5d
mluxSEbkSlORddzD8eQbM1yuVlFGg9RAzdwaeZk4j6x+vq2Zk+jEwq5EKLBIiO/U
kGwu/mEryiWl+lzqV7Nlagt4uLASsT5ZxEjr4zUx9ddDTJo4mqStqONdDPMTdf9h
0qzHrWa9mMhI7RLoOWBuvTEcvEVPSRNhVfo6cY8ZnQcZ/V5tj4sG3jAPUFXkFSMd
iZW3mud5P45ugbKiumR5R7ve3t6yxhvNqWH9FZqfnlPPNXtCaUqBGB772A0Xr2Hz
mRPu2Vl9cjmGdrWQHqF5sViPdm52E8Het3/HO0ccsx4aoH+jhgGKeqmiK779EKTA
lA0NPBrL5PRzjNacNwnR7RxtLpcISf5CbsV0ojiIDtB8x11TCg1Zct+ogeE03luT
YpTNuOgTEg7Gy4oa6LPPXahUS+6RffHmASjlt15xaWx/x5MaCXTyk3H4JtSumDiL
blFzdQmNUcO2YpggSgyS0UzRFyqYJIRPq7lHKMJz5NMfaHVzu4VzoDKmJVo4zG2T
BftEOP7ROh5wq1HkWJs3
=23ne
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
Merge "SoCFPGA update for v4.2 part 2" from Dinh Nguyen:
- Add a DTS node for the A9 SCU
* tag 'socfpga_dts_for_v4.2_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: socfpga: dts: add the a9-scu node
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The CIU(Card Interface Unit) get its clock from the sdmmc_clk_divided clock
which is used to clock the card. The sdmmc_clk_divided clock is the sdmmc_clk
passed through a fixed divider of 4. This patch adds the sdmmc_clk_divided
node and makes the sdmmc_clk it's parent.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: renamed ciu_clk to sdmmc_clk_divided
The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1
Trying to use the master without this change results in the kernel boot
process waiting forever for an interrupt that will never occur while
attempting to probe any slave devices configured in the device tree as being
under SPI master 1.
The change works for the Cyclone V, and according to the Arria 5 handbook
should be good there too.
Signed-off-by: Mark James <maj@jamers.net>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
socfpga.dtsi is missing the DMA channels for the uart nodes.
This will produce the following errors:
of_dma_request_slave_channel: dma-names property of node '/soc/serial0@ffc02000' missing or empty
ttyS0 - failed to request DMA
Provide the correct DMA channels to fix this.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
- Add DTS support for a new chip in the SOCFPGA family, the Arria 10.
- Enable watchdog node.
- Add SPI nodes.
- Add the OCRAM node.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJUbslHAAoJEBmUBAuBoyj0R0EP/2nF0rHzM7s9TivfLLnknwu5
UCPFkuB9DFsfBn6XauAjuioY2/K1yugU5Xh4IyKgXfOdUYDRxT18FzltJl8Tk25h
yx7tm5DlukQ68sdKgcSNMXgH1VNR0zV0k0P1PBjdB2W78DGpQTi5KUDb29a6wk7a
g7pYnhrzlKgLVfAazhxsD/N2o+ImxFvsVpdQBxi4/oR5zgYEoLbv6i4CKzPBrPv9
T/v4MP9E9p8tviSpuj99plMZN8w4uBQ7Clc1xCrh8y+KvKRjViFnUZPXFZHnPENs
XnqPuDyHvMxYEKQgrSDO5GQ4USUFM+TTSKGSobkCYYmaw53F+g6FxYTCDkubyCW/
v9OAH5t3lQf3P8SyHdZ2hhGH4EAoTzxC7uYJes/JdjxZgBHpfZv/bj3MGMI6r+w8
5rUF8ueipQjVOVJtr2YkkGM9U0CFw1dBGFBGk3eMrXPV418fcrIJZkRoDwdnvpQj
I8sG1rEoZHAbPOu2ejyxVAlvHF5uy7HAXpt3ktekJV70DtcNTUpREbMso7fksEzL
xufDmwe/BjUzJBFsVhZZLULUlHt1rZLYHXOn/NdfBEWluT4+uhc+1DcsCsc99Bhe
AIUMX+ngDpWZazxRGhzlOxdzi9dhuN1pFtJlXuj2wBhVNdivac4OjgBgFYWu9lpZ
cC/byWHasY2Kyyi1+tDd
=sh1R
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_updates_for_v3.19' of git://git.rocketboards.org/linux-socfpga-next into next/dt
Pull "SoCFPGA DTS updates for v3.19" from Dinh Nguyen:
- Add DTS support for a new chip in the SOCFPGA family, the Arria 10.
- Enable watchdog node.
- Add SPI nodes.
- Add the OCRAM node.
* tag 'socfpga_dts_updates_for_v3.19' of git://git.rocketboards.org/linux-socfpga-next:
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
arm: dts: socfpga: enable watchdog for socfpga platform
arm: dts: socfpga: Add SPI nodes to SOCFPGA DT.
arm: dts: socfpga: Add OCRAM node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since the Synopsys GPIO IP can support multiple ports of varying widths, it
would make more sense to have the GPIO node DTS entry as this:
gpio0: gpio@ff708000{
porta{
};
};
Also, this is documented in the snps-dwapb-gpio.txt.
Suggested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]
[1] https://lkml.org/lkml/2014/7/30/514
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
[dinguyen] cleaned-up commit header and remove version history.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new platforms,
but there's also a bit of cleanup and code removal for things that
are moved from platform code to DT contents (some OMAP clock code in
particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no particular
order:
* Rockchip RK3288 SoC support, including DTS for a dev board that they
have seeded with some community developers.
* Better support for Hardkernel Exynos4-based ODROID boards.
* CCF conversions (and dtsi contents) for several Renesas platforms.
* Gumstix Pepper (TI AM335x) board support
* TI eval board support for AM437x
* Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an Ippo
tablet with the chipset.
* Allwinner A31 Hummingbird board support, not to be confused with the
SolidRun i.MX-based Hummingboard.
* Tegra30 Apalis board support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJT5DqvAAoJEIwa5zzehBx3tm0QAJk8zFyZuMhUPz6SoZTtO9ti
zojZ2218oqLRDfLSYdJx/3QE7gb2ef0e2S6FrthecdAY8sqZzDddL7M/cCf1WSgy
+D4dD1UEq+W/hOeEwIWyo3GR/71exgo/LMTIw8HOJh5c9fanQ2wNChNetCgh8b4u
sVOEMmP1UTO2W7mH9cCRhWXFifBNi0yNl1QBYnLPzM2CbSEa4qQRarTn/94NSEiY
U9XgzysklvYEW/30wcEkz8ZonKbJrtP+zEjODU4wN/muhHECeTehDrkJq0WEK/3C
3ptko2xQGURNaLM6HVvQS9qkXxyhCeZxqkELpjkjjM+YPFN8wdHu7gDctGZlDr39
LQ2pZF6K8vaFvxp3UM2wzdDeoNi3rxguzpFoBmfRP5NWguDrOvjT3w8W4hO9q04J
8SqMGca0av9myHmeSjtRRg5rmcC3kBbOgSN6siVJ8W80rHT7tnFjl6eCawDreQzn
szFzGaOOUnf/kJ/00vzm1dCuluowFPdSYgW3aamZhfkqu2qYJ8Ztuooz5eZGKtex
zlUfKtpL26gnamoUT42K7E8J968AjHjUc/zimwYzIgHCzTTApYGJQcbD/Y28b8QH
gTvhRxP+0kFb+NNq4IHStVMvJrFOPvzOHXcL8x07HqTxrl7W4XoW+KJxCJOk433W
5NJ9s4tEmiTRMtFL1kv6
=xxlY
-----END PGP SIGNATURE-----
Merge tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree changes from Olof Johansson:
"Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new
platforms, but there's also a bit of cleanup and code removal for
things that are moved from platform code to DT contents (some OMAP
clock code in particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no
particular order:
- Rockchip RK3288 SoC support, including DTS for a dev board that
they have seeded with some community developers.
- Better support for Hardkernel Exynos4-based ODROID boards.
- CCF conversions (and dtsi contents) for several Renesas platforms.
- Gumstix Pepper (TI AM335x) board support
- TI eval board support for AM437x
- Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an
Ippo tablet with the chipset.
- Allwinner A31 Hummingbird board support, not to be confused with
the SolidRun i.MX-based Hummingboard.
- Tegra30 Apalis board support"
* tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits)
ARM: dts: Enable USB host0 (EHCI) on rk3288-evb
ARM: dts: add rk3288 ehci usb devices
ARM: dts: Turn on USB host vbus on rk3288-evb
ARM: tegra: apalis t30: fix device tree compatible node
ARM: tegra: paz00: Fix some indentation inconsistencies
ARM: zynq: DT: Clarify Xilinx Zynq platform
ARM: dts: rockchip: add watchdog node
ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
ARM: dts: Add missing pinctrl for uart0/1 for exynos3250
ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250
ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only
ARM: dts: max77686 is exynos5250-snow only
ARM: zynq: DT: Remove DMA from board DTs
ARM: zynq: DT: Add CAN node
ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table
ARM: dts: Add PMU DT node for exynos5260 SoC
ARM: EXYNOS: Add support for Exynos5410 PMU
ARM: dts: Add PMU to exynos5410
...
This patch adds socfpga Ethernet filter attributes for multicast
and unicast filters per Synopsys Ethernet IP configuration chosen
by Altera for the Cyclone 5 and Arria SOC FPGAs.
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
add #reset-cells to socfpga.dtsi. This was missing from the
latest updates and caused the socfpga reset controller to fail
to load like so:
ffd05000.rstmgr: /soc/rstmgr@ffd05000 missing #reset-cells property
probe of ffd05000.rstmgr failed with error -22
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The SoCFPGA has two watchdog timers. Add them to the dtsi.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
[dinh: modified patch to have correct irq flag]
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The cycloneV has three gpio controllers, each one with 29 gpios. This patch
adds the three controller with the gpio driver which is now sitting the
gpio tree.
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull <atull@altera.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.
Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Add the necessary #reset-cells property to the rst-mgr node and
provide a header-file with all possible resets specified.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The timers and uart can get their clock frequencies using the common clock
driver.
Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Convert all socfpga DT files to the dtc preprocessor include syntax.
This allows to include header files in the devicetrees like other
SoC-types already do.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Add both can controllers to the dtsi.
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
The first interrupt is not at 180 but 104. Fix it.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Mostly clock driver updates, more Device Tree support in the form of
common functions useful across platforms and a handful of features and
fixes to the framework core.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTPKLWAAoJEDqPOy9afJhJTJUP/32NJ6+g2/Ren3LNW2QFUAzj
XAJ1PiuciuMFBI1ttErBwgpgtETj1qLQKakipNxoVQk0hN4Ymi6Dz23+7Vif0241
8uDgvMg70eeZlyUk2cc0huJzta2kCWQB7jOZT0oDTlzXA8lq3OiSJrc5ey/leVwW
SM3NySvbN+t/bOaHW5z7oFtsqANCS/t3P0+cL9I+EgUtCJ4boqqI/a01dgZt4qp3
C68ar1Iy5ko6cFNzsjhmHBw1rz3ChQQhCdKDQsIgTbsgMXlI7AHD8CKizB9dxLpI
dmM4HFprHlwKdNSsCwMltXT4ROhV6to1Jlo64dekvYbJzGsqR4OoRTUzUC549kOW
OijFk7QDWMkCBvKA6pmCMpa3GuxRCnU8P8EtmiTra7tz6wwSFESKKEywG6r17/eO
9TU+apzknHYN//Mfx1ODfHGpXxqgZaJCAR8YGZ/sKFAQZSbJqxl7czqr26BmXDgJ
FQxlxgYHGn2PnKr8aI8F35PZWZf2dOKDYImwdslmQXc122I8+qnHsruxLKdGxzQR
VH33ezMP/IhTjcTLwDSmK9JleX5SxxmULRM5kFM+cDh3KJDpw0h/GZXo8XKFSyN4
8qxh5V+QmROzZ8cFFFa/QVXfNHxkAgVSofP/YovkYYMpVt0o7SBMpEXDrfePrmBD
OdoXQ0ETAaitehRph1Aj
=zk74
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework changes from Mike Turquette:
"The clock framework changes for 3.15 look similar to past pull
requests. Mostly clock driver updates, more Device Tree support in
the form of common functions useful across platforms and a handful of
features and fixes to the framework core"
* tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
clk: shmobile: fix setting paretn clock rate
clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
clk: Fix minor errors in of_clk_init() function comments
clk: reverse default clk provider initialization order in of_clk_init()
clk: sirf: update copyright years to 2014
clk: mmp: try to use closer one when do round rate
clk: mmp: fix the wrong calculation formula
clk: mmp: fix wrong mask when calculate denominator
clk: st: Adds quadfs clock binding
clk: st: Adds clockgen-vcc and clockgen-mux clock binding
clk: st: Adds clockgen clock binding
clk: st: Adds divmux and prediv clock binding
clk: st: Support for A9 MUX clocks
clk: st: Support for ClockGenA9/DDR/GPU
clk: st: Support for QUADFS inside ClockGenB/C/D/E/F
clk: st: Support for VCC-mux and MUX clocks
clk: st: Support for PLLs inside ClockGenA(s)
clk: st: Support for DIVMUX and PreDiv Clocks
clk: support hardware-specific debugfs entries
clk: s2mps11: Use of_get_child_by_name
...
These changes are mostly for ARM specific device drivers that either
don't have an upstream maintainer, or that had the maintainer ask
us to pick up the changes to avoid conflicts. A large chunk of this
are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from
that, reset controllers for STi as well as a large rework of the
Marvell Orion/EBU watchdog driver are notable.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAUz/1+GCrR//JCVInAQJmfg/9GyqHatDjjUPUBjUQRIEtKgGdmQwdbDqF
x+OrS/q5B5zYbpIWkbkt1IUYJfU+89Z5ev9jxI4rV824Nu9Y92mHPDnv+N/ptkIh
q2OVP3bQDpWs3aEVV2B1HBNcWrNUuwco9BJu05eegEePii/cto0/wKwWIgUmrmjy
xOLthsnp2YmeplGs7ctC6Dz8XbmELebpawejTGylARXei/SwmzB/YYDgJbYjRL2I
WSCVa8Vo+MZaGC/yxdKVTtvsKVQenxGoMO3ojikJeRdvuVRJds48Cw+UBdzWYNeJ
3Ssvbdx6Xltf9jy/7H0btOUgxPetZuUV+2XpbWfGu0Zr9FcGDv3q9hrxA+UYKnkY
GIGU0otSsmpHnX5Ms3E2xnHiV/fihxA3qohqts5kYRBDr5uc+IpW6SbDymQliCGG
OO4XmIVM3pmsqAqP3Zuseemt9CeSW2yC0XlfXkzjO74yY39c+WLBbtGI40Z5W6i0
mM1C8RD3QSNijYCEC8eqz06BQfRImsPs+jllsnJTZaHfbOsib718uvandjfG26lN
616YMcqq0Sp51HIQ4qW7f2dQr7vOyNqbukdkrwF5JgkY/nVki5kdciRg/yeipRy6
Ey80a+OTq0GQljM0F2dcH/A1eHH9KsuI1L6NdSMJsl0h6guIBORPTwTw3qJ13OkR
wpJyM+Gm+Fk=
=u/FI
-----END PGP SIGNATURE-----
Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Arnd Bergmann:
"These changes are mostly for ARM specific device drivers that either
don't have an upstream maintainer, or that had the maintainer ask us
to pick up the changes to avoid conflicts.
A large chunk of this are clock drivers (bcm281xx, exynos, versatile,
shmobile), aside from that, reset controllers for STi as well as a
large rework of the Marvell Orion/EBU watchdog driver are notable"
* tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
Revert "net: stmmac: Add SOCFPGA glue driver"
ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks
ARM: STi: Add reset controller support to mach-sti Kconfig
drivers: reset: stih416: add softreset controller
drivers: reset: stih415: add softreset controller
drivers: reset: Reset controller driver for STiH416
drivers: reset: Reset controller driver for STiH415
drivers: reset: STi SoC system configuration reset controller support
dts: socfpga: Add sysmgr node so the gmac can use to reference
dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
reset: Add optional resets and stubs
ARM: shmobile: r7s72100: fix bus clock calculation
Power: Reset: Generalize qnap-poweroff to work on Synology devices.
dts: socfpga: Update clock entry to support multiple parents
ARM: socfpga: Update socfpga_defconfig
dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
net: stmmac: Add SOCFPGA glue driver
watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
drivers: cci: Export CCI PMU revision
...
This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This reverts commit 7e0b4cd062.
The binding changes need to be done differently as well, let's
take them through netdev, and merge the dts changes in a new
patch here.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
commit[7e0b4cd dts: socfpga: Add DTS entry for adding the stmmac glue
layer for stmmac.] references the sysmgr through its phandle. This patch
adds the appropriate sysmgr node for the gmac to use.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.
Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.
Finally, fix an indentation error for the sysmgr node.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Chris Ball <chris@printf.net>
The periph_pll and sdram_pll can have multiple parents. Update the device tree
to list all the possible parents for the PLLs. Add an entry for the the
f2s_sdram_ref_clk, which is a possible parent for the sdram_pll.
Also remove the clock-frequency entry in the f2s_periph_ref_clk, as this
property should be placed in dts file.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: David S. Miller <davem@davemloft.net>
---
v3: Remove stray empty line at end of socfpga_cyclone5_socdk.dts
v2: Use the dwmac-sti as an example for a glue layer and split patch up
to have dts as a separate patch. Also cc dts maintainers since there is
a new binding.
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
prepare function to the gate clk that will toggle clock phase setting.
Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
loaded after the clock driver.
v2: Use the syscon driver
The pl330 dmac won't be added to the list of amba devices, as it doesn't have
a clock entry.
Add the clock.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Some of the clocks that were designated gate-clk do not have a gate, so
change those clocks to be of periph-clk type.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Marek Vasut