ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2.
But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result.
Timekeeping core misbehaves. For example, execution of command
"sleep 5" will take 10 sec instead of 5.
Hence, fix it by adding mpu_periphclk ("fixed-factor-clock") and use
it for clocking ARM TWD and Global timer (same way as on OMAP4).
Cc: Tony Lindgren <tony@atomide.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Fixes:commit 8cbd4c2f6a ("arm: boot: dts: am4372: add ARM timers and SCU nodes")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We were expecting to sit on this branch through most of the merge window since
the contents was merged into our tree late, but we ended up sitting on all of
our contents so it can go in with the rest.
The contents here is:
- A large branch of cleanups of the CM/PRM blocks on OMAP.
- A couple of patches plumbing up CM/PRM on OMAP5 and DRA7.
- A branch with DT updates for Freescale i.MX. including some shuffling from
.dts to .dtsi (include) files that causes a little churn.
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Olof Johansson:
"We were expecting to sit on this branch through most of the merge
window since the contents was merged into our tree late, but we ended
up sitting on all of our contents so it can go in with the rest.
The contents here is:
- a large branch of cleanups of the CM/PRM blocks on OMAP.
- a couple of patches plumbing up CM/PRM on OMAP5 and DRA7.
- a branch with DT updates for Freescale i.MX. including some
shuffling from .dts to .dtsi (include) files that causes a little
churn"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits)
ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON
ARM: OMAP4+: control: add support for initializing control module via DT
ARM: dts: dra7: add minimal l4 bus layout with control module support
ARM: dts: omap5: add minimal l4 bus layout with control module support
ARM: OMAP4+: control: remove support for legacy pad read/write
ARM: OMAP4: display: convert display to use syscon for dsi muxing
ARM: dts: omap4: add minimal l4 bus layout with control module support
ARM: dts: am4372: add minimal l4 bus layout with control module support
ARM: dts: am43xx-epos-evm: fix pinmux node layout
ARM: dts: am33xx: add minimal l4 bus layout with control module support
ARM: dts: omap3: add minimal l4 bus layout with control module support
ARM: dts: omap24xx: add minimal l4 bus layout with control module support
ARM: OMAP2+: control: add syscon support for register accesses
ARM: OMAP2+: id: cache omap_type value
ARM: OMAP2+: control: remove API for getting control module base address
ARM: OMAP2+: clock: add low-level support for regmap
ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
ARM: OMAP2+: CM: move SoC specific init calls within a generic API
ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
...
This patch creates an l4_wkup interconnect for AM43xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM nodea as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ehrpwm tbclk is wrongly modelled as deriving from dpll_per_m2_ck.
The TRM says tbclk is derived from SYSCLKOUT. SYSCLKOUT nothing but the
functional clock of pwmss (l4ls_gclk).
Fix this by changing source of ehrpwmx_tbclk to l4ls_gclk.
Fixes: 4da1c67719 ("add tbclk data for ehrpwm")
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently oscillator frequency is determined based on sysboot settings,
it may not be the case always. To determine it properly, efuse settings
also has to be read. CONTROL_STATUS register holds this information.
Bit 31: if 0, frequency to be determined based on sysboot
if 1, frequency to be determined based on efuse
Bit 29,30 - for efuse detection of frequency
Bit 22,23 - for sysboot detection of frequency
Add clock nodes (mux) to determine oscillator frequency as above.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
We need set-rate-parent flags for the display's clock path so that the
DSS driver can change the clock rate of the PLL.
This patchs adds the ti,set-rate-parent flag to disp_clk and
dpll_disp_m2_ck clock nodes.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
We need "tbclk" clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Use the ti,fixed-factor-clock version so that autoidle for
dpll_per_clkdcoldo is properly controlled after power management code
is introduced. Without this the clock may be held active even when
it is gated.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add USB and USB PHY reference clock data
Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
[tony@atomide.com: tabified]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Grygorii Strashko