Commit Graph

9 Commits

Author SHA1 Message Date
Thomas Gleixner 1802d0beec treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:41 -07:00
Seiya Wang 64f4466c88 clk: mediatek: correct cpu clock name for MT8173 SoC
Correct cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72.

Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-26 10:17:40 -08:00
Sean Wang 567bf2ed86 clk: mediatek: export cpu multiplexer clock for MT8173 SoCs
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:44 -07:00
Philipp Zabel 4585945bf1 clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06 17:47:40 +02:00
James Liao cdb2bab78a clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01 12:06:00 +08:00
James Liao 29859d9315 clk: mediatek: Add subsystem clocks of MT8173
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01 12:04:50 +08:00
James Liao 829f4912d1 clk: mediatek: Removed unused dpi_ck clock from MT8173
The dpi_ck clock can be removed because it not actually used
in topckgen and subsystems.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01 12:04:48 +08:00
Joe.C 2d61fe0fc7 clk: mediatek: add 13mhz clock for MT8173
Add 13mhz clock used by GPT timer in infracfg.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2015-10-01 12:04:34 +08:00
James Liao c1e81a3bef clk: mediatek: Add basic clocks for Mediatek MT8173.
This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs,
INFRA and PERI clocks.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05 22:50:38 -07:00