Commit Graph

6 Commits

Author SHA1 Message Date
Maxime Ripard 2d7945100b ARM: sunxi: Add the Allwinner A31 compatible to the machine definition
The Allwinner A31 is a quad-Cortex-A7 based SoC, which shares a lot of
IPs with the previous SoCs from Allwinner, like the PIO, I2C, UARTs,
timers, watchdog IPs, but also differs by dropping the WEMAC ethernet
controller and most notably dropping the in-house IRQ controller in
favor of a ARM GIC one.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-16 23:19:24 +02:00
Maxime Ripard 19a280a61b ARM: sunxi: select ARCH_REQUIRE_GPIOLIB
CONFIG_ARCH_SUNXI currently doesn't enable a gpiolib, which causes build
problems when building a kernel with only the sunxi platform enabled.
Select ARCH_REQUIRE_GPIOLIB to solve this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
2013-05-15 09:42:47 +02:00
Maxime Ripard 119fd635e3 clocksource: sunxi: Rename sunxi to sun4i
During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.

It was ok at the time of the support of only the A10 and A13 that
looks pretty much the same, but it's beginning to be troublesome with
the future addition of the Allwinner A31 (sun6i) that is quite
different, and would introduce some weird logic, where sunxi would
actually mean in some case sun4i and sun5i but without sun6i...

Moreover, it makes the compatible strings naming scheme not consistent
with other architectures, where usually for this kind of compability, we
just use the oldest SoC name that has this IP, so let's do just this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-08 21:42:11 +02:00
Maxime Ripard ea71d9a600 clocksource: sunxi: make use of CLKSRC_OF
Using CLKSRC_OF allows to remove the SoC specific sunxi_timer.h header,
and instead of using a custom init function in the machine definition
use the standard clocksource_of_init function.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-08 21:41:54 +02:00
Maxime Ripard 0e37f88d9a ARM: sunxi: Add pinctrl driver for Allwinner SoCs
The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.

This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.

This driver only implements the pinctrl part, the gpio part will come
eventually.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22 13:51:15 +01:00
Maxime Ripard 3b52634f0b ARM: sunxi: Add basic support for Allwinner A1x SoCs
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Stefan Roese <sr@denx.de>
2012-11-16 21:56:51 +01:00