Commit Graph

5 Commits

Author SHA1 Message Date
Thomas Gleixner 1d0ea0692a treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 332
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  publishhed by the free software foundation

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 48 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190530000436.292339952@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:37:06 +02:00
John Garry d2a1606c29 arm64: dts: hisi: Enable Hisi LPC node for hip07
The patch enables the HiSi LPC node for hip07, with
the IPMI child device.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-05-15 14:52:51 +01:00
Zhou Wang 9f5ce88de8 arm64: dts: hisi: add PCIe host controller node for hip07 SoC
Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in
D05 board.

Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-08-14 15:25:39 +01:00
Wei Xu 519caba7a9 arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
Enable the NIC and SAS nodes for the hip07-d05 board
to support related functions.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-10 23:32:56 +08:00
Kefeng Wang 4f357f94e1 arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.

Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-11-15 10:36:17 +00:00