Commit Graph

5 Commits

Author SHA1 Message Date
Yendapally Reddy Dhananjaya Reddy 8dbcad020f ARM: dts: nsp: Add sata device tree entry
Add sata support to the Northstar Plus SoC device tree.

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2016-06-16 16:24:55 -04:00
Yendapally Reddy Dhananjaya Reddy ea2d8975e3 ARM: dts: enable pinctrl for Broadcom NSP
This enables the pinctrl support for Broadcom NSP SoC

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-12-06 19:45:19 -08:00
Jon Mason 41254754aa ARM: dts: NSP: Add NAND Support to DT
Add NAND support to the device tree for the Broadcom Northstar Plus SoC.
Since no driver changes are needed to enable this hardware, only the
device tree changes are required to make this functional.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-11-16 10:48:54 -08:00
Jon Mason 1dbcfb228b ARM: dts: NSP: Add PCI support
Add PCI support to the Northstar Plus SoC.  This uses the existing
pcie-iproc driver.  So, all that is needed is device tree entries in the
DTS.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-11-16 10:48:53 -08:00
Jon Mason 7b2e987de2 ARM: NSP: add minimal Northstar Plus device tree
Add a very minimalistic set of Northstar Plus Device Tree files which
describes the SoC and the BCM958625 implementation.  The perpherials
described are:

ARM Cortex A9 CPU
2 8250 UARTs
ARM GIC
PL310 L2 Cache
ARM A9 Global timer

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-09-14 15:48:02 -07:00