Commit Graph

982049 Commits

Author SHA1 Message Date
Konrad Dybcio 53364cfcaa arm64: dts: qcom: msm8992/4: Rename vreg_vph_pwr to vph_pwr
Rename the fixed regulator to follow the common naming scheme

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210118162432.107275-4-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25 12:45:13 -06:00
Konrad Dybcio 31d9dbd2ae arm64: dts: qcom: msm8992-libra: Update regulator config
* Add PMI8994 RPM regulators
* Add missing PM8994 LVSes
* Add comments concerning "missing" regulators

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210118162432.107275-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25 12:45:12 -06:00
Konrad Dybcio 1628dfe5f6 arm64: dts: qcom: msm8992-bullhead: Update regulator config
* Include pm(i)8994 dtsi
* Add PMI8994 RPM regulators
* Add comments concerning "missing" regulators

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210118162432.107275-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25 12:45:12 -06:00
Konrad Dybcio 72b312411d arm64: dts: qcom: Add support for remaining Sony Kitakami boards
This patch adds support for the following Xperias:

* Z3+ [aka Z4 in some regions] (Ivy)
* Z4 Tablet (Karin)
* Z4 Tablet Wi-Fi (Karin_windy) [APQ8094]
* Z5 Compact (Suzuran)
* Z5 Premium (Satsuki)

These devices are very similar in terms of hardware, with main
differences being display panels.

While at it, update comments describing hardware used:
SMB charger seems to not be used after all, PMI8994 charger
is in use instead.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210118162432.107275-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25 12:45:11 -06:00
Konrad Dybcio 0f7273c3da arm64: dts: qcom: msm8992/4: Add RPM Power Domains
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210118161943.105733-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25 12:38:11 -06:00
Manivannan Sadhasivam 3a786086c6 arm64: dts: qcom: Add missing "-thermal" suffix for thermal zones
The thermal devicetree binding requires the "-thermal" suffix for all
thermal zones. Hence, add the missing suffix for PMIC based thermal
zones.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210118051005.55958-8-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-22 13:47:59 -06:00
Eric Biggers e49c2912db arm64: dts: qcom: sdm630: add ICE registers and clocks
Add the registers and clock for the Inline Crypto Engine (ICE) to the
device tree node for the sdhci-msm host controller on sdm630.  This
allows sdhci-msm to support inline encryption on sdm630.

Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20210121090140.326380-9-ebiggers@kernel.org
[bjorn: Changed indentation]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-21 11:11:00 -06:00
Dmitry Baryshkov 687cc021d7 arm64: dts: qrb5165-rb5: port thermal zone definitions
Add thermal zones definitions basing on the downstream kernel.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210119054848.592329-6-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-21 11:08:26 -06:00
Dmitry Baryshkov 681db16a5b arm64: dts: sm8250-mtp: add thermal zones using pmic's adc-tm5
Port thermal zones definitions from msm-4.19 tree. Enable and add
channel configuration to PMIC's ADC-TM definitions. Declare thermal
zones and respective trip points.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210119054848.592329-5-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-21 09:41:40 -06:00
Dmitry Baryshkov 28a7eb65d4 arm64: dts: qcom: pm8150x: add definitions for adc-tm5 part
Define adc-tm5 thermal monitoring part. Individual channes and thermal
zones are to be configured in per-device dts files.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210119054848.592329-4-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-21 09:41:36 -06:00
AngeloGioacchino Del Regno 6243905da7 arm64: dts: pmi8998: Add the right interrupts for LAB/IBB SCP and OCP
In commit 208921bae6 ("arm64: dts: qcom: pmi8998: Add nodes for
LAB and IBB regulators") bindings for the lab/ibb regulators were
added to the pmi8998 dt, but the original committer has never
specified what the interrupts were for.
LAB and IBB regulators provide two interrupts, SC-ERR (short
circuit error) and VREG-OK but, in that commit, the regulators
were provided with two different types of interrupts;
specifically, IBB had the SC-ERR interrupt, while LAB had the
VREG-OK one, none of which were (luckily) used, since the driver
didn't actually use these at all.
Assuming that the original intention was to have the SC IRQ in
both LAB and IBB, as per the names appearing in documentation,
fix the SCP interrupt.

While at it, also add the OCP interrupt in order to be able to
enable the Over-Current Protection feature, if requested.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210119174421.226541-8-angelogioacchino.delregno@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-20 19:50:49 -06:00
Robert Foss d4863ef399 arm64: dts: qcom: sdm845-db845c: Fix reset-pin of ov8856 node
Switch reset pin of ov8856 node from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW,
this issue prevented the ov8856 from probing properly as it did not respon
to I2C messages.

Fixes: d4919a4456 ("arm64: dts: qcom: sdm845-db845c: Add ov8856 & ov7251
camera nodes")

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20201221100955.148584-1-robert.foss@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-18 22:34:38 -06:00
Dmitry Baryshkov 0fb56bf95c arm64: dts: qcom: qrb5165-rb5: sort nodes alphabetically
Move swr0 device node to keep alphabetical sorting order of device tree
nodes.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210116002346.422479-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-16 09:44:36 -06:00
Dmitry Baryshkov abf2c58aaa arm64: dts: qcom: qrb5165-rb5: fix uSD pins drive strength
Lower drive strength for microSD data and CMD pins from 16 to 10. This
fixes spurious card removal issues observed on some boards. Also this
change allows us to re-enable 1.8V support, which seems to work with
lowered drive strength.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Fixes: 53a8ccf1c7 ("arm64: dts: qcom: rb5: Add support for uSD card")
Link: https://lore.kernel.org/r/20201217183341.3186402-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-15 08:47:21 -06:00
Matthias Kaehlcke bc19af98ba arm64: dts: qcom: sc7180: Add labels for cpuN-thermal nodes
Add labels to the cpuN-thermal nodes to allow board files to use
a phandle instead replicating the node hierarchy when adjusting
certain properties.

Due to the 'sustainable-power' property CPU thermal zones are
more likely to need property updates than other SC7180 zones,
hence only labels for CPU zones are added for now.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210108141648.1.Ia8019b8b303ca31a06752ed6ceb5c3ac50bd1d48@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-15 08:29:21 -06:00
Danny Lin 6aabed5526 arm64: dts: qcom: sm8250: Add CPU capacities and energy model
Power and performance measurements were made using my freqbench [1]
benchmark coordinator, which isolates, offlines, and disables the timer
tick on test CPUs to maximize accuracy. It uses EEMBC CoreMark [2] as
the workload and measures power usage using the PM8150B PMIC's fuel
gauge.

The energy model dynamic-power-coefficient values were calculated with
    DPC = µW / MHz / V^2
for each OPP, and averaged across all OPPs within each cluster for the
final coefficient. Voltages were obtained from the qcom-cpufreq-hw
driver that reads voltages from the OSM LUT programmed into the SoC.

Normalized DMIPS/MHz capacity scale values for each CPU were calculated
from CoreMarks/MHz (CoreMark iterations per second per MHz), which
serves the same purpose. For each CPU, the final capacity-dmips-mhz
value is the C/MHz value of its maximum frequency normalized to
SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system.

A Xiaomi Redmi K30S Ultra device running a downstream Qualcomm 4.19
kernel was used for benchmarking to ensure proper frequency scaling and
other low-level controls.

Raw benchmark results can be found in the freqbench repository [3].
Below is a human-readable summary:

Frequency domains: cpu1 cpu4 cpu7
Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7
Baseline power usage: 1223 mW

===== CPU 1 =====
Frequencies: 300 403 518 614 691 787 883 979 1075 1171 1248 1344 1420 1516 1612 1708 1804

 300:  1114     3.7 C/MHz     29 mW    6.4 J   39.0 I/mJ   224.5 s
 403:  1497     3.7 C/MHz     33 mW    5.5 J   45.2 I/mJ   167.0 s
 518:  1925     3.7 C/MHz     48 mW    6.3 J   39.7 I/mJ   129.9 s
 614:  2281     3.7 C/MHz     73 mW    8.0 J   31.1 I/mJ   109.6 s
 691:  2566     3.7 C/MHz     46 mW    4.5 J   55.2 I/mJ    97.4 s
 787:  2923     3.7 C/MHz     86 mW    7.4 J   33.8 I/mJ    85.5 s
 883:  3279     3.7 C/MHz     77 mW    5.9 J   42.5 I/mJ    76.2 s
 979:  3635     3.7 C/MHz     65 mW    4.4 J   56.2 I/mJ    68.8 s
1075:  3992     3.7 C/MHz     71 mW    4.4 J   56.2 I/mJ    62.6 s
1171:  4348     3.7 C/MHz    121 mW    6.9 J   36.0 I/mJ    57.5 s
1248:  4633     3.7 C/MHz     79 mW    4.2 J   58.9 I/mJ    54.0 s
1344:  4990     3.7 C/MHz     81 mW    4.0 J   61.7 I/mJ    50.1 s
1420:  5275     3.7 C/MHz     85 mW    4.0 J   61.8 I/mJ    47.4 s
1516:  5632     3.7 C/MHz     88 mW    3.9 J   64.3 I/mJ    44.4 s
1612:  5988     3.7 C/MHz     92 mW    3.8 J   65.4 I/mJ    41.7 s
1708:  6346     3.7 C/MHz     96 mW    3.8 J   66.3 I/mJ    39.4 s
1804:  6701     3.7 C/MHz    105 mW    3.9 J   63.5 I/mJ    37.3 s

===== CPU 4 =====
Frequencies: 710 825 940 1056 1171 1286 1382 1478 1574 1670 1766 1862 1958 2054 2150 2246 2342 2419

 710:  6022     8.5 C/MHz    123 mW    5.1 J   49.1 I/mJ    41.5 s
 825:  7001     8.5 C/MHz    142 mW    5.1 J   49.4 I/mJ    35.7 s
 940:  7987     8.5 C/MHz    164 mW    5.1 J   48.7 I/mJ    31.3 s
1056:  8954     8.5 C/MHz    185 mW    5.2 J   48.3 I/mJ    27.9 s
1171:  9944     8.5 C/MHz    212 mW    5.3 J   46.9 I/mJ    25.2 s
1286: 10926     8.5 C/MHz    235 mW    5.4 J   46.4 I/mJ    22.9 s
1382: 11735     8.5 C/MHz    253 mW    5.4 J   46.4 I/mJ    21.3 s
1478: 12531     8.5 C/MHz    277 mW    5.5 J   45.2 I/mJ    20.0 s
1574: 13335     8.5 C/MHz    306 mW    5.7 J   43.6 I/mJ    18.8 s
1670: 14169     8.5 C/MHz    335 mW    5.9 J   42.2 I/mJ    17.7 s
1766: 14969     8.5 C/MHz    353 mW    5.9 J   42.3 I/mJ    16.7 s
1862: 15800     8.5 C/MHz    444 mW    7.0 J   35.6 I/mJ    15.8 s
1958: 16630     8.5 C/MHz    463 mW    7.0 J   35.9 I/mJ    15.0 s
2054: 17428     8.5 C/MHz    480 mW    6.9 J   36.3 I/mJ    14.4 s
2150: 18238     8.5 C/MHz    496 mW    6.8 J   36.8 I/mJ    13.7 s
2246: 19053     8.5 C/MHz    578 mW    7.6 J   32.9 I/mJ    13.1 s
2342: 19873     8.5 C/MHz    625 mW    7.9 J   31.8 I/mJ    12.6 s
2419: 20522     8.5 C/MHz    675 mW    8.2 J   30.4 I/mJ    12.2 s

===== CPU 7 =====
Frequencies: 844 960 1075 1190 1305 1401 1516 1632 1747 1862 1977 2073 2169 2265 2361 2457 2553 2649 2745 2841

 844:  7172     8.5 C/MHz    155 mW    5.4 J   46.4 I/mJ    34.9 s
 960:  8148     8.5 C/MHz    172 mW    5.3 J   47.4 I/mJ    30.7 s
1075:  9116     8.5 C/MHz    197 mW    5.4 J   46.2 I/mJ    27.4 s
1190: 10105     8.5 C/MHz    220 mW    5.4 J   46.0 I/mJ    24.8 s
1305: 11084     8.5 C/MHz    242 mW    5.5 J   45.8 I/mJ    22.6 s
1401: 11888     8.5 C/MHz    262 mW    5.5 J   45.4 I/mJ    21.0 s
1516: 12859     8.5 C/MHz    297 mW    5.8 J   43.2 I/mJ    19.5 s
1632: 13840     8.5 C/MHz    335 mW    6.1 J   41.3 I/mJ    18.1 s
1747: 14827     8.5 C/MHz    369 mW    6.2 J   40.1 I/mJ    16.9 s
1862: 15800     8.5 C/MHz    395 mW    6.3 J   40.0 I/mJ    15.8 s
1977: 16786     8.5 C/MHz    443 mW    6.6 J   37.9 I/mJ    14.9 s
2073: 17566     8.5 C/MHz    488 mW    6.9 J   36.0 I/mJ    14.2 s
2169: 18395     8.5 C/MHz    620 mW    8.4 J   29.7 I/mJ    13.6 s
2265: 19223     8.5 C/MHz    621 mW    8.1 J   30.9 I/mJ    13.0 s
2361: 20040     8.5 C/MHz    672 mW    8.4 J   29.8 I/mJ    12.5 s
2457: 20852     8.5 C/MHz    696 mW    8.3 J   29.9 I/mJ    12.0 s
2553: 21684     8.5 C/MHz    738 mW    8.5 J   29.3 I/mJ    11.5 s
2649: 22458     8.5 C/MHz    793 mW    8.8 J   28.3 I/mJ    11.1 s
2745: 23314     8.5 C/MHz    875 mW    9.4 J   26.6 I/mJ    10.7 s
2841: 24103     8.5 C/MHz    928 mW    9.6 J   26.0 I/mJ    10.4 s

[1] https://github.com/kdrag0n/freqbench
[2] https://www.eembc.org/coremark/
[3] https://github.com/kdrag0n/freqbench/tree/master/results/sm8250/k30s

Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20210112013255.415253-2-danny@kdrag0n.dev
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-15 08:29:11 -06:00
Danny Lin b4791e6955 arm64: dts: qcom: sm8250: Define CPU topology
sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within
the same CPU cluster and LLC (Last-Level Cache) domain. Define this
topology to help the scheduler make decisions.

Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20210112013255.415253-1-danny@kdrag0n.dev
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-15 08:29:02 -06:00
Stephan Gerhold 3716a583fe arm64: dts: qcom: msm8916-samsung-a2015: Fix sensors
When the BMC150 accelerometer/magnetometer was added to the device tree,
the sensors were working without specifying any regulator supplies,
likely because the regulators were on by default and then never turned off.

For some reason, this is no longer the case for pm8916_l17, which prevents
the sensors from working in some cases.

Now that the bmc150_accel/bmc150_magn drivers can enable necessary
regulators, declare the necessary regulator supplies to make the sensors
work again.

Fixes: 079f81acf1 ("arm64: dts: qcom: msm8916-samsung-a2015: Add accelerometer/magnetometer")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210111175358.97171-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-15 08:27:49 -06:00
Steev Klimaszewski 6be4ba5467 arm64: dts: sdm850: Add OPP tables for 2.84 and 2.96GHz
Running cpufreq-hw driver on Lenovo Yoga C630 laptop, the following
warning messages will be seen.

[    3.415340] cpu cpu4: Voltage update failed freq=2841600
[    3.418755] cpu cpu4: failed to update OPP for freq=2841600
[    3.422949] cpu cpu4: Voltage update failed freq=2956800
[    3.427086] cpu cpu4: failed to update OPP for freq=2956800

This is because the cpufreq-hw lookup table of SDM850 provides these two
set-points, but they are missing from OPP table in DT.  Let's create
sdm850.dtsi to add the OPP for them, so that the warning will be gone.

Signed-off-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210112090640.20062-1-shawn.guo@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-15 08:25:12 -06:00
Caleb Connolly 288ef8a426 arm64: dts: sdm845: add oneplus6/6t devices
Add initial support for the OnePlus 6 (enchilada) and 6T (fajita) based
on the sdm845-mtp DT with the following functionality:

 * Touch
 * Display
 * GPU
 * Wlan and Bluetooth
 * USB peripheral mode
 * Remoteproc

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Caleb Connolly <caleb@connolly.tech>
Link: https://lore.kernel.org/r/20210114203057.64541-2-caleb@connolly.tech
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-15 08:14:20 -06:00
Dmitry Baryshkov 74097d805e arm64: dts: qcom: sm8250: correct sdhc_2 xo clk
sdhc_2 uses 19200000 Hz clock rather than wrongly specified xo_board
(39400000 Hz). Specify correct clock to fix DLL setup for SDR104 mode.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: c4cf0300be ("arm64: dts: qcom: sm8250: Add support for SDC2")
Link: https://lore.kernel.org/r/20210109011252.3436533-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-14 21:50:24 -06:00
Dmitry Baryshkov c2c76ddb14 arm64: dts: qcom: qrb5165-rb5: add HDMI audio playback
Add support for audio output over the HDMI output using Tertiary I2S
and LT9611UXC DSI-to-HDMI bridge.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210115024713.92574-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-14 21:11:39 -06:00
Dmitry Baryshkov 8f03014019 arm64: dts: qcom: qrb5165-rb5: enable cdsp device
Enable Compute DSP (cdsp) on QRB5165-RB5 platform and provide firmware
filename used to boot the cdsp.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210115024156.92265-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-14 21:11:12 -06:00
Danny Lin b2e3f89768 arm64: dts: qcom: sm8150: Add support for deep CPU cluster idle
This commit adds support for deep idling of the entire unified DynamIQ
CPU cluster on sm8150. In this idle state, the LLCC (Last-Level Cache
Controller) is powered off and the AOP (Always-On Processor) enters a
low-power sleep state.

I'm not sure what the per-CPU 0x400000f4 idle state previously
contributed by Qualcomm as the "cluster sleep" state is, but the
downstream kernel has no such state. The real deep cluster idle state
is 0x41000c244, composed of:

    Cluster idle state: (0xc24) << 4 = 0xc240
    Is reset state: 1 << 30 = 0x40000000
    Affinity level: 1 << 24 = 0x1000000
    CPU idle state: 0x4 (power collapse)

This setup can be replicated with the PSCI power domain cpuidle driver,
which utilizes OSI to enter cluster idle when the last active CPU
enters idle.

The cluster idle state cannot be used as a plain cpuidle state because
it requires that all CPUs in the cluster are idling.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20210105201000.913183-1-danny@kdrag0n.dev
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-12 08:10:51 -06:00
Douglas Anderson e5376f2ea2 arm64: dts: qcom: Clean up sc7180-trogdor voltage rails
For a bunch of rails we really don't do anything with them in Linux.
These are things like modem voltage rails that the modem manages these
itself and core rails (like IO rails) that are setup to just
automagically do the right thing by the firmware.

Let's stop even listing those rails in our device tree.

The net result of this is that some of these rails might be able to go
down to a lower voltage or perhaps transition to LPM (low power mode)
sometimes.

Here's a list of what we're doing and why:

* L1A - only goes to SoC and doesn't seem associated with any
  particular peripheral. Kernel isn't doing anything with
  this. Removing from dts. NET IMPACT: rail might drop from 1.2V to
  1.178V and switch to LPM in some cases depending on firmware.
* L2A - only goes to SoC and doesn't seem associated with any
  particular peripheral. Kernel isn't doing anything with
  this. Removing from dts. NET IMPACT: rail might switch to LPM in
  some cases depending on firmware.
* L3A - only goes to SoC and doesn't seem associated with any
  particular peripheral. Kernel isn't doing anything with
  this. Removing from dts. NET IMPACT: rail might switch to LPM in
  some cases depending on firmware.
* L5A - seems to be totally unused as far as I can tell and doesn't
  even come off QSIP. Removing from dts.
* L6A - only goes to SoC and doesn't seem associated with any
  particular peripheral (I think?). Kernel isn't doing anything with
  this. Removing from dts. NET IMPACT: rail might switch to LPM in
  some cases depending on firmware.
* L16A - Looks like this is only used for internal RF stuff. Removing
  from dts. NET IMPACT: rail might switch to LPM in some cases
  depending on firmware.
* L1C - Just goes to WiFi / Bluetooth. Trust how IDP has this set and
  put this back at 1.616V min.
* L4C - This goes out to the eSIM among other places. This looks like
  it's intended to be for SIM card and modem manages. NET IMPACT:
  rail might switch to LPM in some cases depending on firmware.
* L5C - This goes to the physical SIM.  This looks like it's intended
  to be for SIM card and modem manages. NET IMPACT: rail might drop
  from 1.8V to 1.648V and switch to LPM in some cases depending on
  firmware.

NOTE: in general for anything which is supposed to be managed by Linux
I still left it all forced to HPM since I'm not 100% sure that all the
needed calls to regulator_set_load() are in place and HPM is safer.
Switching more things to LPM can happen in a future patch.

ALSO NOTE: Power measurements showed no measurable difference after
applying this patch, so perhaps it should be viewed more as a cleanup
than any power savings.

Reviewed-by: Alexandru M Stan <amstan@google.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201207143255.1.Ib92ec35163682dec4b2fbb4bde0785cb6e6dde27@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-11 17:27:05 -06:00
Stephan Gerhold 826e6faf49 arm64: dts: qcom: msm8916-samsung-a5u: Fix iris compatible
Unlike most MSM8916 boards, samsung-a5u uses WCN3660B instead of
WCN3620 to support the 5 GHz band additionally.

WCN3660B has similar requirements as WCN3620, but it needs the XO
clock to run at 48 MHz instead of 19.2 MHz. So far it was possible
to describe that configuration using the qcom,wcn3680 compatible.

However, as of commit 8490987bdb ("wcn36xx: Hook and identify RF_IRIS_WCN3680"),
the wcn36xx driver will now use the qcom,wcn3680 compatible
to enable functionality specific to WCN3680. In particular,
WCN3680 supports 802.11ac, which is not available in WCN3660B.

Use the new qcom,wcn3660b compatible to describe the chip properly.

Fixes: 0d70519991 ("arm64: dts: msm8916-samsung-a5u: Override iris compatible")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210106102134.59801-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07 11:09:33 -06:00
Douglas Anderson f772081f48 arm64: dts: qcom: sc7180: Add "dp_hot_plug_det" pinconf for trogdor
We have an external pull on this line, so disable the internal pull.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210106152537.1.Ib4b5b0e88fdc825c0e2662bab982dda8af2297b2@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07 11:03:23 -06:00
Danny Lin 5b2dae7218 arm64: dts: qcom: sm8150: Add CPU capacities and energy model
Power and performance measurements were made using my freqbench [1]
benchmark coordinator, which isolates, offlines, and disables the timer
tick on test CPUs to maximize accuracy. It uses EEMBC CoreMark [2] as
the workload and measures power usage using the PM8150B PMIC's fuel
gauge.

The energy model dynamic-power-coefficient values were calculated with
    DPC = µW / MHz / V^2
for each OPP, and averaged across all OPPs within each cluster for the
final coefficient. Voltages were obtained from the qcom-cpufreq-hw
driver that reads voltages from the OSM LUT programmed into the SoC.

Normalized DMIPS/MHz capacity scale values for each CPU were calculated
from CoreMarks/MHz (CoreMark iterations per second per MHz), which
serves the same purpose. For each CPU, the final capacity-dmips-mhz
value is the C/MHz value of its maximum frequency normalized to
SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system.

An Asus ZenFone 6 device running a downstream Qualcomm 4.14 kernel
(LA.UM.8.1.r1-15600-sm8150.0) was used for benchmarks to ensure proper
frequency scaling and other low-level controls.

Raw benchmark results can be found in the freqbench repository [3].
Below is a human-readable summary:

Frequency domains: cpu1 cpu4 cpu7
Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7
Baseline power usage: 1400 mW

===== CPU 1 =====
Frequencies: 300 403 499 576 672 768 844 940 1036 1113 1209 1305 1382 1478 1555 1632 1708 1785

 300:  1114     3.7 C/MHz     52 mW   11.8 J   21.3 I/mJ   224.4 s
 403:  1497     3.7 C/MHz     57 mW    9.5 J   26.2 I/mJ   167.0 s
 499:  1854     3.7 C/MHz     73 mW    9.8 J   25.5 I/mJ   134.9 s
 576:  2139     3.7 C/MHz     83 mW    9.7 J   25.8 I/mJ   116.9 s
 672:  2495     3.7 C/MHz     65 mW    6.5 J   38.6 I/mJ   100.2 s
 768:  2852     3.7 C/MHz     72 mW    6.3 J   39.4 I/mJ    87.7 s
 844:  3137     3.7 C/MHz     77 mW    6.2 J   40.5 I/mJ    79.7 s
 940:  3493     3.7 C/MHz     84 mW    6.0 J   41.8 I/mJ    71.6 s
1036:  3850     3.7 C/MHz     91 mW    5.9 J   42.5 I/mJ    64.9 s
1113:  4135     3.7 C/MHz     96 mW    5.8 J   43.2 I/mJ    60.5 s
1209:  4491     3.7 C/MHz    102 mW    5.7 J   44.2 I/mJ    55.7 s
1305:  4848     3.7 C/MHz    110 mW    5.7 J   44.0 I/mJ    51.6 s
1382:  5133     3.7 C/MHz    114 mW    5.5 J   45.2 I/mJ    48.7 s
1478:  5490     3.7 C/MHz    120 mW    5.5 J   45.7 I/mJ    45.5 s
1555:  5775     3.7 C/MHz    126 mW    5.5 J   45.8 I/mJ    43.3 s
1632:  6060     3.7 C/MHz    131 mW    5.4 J   46.1 I/mJ    41.3 s
1708:  6345     3.7 C/MHz    137 mW    5.4 J   46.3 I/mJ    39.4 s
1785:  6630     3.7 C/MHz    146 mW    5.5 J   45.5 I/mJ    37.7 s

===== CPU 4 =====
Frequencies: 710 825 940 1056 1171 1286 1401 1497 1612 1708 1804 1920 2016 2131 2227 2323 2419

 710:  2765     3.9 C/MHz    126 mW   11.4 J   22.0 I/mJ    90.4 s
 825:  6432     7.8 C/MHz    206 mW    8.0 J   31.2 I/mJ    38.9 s
 940:  7331     7.8 C/MHz    227 mW    7.7 J   32.3 I/mJ    34.1 s
1056:  8227     7.8 C/MHz    249 mW    7.6 J   33.0 I/mJ    30.4 s
1171:  9127     7.8 C/MHz    261 mW    7.2 J   34.9 I/mJ    27.4 s
1286: 10020     7.8 C/MHz    289 mW    7.2 J   34.6 I/mJ    25.0 s
1401: 10918     7.8 C/MHz    311 mW    7.1 J   35.1 I/mJ    22.9 s
1497: 11663     7.8 C/MHz    336 mW    7.2 J   34.7 I/mJ    21.4 s
1612: 12546     7.8 C/MHz    375 mW    7.5 J   33.5 I/mJ    19.9 s
1708: 13320     7.8 C/MHz    398 mW    7.5 J   33.5 I/mJ    18.8 s
1804: 14069     7.8 C/MHz    456 mW    8.1 J   30.9 I/mJ    17.8 s
1920: 14909     7.8 C/MHz    507 mW    8.5 J   29.4 I/mJ    16.8 s
2016: 15706     7.8 C/MHz    558 mW    8.9 J   28.1 I/mJ    15.9 s
2131: 16612     7.8 C/MHz    632 mW    9.5 J   26.3 I/mJ    15.1 s
2227: 17349     7.8 C/MHz    698 mW   10.1 J   24.8 I/mJ    14.4 s
2323: 18088     7.8 C/MHz    717 mW    9.9 J   25.2 I/mJ    13.8 s
2419: 18835     7.8 C/MHz    845 mW   11.2 J   22.3 I/mJ    13.3 s

===== CPU 7 =====
Frequencies: 825 940 1056 1171 1286 1401 1497 1612 1708 1804 1920 2016 2131 2227 2323 2419 2534 2649 2745 2841

 825:  3215     3.9 C/MHz    158 mW   12.3 J   20.3 I/mJ    77.8 s
 940:  7330     7.8 C/MHz    269 mW    9.2 J   27.3 I/mJ    34.1 s
1056:  8227     7.8 C/MHz    291 mW    8.8 J   28.2 I/mJ    30.4 s
1171:  9125     7.8 C/MHz    316 mW    8.7 J   28.9 I/mJ    27.4 s
1286: 10024     7.8 C/MHz    338 mW    8.4 J   29.6 I/mJ    25.0 s
1401: 10922     7.8 C/MHz    365 mW    8.4 J   29.9 I/mJ    22.9 s
1497: 11674     7.8 C/MHz    383 mW    8.2 J   30.4 I/mJ    21.4 s
1612: 12564     7.8 C/MHz    406 mW    8.1 J   30.9 I/mJ    19.9 s
1708: 13317     7.8 C/MHz    427 mW    8.0 J   31.2 I/mJ    18.8 s
1804: 14062     7.8 C/MHz    446 mW    7.9 J   31.5 I/mJ    17.8 s
1920: 14966     7.8 C/MHz    498 mW    8.3 J   30.1 I/mJ    16.7 s
2016: 15711     7.8 C/MHz    513 mW    8.2 J   30.6 I/mJ    15.9 s
2131: 16599     7.8 C/MHz    599 mW    9.0 J   27.7 I/mJ    15.1 s
2227: 17353     7.8 C/MHz    622 mW    9.0 J   27.9 I/mJ    14.4 s
2323: 18095     7.8 C/MHz    704 mW    9.7 J   25.7 I/mJ    13.8 s
2419: 18849     7.8 C/MHz    738 mW    9.8 J   25.5 I/mJ    13.3 s
2534: 19761     7.8 C/MHz    824 mW   10.4 J   23.9 I/mJ    12.7 s
2649: 20658     7.8 C/MHz    882 mW   10.7 J   23.4 I/mJ    12.1 s
2745: 21400     7.8 C/MHz   1003 mW   11.7 J   21.3 I/mJ    11.7 s
2841: 22147     7.8 C/MHz   1092 mW   12.3 J   20.3 I/mJ    11.3 s

[1] https://github.com/kdrag0n/freqbench
[2] https://www.eembc.org/coremark/
[3] https://github.com/kdrag0n/freqbench/tree/master/results/sm8150/main

Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20201221002907.2870059-4-danny@kdrag0n.dev
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-05 16:36:22 -06:00
Danny Lin 81188f585d arm64: dts: qcom: sm8150: Add PSCI idle states
Like other Qualcomm SoCs, sm8150 exposes CPU and cluster idle states
through PSCI. Define the idle states to save power when the CPU is not
in active use.

These idle states, latency, and residency values match the downstream
4.14 kernel from Qualcomm as of LA.UM.8.1.r1-15600-sm8150.0.

It's worth noting that the CPU has an additional C3 power collapse idle
state between WFI and rail power collapse (with PSCI mode 0x40000003),
but it is not officially used in downstream kernels due to "thermal
throttling issues."

Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20201221002907.2870059-3-danny@kdrag0n.dev
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-05 16:36:18 -06:00
Danny Lin 066d21bcf6 arm64: dts: qcom: sm8150: Define CPU topology
sm8150 has a big.LITTLE CPU setup with DynamIQ, so all cores are within
the same CPU cluster and LLC (Last-Level Cache) domain. Define this
topology to help the scheduler make decisions.

Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20201221002907.2870059-2-danny@kdrag0n.dev
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-05 16:35:54 -06:00
Stephen Boyd 8d079bf204 arm64: dts: qcom: sc7180: Drop pinconf on dp_hot_plug_det
We shouldn't put any pinconf here in case someone decides to invert this
HPD signal or remove an external pull-down. It's better to leave that to
the board pinconf nodes, so drop it here.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reported-by: Douglas Anderson <dianders@chromium.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Fixes: 681a607ad2 ("arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20201215020004.731239-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:26 -06:00
J.R. Divya Antony bd167507d5 arm64: dts: qcom: Add device tree for ASUS Zenfone 2 Laser
ASUS Zenfone 2 Laser Z00L is a smartphone based on MSM8916 SoC
released on 2015.

Add a device tree for Z00L with initial support for:
  - SDHCI (internal storage)
  - USB Device Mode
  - UART
  - Regulators

Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: J.R. Divya Antony <d.antony.jr@gmail.com>
Link: https://lore.kernel.org/r/20201209143743.7383-1-d.antony.jr@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:26 -06:00
Douglas Anderson 465b13cc0a arm64: dts: qcom: Fix SD card vqmmc max voltage on sc7180-trogdor
It never makes sense to set the IO voltage of the SD card (vqmmc) to a
voltage that's higher than the voltage of the card's main power supply
(vmmc).  The card's main voltage is 2.952V on trogdor, so let's set
the max for the IO voltage to the same.

NOTE: On Linux, this is pretty much a no-op currently.  Linux already
makes an effort to match vqmmc with vmmc when running at "3.3" signal
voltage, so both before and after this change we end up running vqmmc
at 2.904V when talking to non-UHS cards.  It still seems cleaner to
make it a little more correct, though.

Also note: as per above, on Linux right now we end up running vqmmc as
2.904V even though vmmc is 2.952V.  This isn't super ideal but
shouldn't really hurt.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201204104900.1.I0a4ac2c7f4d405431cf95eb7b7c36800660516ec@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:25 -06:00
Dmitry Baryshkov 88b57bc335 arm64: dts: qcom: sm8250: rename smem device node to follow schema
Rename 'qcom,smem' to just 'smem' to follow the rest of SoC (and device
schema).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203191335.927001-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:25 -06:00
Srinivas Kandagatla 590a135ebd arm64: dts: qcom: qrb5165-rb5: Add Audio support
This patch add support for two WSA881X smart speakers attached via Soundwire
and a DMIC0 on the main board.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201202180741.16386-7-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:25 -06:00
Srinivas Kandagatla b657d37262 arm64: dts: qcom: sm8250: add mi2s pinconfs
Add primary and tertinary mi2s pinconfs required to get I2S audio.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201202180741.16386-6-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:24 -06:00
Srinivas Kandagatla 768270ca57 arm64: dts: qcom: sm8250: add wsa and va codec macros
Add support for WSA and VA codec macros along with WSA soundwire
controller required for getting audio on RB5.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201202180741.16386-5-srinivas.kandagatla@linaro.org
[bjorn: Replaced LPASS_CDC clock defines with constants]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:24 -06:00
Srinivas Kandagatla 3160c1b894 arm64: dts: qcom: sm8250: add lpass lpi pin controller node
Add LPASS LPI pinctrl node required for Audio functionality on RB5.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201202180741.16386-4-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:23 -06:00
Srinivas Kandagatla 793bbd2db7 arm64: dts: qcom: sm8250: add audio clock controllers
Add audiocc and aoncc clock controller nodes required for audio on RB5.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201202180741.16386-3-srinivas.kandagatla@linaro.org
[bjorn: Dropped includes for now]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:23 -06:00
Srinivas Kandagatla 63e10791cc arm64: dts: qcom: sm8250: add apr and its services
Add apr node and its associated services required for audio on RB5.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201202180741.16386-2-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:23 -06:00
Dmitry Baryshkov 3f2094dfbe arm64: dts: qcom: sm8250: power up dispcc on sm8250 by MMCX regulator
Add regulator controlling MMCX power domain to be used by display clock
controller on SM8250.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203142105.841666-8-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:22 -06:00
Dmitry Baryshkov d004c631ea arm64: dts: qcom: qrb5165-rb5: add lt9611 HDMI bridge
Add device tree node for the lontium lt9611ux DSI-HDMI bridge.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203142105.841666-7-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:22 -06:00
Dmitry Baryshkov 04c8e3f7e9 arm64: dts: qcom: qrb5165-rb5: correct vdc_3v3 regulator
vdc_3v3 regulator is sourced from 12V, but it is controlled by l11c
regulator, so set it as vin for vdc_3v3.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203142105.841666-6-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:21 -06:00
Dmitry Baryshkov 9e301a547a arm64: dts: qcom: sm8250-mtp: add gpu/zap-shader node
Add firmware configuration for Adreno zap shader on sm8250-mtp.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203142105.841666-5-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:21 -06:00
Dmitry Baryshkov 0b2033dcf4 arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node
Add firmware configuration for Adreno zap shader on qrb5165-rb5.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203142105.841666-4-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:21 -06:00
Dmitry Baryshkov 46967bb61a arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203142105.841666-3-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:20 -06:00
Dmitry Baryshkov 7c1dffd471 arm64: dts: qcom: sm8250.dtsi: add display system nodes
Add device tree nodes for mdss, mdp, dsi0/1.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203142105.841666-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:20 -06:00
Dmitry Baryshkov 221f0ef37f arm64: dts: sm8250-mtp: enable USB host nodes
Enable both USB host controller, hsphy and qmpphy nodes on sm8250. Add
missing pm8150 ldo18 definition (used by USB qmp phys). Both controllers
are locked to host mode: dual role on first controller is not enabled.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201127092646.122663-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:19 -06:00
Manivannan Sadhasivam 0085a33a25 arm64: dts: qcom: sm8250: Add support for LLCC block
Add support for Last Level Cache Controller (LLCC) in SM8250 SoC.
This LLCC is used to provide common cache memory pool for the cores in
the SM8250 SoC thereby minimizing the percore caches.

Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20201130093924.45057-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28 12:14:19 -06:00
Linus Torvalds 5c8fe583cc Linux 5.11-rc1 2020-12-27 15:30:22 -08:00