Commit Graph

1578 Commits

Author SHA1 Message Date
Tomasz Figa d97f5b9804 pinctrl: exynos: Add driver data for Exynos3250
This patch adds driver data (bank list and EINT layout) for Exynos3250
to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
ports. There are 23 general port groups.

Changes from v1:
- Add signed-off of sender
- Post only separated patch for pinctrl from following patchset(v1)
  : https://lkml.org/lkml/2014/4/10/286

Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 09:00:25 +02:00
Alexander Stein 47f227163a pinctrl/at91: Fix mask creation in at91_gpio_dbg_show
pin_to_mask expects a bank pin number. So do not add the chip base.

Without that patch cat /sys/kernel/debug/gpio looks like that:
GPIOs 0-31, platform/fffff200.gpio, fffff200.gpio:
[spi32766.0] GPIOfffff200.gpio5: [gpio] set
[ads7846_pendown] GPIOfffff200.gpio15: [gpio] set
[ohci_vbus] GPIOfffff200.gpio21: [gpio] set
[ohci_vbus] GPIOfffff200.gpio24: [gpio] set
[button1] GPIOfffff200.gpio28: [gpio] clear
[button2] GPIOfffff200.gpio29: [gpio] clear

GPIOs 32-63, platform/fffff400.gpio, fffff400.gpio:
[sda] GPIOfffff400.gpio4: [periph A]
[scl] GPIOfffff400.gpio5: [periph A]
[spi32766.3] GPIOfffff400.gpio11: [periph A]
[error] GPIOfffff400.gpio22: [periph A]
[run] GPIOfffff400.gpio23: [periph A]

GPIOs 64-95, platform/fffff600.gpio, fffff600.gpio:
[reset_pin] GPIOfffff600.gpio29: [periph A]

GPIOs 96-127, platform/fffff800.gpio, fffff800.gpio:
[led1] GPIOfffff800.gpio5: [periph A]
[led2] GPIOfffff800.gpio6: [periph A]
[led3] GPIOfffff800.gpio7: [periph A]
[led4] GPIOfffff800.gpio8: [periph A]

GPIOs 128-159, platform/fffffa00.gpio, fffffa00.gpio:
[button3] GPIOfffffa00.gpio10: [periph A]
[button4] GPIOfffffa00.gpio12: [periph A]

Note that every bank despite bank 0 only shows "periph A" which are
obviously used as GPIOs.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 23:45:57 +02:00
Alexander Stein 80cc37329d pinctrl/at91: convert driver to use gpiolib irqchip
This converts the AT91 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 23:37:21 +02:00
Andrew Bresticker a73d2e30b4 pinctrl: as3722: fix handling of GPIO invert bit
The AS3722_GPIO_INV bit will always be blindly overwritten by
as3722_pinctrl_gpio_set_direction() and will be ignored when
setting the value of the GPIO in as3722_gpio_set() since the
enable_gpio_invert flag is never set.  This will cause an
initially inverted GPIO to toggle when requested as an output,
which could be problematic if, for example, the GPIO controls
a critical regulator.

Instead of setting up the enable_gpio_invert flag, just leave
the invert bit alone and check it before setting the GPIO value.

Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 17:04:11 +02:00
Stephen Warren 443ac95302 pinctrl: tegra: add missing kerneldoc
The kerneldoc for struct tegra_pingroup didn't describe all of the fields
in the struct. Add some extra kerneldoc to fix that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:55:41 +02:00
Stephen Warren 36e80dca9f pinctrl: tegra: print better error messages
When an attempt is made to configure an unsupported option on a pin,
print the DT property name of that option, so it's easier to debug
what the problem is.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:53:43 +02:00
Stephen Warren 0298fc3e1b pinctrl: tegra: reduce size of data table fields
The range of npins and function ID values is small enough to fit into a
u8. Use this type rather than unsigned to shrink the pinmux data tables.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:52:38 +02:00
Stephen Warren 6240d691be pinctrl: tegra: remove fsafe from data tables
The fsafe value in the pingroup data tables is only used to implement
tegra_pinctrl_disable(). The only reason this function is called is when
dynamically switching between pinmux states, i.e. when disabling the old
state before programming the new state. It's simpler to have the new
target state define the expected value of each pin (and all current DTs
do that). This also gives more flexibility, since it allows individual
boards explicit control over the "inactive" mux function for each pin,
rather than requiring it to be an SoC-specific value. Assuming this, we
can get rid of the fsafe value from the driver completely, thus saving
some more space in the driver tables.

While re-writing the content of tegra124_pingroups[], fix the indentation
to use a TAB instead of spaces.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:50:24 +02:00
Stephen Warren e53b797474 pinctrl: tegra: remove redundant data table fields
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel
options has the relevant HW register fields in the same register as the
mux function selection. Similarly, the drvtype option is always in the
drive register, if it is supported at all. Hence, we don't need to have
struct *_reg fields in the pin group table to define which register and
bank to use for those options. Delete this to save space in the driver's
data tables.

However, many of those options are not supported on all SoCs, or not
supported on some pingroups. We need a way to detect when they are
supported. Previously, this was indicated by setting the struct *_reg
field to -1. With the struct *_reg fields removed, we use the struct
*_bit fields for this purpose instead. The struct *_bit fields need to
be expanded from 5 to 6 bits in order to store a value outside the valid
HW bit range of 0..31.

Even without removing the struct *_reg fields, we still need to add code
to validate the struct *_bit fields, since some struct *_bit fields were
already being set to -1, without an option-specific struct *_reg field to
"guard" them. In other words, before this change, the pinmux driver might
allow some unsupported options to be written to HW.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:48:39 +02:00
Wolfram Sang a16b81dcbf pinctrl: pfc: r8a7790: add mux data for IIC(B) cores
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:39:41 +02:00
Wolfram Sang 35a493de0d pinctrl: pfc: r8a7790: add i2c0 muxing
Add the muxing for the last missing i2c rcar core. Fix the sorting for
SH_PFC_PIN_NAMED while we are here.

Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:38:23 +02:00
Fabio Estevam 08b519534e pinctrl: pinctrl-imx: Print the mux_mode field in hex format
With debug enabled we get better readability dumps of the mux_mode register if
we use hexadecimal format instead:

imx6sl-pinctrl 20e0000.iomuxc: MX6SL_PAD_FEC_REF_CLK: 0x10 0x0001b0a8

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:10:35 +02:00
Kuninori Morimoto c57a05b0eb sh-pfc: r8a7791: Add Audio pin support
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:09:29 +02:00
Kuninori Morimoto b664cd1f02 sh-pfc: r8a7791: Add SSI pin support
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:08:16 +02:00
Christian Ruppert 4c5fba3d4a pinctrl/TB10x: Fix signedness bug
In the TB10x pin database, a port index of -1 is used to indicate
unmuxed GPIO pin groups. This bug fixes a 'cast to unsigned' bug of
this value.

Thanks to Dan Carpenter for highlighting this.

CC: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 14:55:02 +02:00
Antoine Ténart b6369a8f15 pinctrl: sunxi: fix typo in module author address
According to the MODULE_AUTHOR() comments, the author name should be
"Name <email>" or just "Name". Add the missing '>'.

Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 14:53:24 +02:00
Antoine Ténart e5b3b2d9ed pinctrl: allows not to define the get_group_pins operation
When using a group only pinctrl driver, which does not have any
information on the pins it is useless to define a get_group_pins
always returning an empty list of pins.

When not using get_group_pin[1], a driver must implement it so
pins = NULL and num_pins = 0. This patch makes it the default
behaviour if not defined in the pinctrl driver when used in
pinmux enable and disable funtions and in pinctrl_groups_show.

It also adds a check in pinctrl_get_group_pins and return -EINVAL if
not defined. This function is called in the gpiolib when adding when
pingroup range. It cannot be used if no group is defined, so this seams
reasonable.

[1] get_group_pin(struct pinctrl_dev *pctldev,
		  unsigned selector,
		  const unsigned **pins,
		  unsigned *num_pins);

Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 14:47:02 +02:00
Boris BREZILLON cf2908e4ff pinctrl: sunxi: add reset control support
The A31 SoC define a reset line for the R_PIO block which needs to be
deasserted.

Try to retrieve a reset control and deassert if one was found.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:47:43 +02:00
Boris BREZILLON d9d0e1f658 pinctrl: sunxi: define A31 R_PIO pin functions
The A31 SoC provides both PL and PM pio bank through the R_PIO block.

These pins all support gpio function and can bbe assigned to system
peripherals (like TWI, P2WI, JTAG, ...)

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:45:08 +02:00
Boris BREZILLON d83c82ce7c pinctrl: sunxi: support multiple pin controller
Add support for multiple pin controller instances.

First remove the static definition of the sunxi gpio chip struct and fill
the dynamically struct instead.
Then define a new pin_base field in the sunxi_pinctrl_desc which will be
used to specify the gpiochip base pin.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:42:36 +02:00
Boris BREZILLON 0aba61787f pinctrl: sunxi: add PL and PM pin definitions
Define PL and PM pin macros.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:41:23 +02:00
Boris BREZILLON e2bddc6a7d pinctrl: sunxi: disable clk when failing to probe pin controller
Disable the clk when failing to probe the pin controller device.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:40:05 +02:00
Boris BREZILLON 6415093f7f pinctrl: sunxi: check clk_prepare_enable return value
Check the clk_prepare_enable return value to avoid false positive probe.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:38:35 +02:00
Maxime COQUELIN 3b02dad20f pinctrl: st: Use ARRAY_SIZE for STiH415 data
This patch completes the one that used ARRAY_SIZE for STiH407 and STiH416
for setting ninput_delays and noutput_delays fields.

Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Maxime COQUELIN a4bc1f57fd pinctrl: st: Use const qualifier when required
This patch adds const qualifier where applicable.

Reported-by: Joe Perches <joe@perches.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Axel Lin edb052c3c2 pinctrl: lantiq: Fix header file include guard
Define __PINCTRL_LANTIQ_H to prevent multiple inclusion.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Axel Lin f77329d1ed pinctrl: adi2: Statize adi_gpio_irq_domain_ops
It's only referenced in this file, make it static.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Laurent Pinchart d10046e25c pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groups
The DU parallel interface ODDF signal is optional, move it out of the
HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are
independent, split them to two different groups.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Uwe Kleine-König fb95a94b04 pinctrl: msm8x74: make Kconfig dependency more strict
This driver is only useful on MSM8x74, so let the driver depend on
ARCH_QCOM but allow compile coverage testing.
The main benefit is that the driver isn't available to be selected for
machines that don't have the matching hardware.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Bjorn Andersson e2c802be58 pinctrl: msm: Add definitions for the APQ8064 platform
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm APQ8064 platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Bjorn Andersson 3c25381f9b pinctrl: msm: Make number of functions variable
The various pins may have different number of functions defined, so make this
number definable per pin instead of just increasing it to the largest one for
all of the platforms.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:34 +02:00
Linus Walleij 130cbe3082 pinctrl: st: use gpiolib irqchip helpers
This lets the gpiolib core handle the irqchip set-up and
chained IRQ on the primary (behind the mux) IRQ chip in
the st pinctrl driver.

Default irq type is set to level low at irqchip add time.

The v1 was sent by Linus
(https://lkml.org/lkml/2014/4/4/287).

Two changes were necessary to make it to work properly
on STiH416:
  1 - dev reference was not passed to the gpio_chip
      struct, causing a panic.
  2 - gpiochip_irqchip_add passed IRQ_TYPE_NONE as
      default type, which caused lot of warnings at
      init time. I choose IRQ_TYPE_LEVEL_LOW as default.

Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Maxime COQUELIN <maxime.coquelin@st.com>
2014-04-22 08:41:34 +02:00
Linus Walleij c15c0d160c pinctrl: st: switch IRQ locking to resource callbacks
In the mass-conversion to the new irqchip callbacks, this
in-transit IRQ support was missed. Fix it.

Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Cc: Maxime COQUELIN <maxime.coquelin@st.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:34 +02:00
Sherman Yin 7418b5cc81 pinctrl: Rename Broadcom Capri pinctrl driver
To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl
driver and its related CONFIG option are renamed to bcm281xx.

Devicetree compatible string and binding documentation use
"brcm,bcm11351-pinctrl" to match the machine binding here:
Documentation/devicetree/bindings/arm/bcm/bcm11351.txt

This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145
and BCM28155 SoCs.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Bjorn Andersson 48f15e94f5 pinctrl: msm: Correct interrupt code for TLMM v2
Acking interrupts are done differently between on v2 and v3, so add an extra
attribute to the pingroup struct to let the platform definitions control this.
Also make sure to start dual edge detection by detecting the rising edge.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Linus Walleij 6888c75b24 pinctrl: nomadik: delete stray debug print
I left this in by mistake, get rid of it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Heiko Stübner c4a532dee6 pinctrl: rockchip: handle first half of rk3188-bank0 correctly
The first half of pinbank 0 only has one muxing function (as gpios) and
does not have a special mux-register.

Therefore ensure that no other mux function can be selected and also do not
write to a non-existent register.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Heiko Stübner 14797189b3 pinctrl: rockchip: add return value to rockchip_set_mux
In a following change, rockchip_set_mux gets the possibility to fail.
Therefore add a return value to it and honor error codes in functions
using rockchip_set_mux.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Beniamino Galvani 22c0d7e36f pinctrl: rockchip: fix offset of mux registers for rk3188
The correct value of .mux_offset for rk3188 seems to be 0x60
instead of 0x68.

Heiko adds:

GPIO0 only has the second two IOMUX registers:
- GRF_GPIO0C_IOMUX at 0x68
- GRF_GPIO0D_IOMUX at 0x6c
which I guess is where my mistake comes from.

It looks like there does no iomux register exist at all
for the first 16 pins.

In any case, the current number is wrong, and the 0x60
offset is the correct one, but I guess we need to
determine what the affected pins do - do they always have a
gpio mux or such?

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Linus Torvalds 154d6f18a4 This is the bulk of GPIO changes for v3.15:
- Merged in a branch of irqchip changes from Thomas
   Gleixner: we need to have new callbacks from the
   irqchip to determine if the GPIO line will be eligible
   for IRQs, and this callback must be able to say "no".
   After some thinking I got the branch from tglx and
   have switched all current users over to use this.
 
 - Based on tglx patches, we have added some generic
   irqchip helpers in the gpiolib core. These will
   help centralize code when GPIO drivers have simple
   chained/cascaded IRQs. Drivers will still define
   their irqchip vtables, but the gpiolib core will
   take care of irqdomain set-up, mapping from local
   offsets to Linux irqs, and reserve resources by
   marking the GPIO lines for IRQs.
 
 - Initially the PL061 and Nomadik GPIO/pin control
   drivers have been switched over to use the new
   gpiochip-to-irqchip infrastructure with more
   drivers expected for the next kernel cycle. The
   factoring of just two drivers still makes it worth
   it so it is already a win.
 
 - A new driver for the Synopsys DesignWare APB GPIO
   block.
 
 - Modify the DaVinci GPIO driver to be reusable also
   for the new TI Keystone architecture.
 
 - A new driver for the LSI ZEVIO SoCs.
 
 - Delete the obsolte tnetv107x driver.
 
 - Some incremental work on GPIO descriptors: have
   gpiod_direction_output() use a logical level,
   respecting assertion polarity through ACTIVE_LOW
   flags, adding gpiod_direction_output_raw() for the
   case where you want to set that very value. Add
   gpiochip_get_desc() to fetch a GPIO descriptor from
   a specific offset on a certain chip inside driver
   code.
 
 - Switch ACPI GPIO code over to using
   gpiochip_get_desc() and get rid of gpio_to_desc().
 
 - The ACPI GPIO event handling code has been reworked
   after encountering an actual real life implementation.
 
 - Support for ACPI GPIO operation regions.
 
 - Generic GPIO chips can now be assigned labels/names
   from platform data.
 
 - We now clamp values returned from GPIO drivers to
   the boolean [0,1] range.
 
 - Some improved documentation on how to use the polarity
   flag was added.
 
 - The a large slew of incremental driver updates and
   non-critical fixes. Some targeted for stable.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJTPQnkAAoJEEEQszewGV1zyf4P/AmXV0O/FoyeQnXDxDsp7V/t
 JpfD0Gy8FlFmRxjG+UYutRCWUHxFQJU+j0ToVC4/N8clNS1LwA+ZwhNgB8dqRokz
 JVeeqUPn95z2kGe3j9DgVXWMRAytq7y8fXFuNUN36losceuxyOj4mYKLP9Yjnp9l
 4pS1TtQHF95a7qmnyYjGZy8VNcUz1gJ7wJrGxKI+Kl/8pcdA6rPqom6ozCXpZjaD
 5GGQoSvXKIn44+8qZeJsebd1YEso/8K66e9JomcGEsuZl78ArDOzoSllpYF2h/RM
 bo4BFUmoOL3/jVp7FFVbybfolwuRmQesY4NFqx03e+y++hxHFHl90FT+mnednS2Q
 k4lB0o1YRjf2tfMmm4cJ3tVBnFRhssTVb9ynDbzUw61mNVEuxP90f/njrHlObnPT
 1uVVWUE+4ojral213S2IYGHkg1OlWSn0DP6tEaswjOsGJrMdXpdxS5RPwcRtcByT
 HufZRNbUbLzXBzf4WeV2foSS3XqbXYcuMfdRBSWrbuJqW56robbdKKyvrMRPvh7j
 FV7SEK0yFPRe3nuzKM+t9TDGdUt4qivv/YfVeGfCnTVgFOac6cKrHG9gzM58mVcb
 4czG3B1TbqgfGVeZuew4qUdlHSmnSsS+pf/h9Yh9QCHqaKGh3R17cSDxIKAIVTIW
 pH6nuShTXsbrmRMeMhux
 =8Qqf
 -----END PGP SIGNATURE-----

Merge tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull bulk of gpio updates from Linus Walleij:
 "A pretty big chunk of changes this time, but it has all been on
  rotation in linux-next and had some testing.  Of course there will be
  some amount of fixes on top...

   - Merged in a branch of irqchip changes from Thomas Gleixner: we need
     to have new callbacks from the irqchip to determine if the GPIO
     line will be eligible for IRQs, and this callback must be able to
     say "no".  After some thinking I got the branch from tglx and have
     switched all current users over to use this.

   - Based on tglx patches, we have added some generic irqchip helpers
     in the gpiolib core.  These will help centralize code when GPIO
     drivers have simple chained/cascaded IRQs.  Drivers will still
     define their irqchip vtables, but the gpiolib core will take care
     of irqdomain set-up, mapping from local offsets to Linux irqs, and
     reserve resources by marking the GPIO lines for IRQs.

   - Initially the PL061 and Nomadik GPIO/pin control drivers have been
     switched over to use the new gpiochip-to-irqchip infrastructure
     with more drivers expected for the next kernel cycle.  The
     factoring of just two drivers still makes it worth it so it is
     already a win.

   - A new driver for the Synopsys DesignWare APB GPIO block.

   - Modify the DaVinci GPIO driver to be reusable also for the new TI
     Keystone architecture.

   - A new driver for the LSI ZEVIO SoCs.

   - Delete the obsolte tnetv107x driver.

   - Some incremental work on GPIO descriptors: have
     gpiod_direction_output() use a logical level, respecting assertion
     polarity through ACTIVE_LOW flags, adding gpiod_direction_output_raw()
     for the case where you want to set that very value.  Add
     gpiochip_get_desc() to fetch a GPIO descriptor from a specific
     offset on a certain chip inside driver code.

   - Switch ACPI GPIO code over to using gpiochip_get_desc() and get rid
     of gpio_to_desc().

   - The ACPI GPIO event handling code has been reworked after
     encountering an actual real life implementation.

   - Support for ACPI GPIO operation regions.

   - Generic GPIO chips can now be assigned labels/names from platform
     data.

   - We now clamp values returned from GPIO drivers to the boolean [0,1]
     range.

   - Some improved documentation on how to use the polarity flag was
     added.

   - a large slew of incremental driver updates and non-critical fixes.
     Some targeted for stable"

* tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (80 commits)
  gpio: rcar: Add helper variable dev = &pdev->dev
  gpio-lynxpoint: force gpio_get() to return "1" and "0" only
  gpio: unmap gpio irqs properly
  pch_gpio: set value before enabling output direction
  gpio: moxart: Actually set output state in moxart_gpio_direction_output()
  gpio: moxart: Avoid forward declaration
  gpio: mxs: Allow for recursive enable_irq_wake() call
  gpio: samsung: Add missing "break" statement
  gpio: twl4030: Remove redundant assignment
  gpio: dwapb: correct gpio-cells in binding document
  gpio: iop: fix devm_ioremap_resource() return value checking
  pinctrl: coh901: convert driver to use gpiolib irqchip
  pinctrl: nomadik: convert driver to use gpiolib irqchip
  gpio: pl061: convert driver to use gpiolib irqchip
  gpio: add IRQ chip helpers in gpiolib
  pinctrl: nomadik: factor in platform data container
  pinctrl: nomadik: rename secondary to latent
  gpio: Driver for SYSCON-based GPIOs
  gpio: generic: Use platform_device_id->driver_data field for driver flags
  pinctrl: coh901: move irq line locking to resource callbacks
  ...
2014-04-03 16:44:15 -07:00
Linus Torvalds d64b393253 Pin control bulk changes for the v3.15 series, no new core
functionality this time, just incremental driver updates:
 
 - A large refactoring of the MVEBU (Marvell) driver.
 
 - A large refactoring of the Tegra (nVidia) driver.
 
 - GPIO interrupt including soft edges support in the
   STi driver.
 
 - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
   pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung),
   sunxi (AllWinner), i.MX (Freescale), Baytrail.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJTORWVAAoJEEEQszewGV1zkCgP/3CxgHSqwAN5ps1IxRhOThgQ
 UClm2EETW9hca7okOdCLgngEYJEtetQ0atAW9yJS6bwK9KP3zhQXVXFBS9ecO3Z4
 U8U6UuKWiBLxZjmaPS6NvSxAY61Co60aoTow67zxrVhnwF/a8Cl7E4y+jD/Q/bmk
 +NM5B9puRYO2kPhjfr9VwIsQamjyCN8uXXI1r5YSR/ti1IbX78DDlz4+fyBfYX5f
 h95B8+kfDzygHIHpuLs3zJiRnKw/Q5G/PbDHyA2TgpL2Z8/Lyv6hvMWZ1O1qFOXi
 SDkyCv0ocXgVlYn6CT7k9s6/q2TVmD7hjiiLHAYebZcBg3NbF3/ApUYzNTAdp7eu
 FuuBPk4wCCvwxs0PFKNWQHzlCvr0WEbZNmUmKFzUOKoZMsl//lsm0l5v0IYJBs1w
 iB/ruetNVLlq9jhMCcmgesSn5JRxOW9jhU/N2VIMSu/L8nIFeTbok8iL3abTEglg
 gE1odnZf6lDsrcuq7VkGq6xXbevxz/pJVG604Y2vNvqvdDbQA9e1F9X+Ggh1gZTb
 Fnb0B7D42LlT5SDSzsxMciOvVAZ5PzRnsDvjIqEs+xp22IiLHQ+fK09AO76DgVy9
 oxb897mc2Oa3BbjJBE/Dkk2QjGlq0vHNf7Mm3W+nerGS5o0C78x7KwEWH7/X5ICd
 szzkXNdY7V8DMMzrsDOe
 =i7Sq
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control bulk changes from Linus Walleij:
 "Pin control bulk changes for the v3.15 series, no new core
  functionality this time, just incremental driver updates:

   - A large refactoring of the MVEBU (Marvell) driver.

   - A large refactoring of the Tegra (nVidia) driver.

   - GPIO interrupt including soft edges support in the STi driver.

   - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
     pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi
     (AllWinner), i.MX (Freescale), Baytrail"

* tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: tegra: add some missing Tegra114 entries
  pinctrl: tegra: fix some mistakes in Tegra124
  pinctrl: msm: fix up out-of-order merge conflict
  pinctrl: st: Fix error check for of_irq_to_resource usage
  pinctrl: tegra: consistency cleanup
  pinctrl: tegra: dynamically calculate function list of groups
  pinctrl: tegra: init Tegra20/30 at module_init time
  pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays
  pinctrl: st: add pinctrl support for the STiH407 SoC
  pinctrl: st: Enhance the controller to manage unavailable registers
  pinctrl: msm: Simplify msm_config_reg() and callers
  pinctrl: msm: Remove impossible WARN_ON()s
  pinctrl: msm: Replace lookup tables with math
  pinctrl: msm: Drop OF_IRQ dependency
  pinctrl: msm: Drop unused includes
  pinctrl: msm: Check for ngpios > MAX_NR_GPIO
  pinctrl: msm: Silence recursive lockdep warning
  pinctrl: mvebu: silence WARN to dev_warn
  pinctrl: msm: drop wake_irqs bitmap
  pinctrl-baytrail: add function mux checking in gpio pin request
  ...
2014-04-01 13:10:49 -07:00
Linus Walleij 523dcce72c pinctrl: coh901: convert driver to use gpiolib irqchip
This converts the COH901 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-26 10:31:34 +01:00
Linus Walleij e0bc34a3da pinctrl: nomadik: convert driver to use gpiolib irqchip
This converts the Nomadik pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-26 10:31:33 +01:00
Linus Walleij 8f18bcfcd2 pinctrl: nomadik: factor in platform data container
The old platform data struct is just a leftover from the times
when the driver was not probed exclusively from the device tree.
Factor this into the general state container and simplify the
probe path.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-25 09:57:07 +01:00
Linus Walleij 194e15ba00 pinctrl: nomadik: rename secondary to latent
The "secondary irq" in the nomadik pin control driver is actually
not secondary (as in: can occur any time alongside the ordinary
irq), it is a latent IRQ. It is an IRQ that has occurred when
the system was in sleep state and has been cached in a special
register flagged from the low power management unit (PRCM).

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-25 09:57:01 +01:00
Linus Walleij 8c1d50a6a7 pinctrl: coh901: move irq line locking to resource callbacks
This switches the COH901 GPIO driver over to using the
.request_resources() and .release_resources() callbacks from
the irqchip vtable and separate the calls from the .enable()
and .disable() callbacks as the latter cannot really say no
to a request, whereas the resource callbacks can.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-18 09:28:30 +01:00
Linus Walleij 57ef04288a gpio: switch drivers to use new callback
This switches all GPIO and pin control drivers with irqchips
that were using .startup() and .shutdown() callbacks to lock
GPIO lines for IRQ usage over to using the .request_resources()
and .release_resources() callbacks just introduced into the
irqchip vtable.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-18 09:28:30 +01:00
Stephen Warren 43f23a0660 pinctrl: tegra: add some missing Tegra114 entries
Add some missing pin and drive group definitions to the driver. These
are all defined in the TRM, but missing from the driver for some reason.

Fix a couple of mistakes in the drive group definitions.

Much of the diff to tegra114_groups[] is an indentation change due to one
of the new group names being long. git diff/show -w will highlight this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-14 16:32:36 +01:00
Stephen Warren 0ffdd4b61b pinctrl: tegra: fix some mistakes in Tegra124
A couple of pairs of pin group names were swapped in the table. This
caused the wrong register to be programmed. Luckily, this had little
effect, if any, since the swapped pins were likely to be programmed
identically.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-14 16:32:36 +01:00
Linus Walleij 17cdc926ec pinctrl: msm: fix up out-of-order merge conflict
Commit 051a58b462
"pinctrl: msm: Simplify msm_config_reg() and callers"
removed the local "reg" variable in the msm_config_reg()
function, but the earlier
commit ed118a5fd9
"pinctrl-msm: Support output-{high,low} configuration"
introduced a new switchclause using it.

Fix this up by removing the offending register assignment.

Reported-by: Kbuild test robot <fengguang.wu@intel.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-14 16:32:23 +01:00
Srinivas Kandagatla bcca9220b2 pinctrl: st: Fix error check for of_irq_to_resource usage
This patch fixes an error check while using of_irq_to_resource.
of_irq_to_resource returns non-zero interrupt number on success and zero
on error. The driver was using error check is wrong way.

Without this patch the driver will configure interrupt zero if there is
no interrupt specified in the node.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:53:44 +01:00
Stephen Warren 93cfb2d862 pinctrl: tegra: consistency cleanup
Fix Tegra30/114/124 pinmux drivers consistency issues.
* Sort all lists of the same object type (e.g. #defines for pins, and
  the array that defines their names) in the same order.
* Whitespace fixes.
* Consistency in layout between the 3 drivers.

These driver files were also auto-generated, which should allow us to
make e.g. the U-Boot drivers completely consistent with the kernel in
the future:-)

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:27:33 +01:00
Stephen Warren ce43625466 pinctrl: tegra: dynamically calculate function list of groups
The per-SoC data structures for Tegra pinctrl stored some information
in a redundant way. Specifically, the list of groups that each function
could be muxed onto was stored once explicitly, and also as part of the
definition of each group. Eliminate this redundancy, and calculate each
function's list of valid groups at pinctrl probe time. This removes
thousands of lines of code from the pinctrl driver and ~16K from the
vmlinux binary size, and adds only about 500uS to the boot process (on
Tegra30; newer SoCs will likely be faster still).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:23:41 +01:00
Stephen Warren edfab368c8 pinctrl: tegra: init Tegra20/30 at module_init time
The Tegra20/30 pinctrl drivers currently initializes at arch_initcall,
whereas Tegra114/124 pinctrl drivers initialize at module_init time.
Convert Tegra20/30 to work the same way as the other drivers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:22:29 +01:00
Maxime COQUELIN 88430acf38 pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays
This patch replaces the raw values with ARRAY_SIZE for assigning the
ninput_delays and noutput_delays fields of STiH416's st_pctl_data struct.

Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:18:24 +01:00
Giuseppe Cavallaro 7ce717db38 pinctrl: st: add pinctrl support for the STiH407 SoC
This patch adds the initial support for pinctrl based on H407 SoC.

Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:17:07 +01:00
Giuseppe Cavallaro 4e6a609fb7 pinctrl: st: Enhance the controller to manage unavailable registers
This patch adds a new logic inside the st pinctrl to manage
an unsupported scenario: some sysconfig are not available!

This is the case of STiH407 where, although documented, the
following registers from SYSCFG_FLASH have been removed from the SoC.

SYSTEM_CONFIG3040
   Output Enable pad control for all PIO Alternate Functions
and
SYSTEM_ CONFIG3050
   Pull Up pad control for all PIO Alternate Functions

Without managing this condition an imprecise external abort
will be detect.

To do this the patch also reviews the st_parse_syscfgs
and other routines to manipulate the registers only if
actually available.
In any case, for example the st_parse_syscfgs detected
an error condition but no action was made in the
st_pctl_probe_dt.

Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:15:34 +01:00
Stephen Boyd 051a58b462 pinctrl: msm: Simplify msm_config_reg() and callers
We don't need to check for a negative reg here because reg is
always the same and is always non-negative. Also, collapse the
switch statement down for the duplicate cases.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:29 +01:00
Stephen Boyd 1a0840ae03 pinctrl: msm: Remove impossible WARN_ON()s
All these functions are limited in what they can pass as the gpio
or irq number to whatever is setup during probe. Remove the
checks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:28 +01:00
Stephen Boyd 7cc34e2e1a pinctrl: msm: Replace lookup tables with math
We don't need to waste space with these lookup tables, just do
the math directly.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:28 +01:00
Stephen Boyd 5f2449d022 pinctrl: msm: Drop OF_IRQ dependency
This driver doesn't rely on any functionality living in
drivers/of/irq.c to compile. Drop this dependency.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:27 +01:00
Stephen Boyd af3e18f13d pinctrl: msm: Drop unused includes
These includes are unused or can be handled via forward
declarations. Remove them.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:27 +01:00
Stephen Boyd dcd278b860 pinctrl: msm: Check for ngpios > MAX_NR_GPIO
Fail the probe and print a warning if SoC specific drivers have
more GPIOs than there can be accounted for in the static bitmaps.
This should avoid silent corruption/failures in the future.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:27 +01:00
Stephen Boyd 3525f5556a pinctrl: msm: Silence recursive lockdep warning
If a driver calls enable_irq_wake() on a gpio turned interrupt
from the msm pinctrl driver we'll get a lockdep warning like so:

=============================================
[ INFO: possible recursive locking detected ]
3.14.0-rc3 #2 Not tainted
---------------------------------------------
modprobe/52 is trying to acquire lock:
 (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88

but task is already holding lock:
 (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88

other info that might help us debug this:
 Possible unsafe locking scenario:

       CPU0
       ----
  lock(&irq_desc_lock_class);
  lock(&irq_desc_lock_class);

 *** DEADLOCK ***

 May be due to missing lock nesting notation

4 locks held by modprobe/52:
 #0:  (&__lockdep_no_validate__){......}, at: [<c04f2864>] __driver_attach+0x48/0x98
 #1:  (&__lockdep_no_validate__){......}, at: [<c04f2874>] __driver_attach+0x58/0x98
 #2:  (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88
 #3:  (&(&pctrl->lock)->rlock){......}, at: [<c04bb4b8>] msm_gpio_irq_set_wake+0x20/0xa8

Silence it by putting the gpios into their own lock class.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:19 +01:00
Sebastian Hesselbarth 3c7d563789 pinctrl: mvebu: silence WARN to dev_warn
Pinctrl will WARN on missing DT resources, which is a little bit too
noisy. Use dev_warn with FW_BUG instead.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:00:04 +01:00
Josh Cartwright 6aced33f49 pinctrl: msm: drop wake_irqs bitmap
Currently, the wake_irqs bitmap is used to track whether there are any
gpio's which are configured as wake irqs, and uses this to determine
whether or not to call enable_irq_wake()/disable_irq_wake() on the
summary interrupt.

However, the genirq core already handles this case, by maintaining a
'wake_count' per irq_desc, and only calling into the controlling
irq_chip when wake_count transitions 0 <-> 1.

Drop this bitmap, and unconditionally call irq_set_irq_wake() on the
summary interrupt.

Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 14:54:28 +01:00
Chew, Kean Ho 42bd00706c pinctrl-baytrail: add function mux checking in gpio pin request
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup pin, I/O interfaces for LPSS, etc.

Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Darren Hart <dvhart@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-11 11:22:54 +01:00
Stephen Warren a76cbd7eba pinctrl: tegra: fix some typos and inconsistencies
drive_dev3_pins in pinctrl-tegra114.c wasn't used; delete it.

pinctrl-tegra124.c had quite a few typos. Fix those.

pinctrl-tegra124.c had a few mismatches between the *_groups[] ararys
and the function lists in tegra124_groups[]. Fix those.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-11 11:16:28 +01:00
Linus Torvalds 79e615420c ARM: SoC fixes for 3.14-rc
A collection of fixes for ARM platforms. A little large due to us missing to
 do one last week, but there's nothing in particular here that is in itself
 large and scary.
 
 Mostly a handful of smaller fixes all over the place. The majority is made
 up of fixes for OMAP, but there are a few for others as well. In particular,
 there was a decision to rename a binding for the Broadcom pinctrl block that
 we need to go in before the final release since we then treat it as ABI.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJTHKFOAAoJEIwa5zzehBx36EoP/0K7ts9qrShYUD2ASy9HuFKj
 cUcIHF+c0203bavIZzP5EQW/m7TGSybjO8UwkOaLv5SL6E9fn8rR01mmKpONeZbN
 E40ANvOxP3FdWWUFzZSh4oyaX0abaPUtPaYBavakHQI2Ej2m4UmpXAWUkCUGt9Om
 sXSAYuOi6tmpy40aimpaI1QBtx/eyxxJgEBKcbFBvhp1P3d56LTtoqmzACxBFU/8
 4NJIXuZlXTmXV9qIX+y4yXDhmVb6c/gEbNeLJ2F3yWzEeTgnMeycDb8o27Jl6Ii4
 rjsT25qplW5zvUODuhU6QUjuipPh8+WtyF8ruKMakxMNkVoGAC2flWw2TBR09tVj
 zIqYP7/vDhCEYcw4g/BqR8tEvojWt2m7Hm5y+oQY3qmCtLewL6TYeXZcXWFLCwSk
 m4zSvzZOsRsZWsZcflJKZr3g5vsjbg3vtoc3pOZaN4UcqEhU1HCtMfN3znnXIhtj
 xGWqN22S3OpGM0lzLY95lnVeLdrs6eX/ZY23BG1OV4OcDWM4nYwAxEq94QgPvSxR
 9E/fFhU2DZIulEA5Z+/PIReUCLuNL709zqnyAG9VTvbeC24sdr0W6bEM08O85xan
 kb7sbYRnt4qr4uOhPCi7wIENY4rrS91dcE3XZUhJtLWi/0jj+pHT9VoggyS4QdtS
 aWRhg70S5M6quMEoIOzg
 =YBim
 -----END PGP SIGNATURE-----

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from from Olof Johansson:
 "A collection of fixes for ARM platforms.  A little large due to us
  missing to do one last week, but there's nothing in particular here
  that is in itself large and scary.

  Mostly a handful of smaller fixes all over the place.  The majority is
  made up of fixes for OMAP, but there are a few for others as well.  In
  particular, there was a decision to rename a binding for the Broadcom
  pinctrl block that we need to go in before the final release since we
  then treat it as ABI"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: omap3-gta04: Add ti,omap36xx to compatible property to avoid problems with booting
  ARM: tegra: add LED options back into tegra_defconfig
  ARM: dts: omap3-igep: fix boot fail due wrong compatible match
  ARM: OMAP3: Fix pinctrl interrupts for core2
  pinctrl: Rename Broadcom Capri pinctrl binding
  pinctrl: refer to updated dt binding string.
  Update dtsi with new pinctrl compatible string
  ARM: OMAP: Kill warning in CPUIDLE code with !CONFIG_SMP
  ARM: OMAP2+: Add support for thumb mode on DT booted N900
  ARM: OMAP2+: clock: fix clkoutx2 with CLK_SET_RATE_PARENT
  ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4
  ARM: DRA7: hwmod data: correct the sysc data for spinlock
  ARM: OMAP5: PRM: Fix reboot handling
  ARM: sunxi: dt: Change the touchscreen compatibles
  ARM: sun7i: dt: Fix interrupt trigger types
2014-03-09 19:27:31 -07:00
Barry Song e291fd20ef pinctrl: sirf: fix kernel panic in gpio_lock_as_irq
commit 655dada627 causes kernel panic, this patch fixes it.

    [    1.197816] [ffffffee] *pgd=0d7fd821, *pte=00000000, *ppte=00000000
    [    1.204070] Internal error: Oops: 17 [#1] PREEMPT SMP ARM
    [    1.209447] Modules linked in:
    [    1.212490] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.0-rc1 #3
    [    1.218737] task: cd03c000 ti: cd040000 task.ti: cd040000
    [    1.224127] PC is at gpiod_lock_as_irq+0xc/0x64
    [    1.228634] LR is at sirfsoc_gpio_irq_startup+0x18/0x44
    [    1.233842] pc : [<c01d3990>]    lr : [<c01d1c38>]    psr: a0000193
    [    1.233842] sp : cd041d30  ip : 00000000  fp : 00000000
    [    1.245296] r10: 00000000  r9 : cd023db4  r8 : 60000113
    [    1.250505] r7 : 0000003e  r6 : cd023dd4  r5 : c06bfa54  r4 : cd023d80
    [    1.257014] r3 : 00000020  r2 : 00000000  r1 : ffffffea  r0 : ffffffea
    [    1.263526] Flags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
    [    1.270903] Control: 10c53c7d  Table: 00004059  DAC: 00000015
    [    1.276631] Process swapper/0 (pid: 1, stack limit = 0xcd040240)
    [    1.282620] Stack: (0xcd041d30 to 0xcd042000)
    [    1.286963] 1d20:                                     cd023d80 c01d1c38 c01d1c20 cd023d80
    [    1.295124] 1d40: 00000001 c0068438 cd023d80 ccb6d880 cd023dd4 c0067044 0000718e c006719c
    [    1.286963] 1d20:                                     cd023d80 c01d1c38 c01d1c20 cd023d80
    [    1.295124] 1d40: 00000001 c0068438 cd023d80 ccb6d880 cd023dd4 c0067044 0000718e c006719c
    [    1.295124] 1d40: 00000001 c0068438 cd023d80 ccb6d880 cd023dd4 c0067044 0000718e c006719c
    [    1.303283] 1d60: 00000800 00000083 ccb6d880 cd023d80 c02b41d8 00000083 0000003e ccb7c410
    [    1.311442] 1d80: 00000000 c00671dc 00000083 0000003e c02b41d8 cd3dd5c0 0000003e ccb7c634
    [    1.319601] 1da0: cd040030 c00672a8 cd3dd5c0 ccb7c410 ccb6d340 ccb7c410 ccb6d340 cd3dd400
    [    1.327760] 1dc0: cd3dd410 c02b4434 ccb7c410 c01265a8 00000001 cd3dd410 c0687108 00000000
    [    1.335919] 1de0: c0687108 00000000 00000000 c0240170 c0240158 cd3dd410 c06c30d0 c023e8bc
    [    1.344079] 1e00: c023e9d4 00000000 cd3dd410 c023e9d4 c0682150 c023cf88 cd003e98 cd2d50c4
    [    1.352238] 1e20: cd3dd410 cd3dd444 c06822f0 c023e768 cd3dd418 cd3dd410 c06822f0 c023de14
    [    1.360397] 1e40: cd3dd418 00000000 cd3dd410 c023c398 cd041e78 cd041ea8 cd3dd400 cd3dd410
    [    1.368556] 1e60: 00000083 00000000 cd3dd400 cd3dd410 00000083 000000c8 c04e00c8 c023fee8
    [    1.376715] 1e80: 00000000 cd041ea8 cd3dd400 00000001 00000083 c024048c c0435ef8 c0434dec
    [    1.384874] 1ea0: c068da58 c04c6d04 c0682150 c0435ef8 ffffffff 00000000 00000000 c068da58
    [    1.393033] 1ec0: 00000020 00000000 00000000 00000000 c05dabb8 00000007 c068d640 c068d640
    [    1.401193] 1ee0: c04c247c c04c249c 00000000 c00088e8 cd004c00 c043bbb8 cd029180 c03812a0
    [    1.409352] 1f00: 00000000 00000000 60000113 c0673728 60000113 c0673728 00000000 00000000
    [    1.417511] 1f20: cd7fce01 c0390a54 00000065 c003a81c c049e8bc 00000007 cd7fce0e 00000007
    [    1.425670] 1f40: 00000000 c05dabb8 00000007 c068d640 c068d640 c04c050c c04e00c8 00000065
    [    1.433829] 1f60: c04e00c0 c04c0c54 00000007 00000007 c04c050c c037d8fc cd03c000 c004322c
    [    1.441988] 1f80: c0662b40 0000d640 c03737c0 00000000 00000000 00000000 00000000 00000000
    [    1.450147] 1fa0: 00000000 c03737cc 00000000 c000e478 00000000 00000000 00000000 00000000
    [    1.458307] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
    [    1.466467] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 0002d481 05014092
    [    1.474640] [<c01d3990>] (gpiod_lock_as_irq) from [<c01d1c38>] (sirfsoc_gpio_irq_startup+0x18/0x44)
    [    1.483661] [<c01d1c38>] (sirfsoc_gpio_irq_startup) from [<c0068438>] (irq_startup+0x34/0x6c)
    [    1.492163] [<c0068438>] (irq_startup) from [<c0067044>] (__setup_irq+0x450/0x4b8)
    [    1.499714] [<c0067044>] (__setup_irq) from [<c00671dc>] (request_threaded_irq+0xa8/0x128)
    [    1.507960] [<c00671dc>] (request_threaded_irq) from [<c00672a8>] (request_any_context_irq+0x4c/0x7c)
    [    1.517164] [<c00672a8>] (request_any_context_irq) from [<c02b4434>] (gpio_extcon_probe+0x144/0x1d4)
    [    1.526279] [<c02b4434>] (gpio_extcon_probe) from [<c0240170>] (platform_drv_probe+0x18/0x48)
    [    1.534783] [<c0240170>] (platform_drv_probe) from [<c023e8bc>] (driver_probe_device+0x120/0x238)
    [    1.543641] [<c023e8bc>] (driver_probe_device) from [<c023cf88>] (bus_for_each_drv+0x58/0x8c)
    [    1.552143] [<c023cf88>] (bus_for_each_drv) from [<c023e768>] (device_attach+0x74/0x88)
    [    1.560126] [<c023e768>] (device_attach) from [<c023de14>] (bus_probe_device+0x84/0xa8)
    [    1.568113] [<c023de14>] (bus_probe_device) from [<c023c398>] (device_add+0x440/0x520)
    [    1.576012] [<c023c398>] (device_add) from [<c023fee8>] (platform_device_add+0xb4/0x214)
    [    1.584084] [<c023fee8>] (platform_device_add) from [<c024048c>] (platform_device_register_full+0xb8/0xdc)
    [    1.593719] [<c024048c>] (platform_device_register_full) from [<c04c6d04>] (sirfsoc_init_late+0xec/0xf4)
    [    1.603185] [<c04c6d04>] (sirfsoc_init_late) from [<c04c249c>] (init_machine_late+0x20/0x28)
    [    1.611603] [<c04c249c>] (init_machine_late) from [<c00088e8>] (do_one_initcall+0xf8/0x144)
    [    1.619934] [<c00088e8>] (do_one_initcall) from [<c04c0c54>] (kernel_init_freeable+0x13c/0x1dc)
    [    1.628620] [<c04c0c54>] (kernel_init_freeable) from [<c03737cc>] (kernel_init+0xc/0x118)

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 17:11:47 +08:00
Magnus Damm b5973fcd76 pinctrl: sh-pfc: r8a7791: SD1_CLK fix
Fix the SD1_CLK handling for r8a7791. Without this patch
it is impossible to request all pins needed for SDHI1 on
the Koelsch board.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:57:47 +08:00
Josh Cartwright 5ba341604a pinctrl: msm: make PINCTRL_MSM bool instead of tristate
Modular builds of pinctrl-msm break due to handle_bad_irq being
unexported for module use.  For now, make PINCTRL_MSM 'bool'.

Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:57:47 +08:00
Hans de Goede ef5aff05f1 pinctrl: sunxi: Fix interrupt register offset calculation
This fixing setting the interrupt type for eints >= 8.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:57:42 +08:00
Hans de Goede d82f94013a pinctrl: sunxi: Fix masking when setting irq type
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:57:36 +08:00
Chen-Yu Tsai 905a5117e7 pinctrl: sunxi: use chained_irq_{enter, exit} for GIC compatibility
On tha Allwinner A20 SoC, the external interrupts on the pin controller
device are connected to the GIC. Without chained_irq_{enter, exit},
external GPIO interrupts, such as used by mmc core card detect, cause
the system to hang.

This issue was first encountered during my attempt to get out-of-band
interrupts for WiFi on the Cubietruck working. With David's new series
of sunci-mci using mmc slot-gpio for (GPIO interrupt based) card
detection, removing the SD card also causes my Cubietruck to hang. This
problem should extend to all Allwinner A20 based boards.

With this fix, the system no longer hangs when I remove or insert the
SD card. /proc/interrupts show that the interrupt has correctly fired.
However the system still does not detect card removal/insertion. I
believe this is another unrelated issue.

Cc: stable@vger.kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:57:10 +08:00
Geert Uytterhoeven e6fae2d03d pinctrl: sh-pfc: r8a7791: Add alternative MSIOF pin groups
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:53:49 +08:00
Geert Uytterhoeven 7033168da5 pinctrl: sh-pfc: r8a7790: Add alternative MSIOF pin groups
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05 09:15:30 +08:00
Linus Walleij a9ea2ed45a Merge branch 'pinctrl-mvebu' into devel 2014-03-03 13:40:22 +08:00
Jason Cooper 7cab36e5ee Sign for-mvebu/pinctrl-3xx
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJTDOcOAAoJEN2kpao7fSL46REP/2EX8ls2mLvOH8XUd9kC8GHS
 qDfsiAwrb84t1PzL3DkWX2eZXbBLZBWI5m0xTcvvnAuEKD/EuMFY13AyqF3fGZYk
 ixMJ0JyQ1ML73boLTdCE4xaS18tRdI7UKi3T1d+K2293oskpkCX+84JYBkMbyr5K
 ShLHDn0EEWMxPOH/PJcle5QM6taB8/vwrQPsTfAJjRoA/1yIJ5o+g8RkfhgGdJuL
 nend3dInAKDHLvjf/Up19j6tjJsaDEILDqVVpN55fhj6+d3yd0dpWg2nh3w/TCPe
 tVXppKIua6vm3t5INN8p55d2yOuSjD7/NR/Dc8sIGOnc99yLaBlilkDnagH19gc8
 PhHd3b3k/clEo2zEF/xy1DqvxS4t5Xd5p2D3lBlA0PCCDdQTbwkMXPdll0TNHV0Y
 AHPGv7VQYLkn1/iMo3UkgGAQOfdaL81NQNkULDlGxjfllX7cjNgePKIf1lCi6pI4
 SYaiqRUNg+5cln3gFfdXc/vcMBF7CLVETFFPK3cmQncdm36LMRE04PKB9hxT2taB
 zdmE3iNRVGsPQEwsDxTnrRU7zbaPCQVjTd4ctqW3SBn/4J9mIhjgEEKWfLFVFbvJ
 4A7UDCWSkRhQHB6pnf0Gvkt2j1PaDUWl0U8PMptwrRqF8JqmQnJ3Me3a1Fun5oV5
 bkRIixitLBfPY5QARgd7
 =BnOr
 -----END PGP SIGNATURE-----

Merge tag 'tags/for-mvebu-pinctrl-3xx' into mvebu/pinctrl

Sign for-mvebu/pinctrl-3xx
2014-03-01 07:03:52 +00:00
Sebastian Hesselbarth 6da67cab4b pinctrl: mvebu: dove: use global register regmap
Now that we have a regmap for global registers, get rid of the last
remaining hardcoded physical addresses. While at it, also remove
DOVE_ prefix from those macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:18 +01:00
Sebastian Hesselbarth 18e6f28e9c pinctrl: mvebu: dove: use remapped pmu_mpp registers
Now that we have ioremapped pmu_mpp registers, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:16 +01:00
Sebastian Hesselbarth 2c4b229baf pinctrl: mvebu: dove: use remapped mpp4 register
Now that we have an ioremapped mpp4 register, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:14 +01:00
Sebastian Hesselbarth 00202b013e pinctrl: mvebu: dove: use remapped mpp base registers
Now that we have ioremapped mpp base registers, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:12 +01:00
Sebastian Hesselbarth e91f7916ea pinctrl: mvebu: dove: request syscon regmap for global registers
Dove pinctrl uses some global config registers to control pins.
This patch requests a syscon regmap for those registers. As this
changes DT to driver requirements, fallback to a self-registered
regmap with hardcoded resources, if the corresponding syscon DT
node is missing. Also, WARN about old DT binding usage to encourage
users to update their DTBs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:09 +01:00
Sebastian Hesselbarth 4d73fc7728 pinctrl: mvebu: dove: request additional resources
Dove pinctrl also requires additional registers to control all pins.
This patch requests resources for mpp4 and pmu-mpp register ranges.
As this changes DT to driver requirements, fallback to hardcoded
resources, if the corresponding DT regs have not been set.
Also, WARN about old DT binding usage to encourage users to update
their DTBs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 21:16:08 +01:00
Thomas Petazzoni ca6d9a084b pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385
The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:51:05 +01:00
Thomas Petazzoni ce3ed59dcd pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375
The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2014-02-25 18:51:01 +01:00
Sebastian Hesselbarth 78c2c3d3da pinctrl: mvebu: dove: reuse mpp_{set,get} in pmu callbacks
Dove has pins that can be switched between normal and pmu functions.
Rework pmu_mpp callbacks to reuse default mpp ctrl helpers.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:38:41 +01:00
Sebastian Hesselbarth c2f082fe97 pinctrl: mvebu: dove: consolidate auto-numbered pmu mpp ranges
Passing a NULL name for pin ranges will auto-generate standard names
for each pin. With common pinctrl driver now checking NULL name correctly,
consolidate mpp pins 0-15.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:38:37 +01:00
Thomas Petazzoni cffa7a6b10 pinctrl: mvebu: remove MPP_REG_CTRL macro
Now that each per-SoC pinctrl driver must implement its own get/set
functions, there is no point in keeping the MPP_REG_CTRL macro, whose
purpose was to let the core pinctrl mvebu driver use default get/set
functions. While at it also update the comment about mvebu_mpp_ctrl.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:38:31 +01:00
Sebastian Hesselbarth faaa8325ad pinctrl: mvebu: remove common get/set functions
With every SoC always providing its own get/set callbacks, we can now
remove the generic ones, remove the obsolete base address, and always
use the provided callbacks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:38:24 +01:00
Sebastian Hesselbarth 1217b790ae pinctrl: mvebu: move resource allocation to SoC specific drivers
The way that mvebu pinctrl is designed, requesting mpp registers
in common pinctrl driver does not allow SoC specific drivers to
access this resource.

Move resource allocation in each SoC pinctrl driver and enable
already provided mpp_{set,get} callbacks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:37:53 +01:00
Sebastian Hesselbarth ad2a4f2b80 pinctrl: mvebu: armada-xp: provide generic mpp callbacks
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:35:41 +01:00
Sebastian Hesselbarth 877f01fc4d pinctrl: mvebu: armada-370: provide generic mpp callbacks
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:35:35 +01:00
Sebastian Hesselbarth 3a25f9f2f7 pinctrl: mvebu: kirkwood: provide generic mpp callbacks
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
2014-02-25 18:35:30 +01:00
Sebastian Hesselbarth 17bdec6770 pinctrl: mvebu: dove: provide generic mpp callbacks
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later. While at it, also make use of globally defined
MPP macros.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25 18:35:24 +01:00
Sebastian Hesselbarth f5b85e42d4 pinctrl: mvebu: add common mpp reg helper to mvebu pinctrl include
This adds some defines and helper functions for the common mpp reg
layout to mvebu pinctrl include.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
2014-02-25 18:35:16 +01:00
Sebastian Hesselbarth 2035d39da1 pinctrl: mvebu: remove passing mvebu_mpp_ctrl to callbacks
The only valuable information a special callback can derive from
mvebu_mpp_ctrl passed to it, is the pin id. Instead of passing
the struct, pass the pid directly.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:34:51 +01:00
Sebastian Hesselbarth e310b74544 pinctrl: mvebu: identify generic controls by name
We treat unnamed controls as generic mvebu mpp register controls but
we identify them by not being special controls. Flip the logic and
use the name pointer as identification instead. While at it, add some
comments explaining the not so obvious treatment.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:34:45 +01:00
Sebastian Hesselbarth dc2a90004e pinctrl: mvebu: remove obsolete per-control name buffer allocation
With the introduction of a global name buffer, we can now remove
the allocation and preparation of per-control name buffers.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:34:41 +01:00
Sebastian Hesselbarth 8d898fd596 pinctrl: mvebu: count unnamed controls and allocate name buffer
pinctrl-mvebu allows SoCs to pass unnamed controls that will get an
auto-generated name of "mpp<PIN#>". Currently, we are allocating name
buffers on a per-control basis while looping over passed controls.
This counts the total number of unnamed controls and allocates a
global name buffer instead. The new buffer is then used while assigning
controls to pinctrl groups later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25 18:34:34 +01:00
Wolfram Sang 6787141361 pinctrl: pfc: r8a7791: add mux data for IIC(B) cores
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:15 +01:00
Richard Genoud 8af584b868 pinctrl: at91: implement get_direction
This is needed for gpiod_get_direction().
Otherwise, it returns -EINVAL.

Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:15 +01:00
Martin Fuzzey 7c001e556e pinctrl: imx: Fix pin name in debug message.
The wrong index counter was being used, causing the debug message
to show an incorrect pin name.

Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:14 +01:00
Hans de Goede 885d662618 pinctrl-sunxi: Fix sun5i-a13 port F multiplexing
The correct value for selecting the mmc0 function on port F pins is 2 not 4,
as per the data-sheet:
http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:14 +01:00
Sonic Zhang e3653749aa pinctrl: pinctrl-adi: combine multiple groups of one function together
The data pins of some peripheral are different if connecting to different
devices in one pinmux function. In the PPI case, data pins can be used
in 8, 16 and 24 pin groups individually. Add these groups into one ppi
function.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:13 +01:00
Barry Song 019c12f474 pinctrl: sirf: update copyright years to 2014
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:13 +01:00
Ulf Hansson c003eed7a0 pinctrl: nomadik: Convert to modern pm_ops
Use the SIMPLE_DEV_PM_OPS macro and convert to the modern pm ops.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:12 +01:00
Ulf Hansson 131d85bc3a pinctrl: nomadik: Silence compiler warn for !CONFIG_PM
The static suspend/resume functions were not being used while
!CONFIG_PM. Fix it and convert to CONFIG_PM_SLEEP.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:12 +01:00
Geert Uytterhoeven 202909cdf1 pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:11 +01:00
Ivan T. Ivanov dc1791188b pinctrl-msm: Add SPI8 pin definitions
Add pin, group and function definitions for SPI#8
controller.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 10:49:11 +01:00
Christian Daudt d0deca0276 pinctrl: refer to updated dt binding string.
Bring the driver in line with the bcm-based dt name for pinctrl.
This is being done to keep consistency with other Broadcom mobile
SoC drivers.

Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
2014-02-24 20:25:54 -08:00
Mark Brown 5d88dceac7 pinctrl: Quiet logging about missing DT nodes when not using DT
On systems which were not booted using DT it is entirely unsurprising that
device nodes don't have any DT information and this is going to happen for
every single device in the system. Make pinctrl be less chatty about this
situation by only logging in the case where we have DT.

Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-24 10:44:54 +01:00
Magnus Damm 97e00faaf1 pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUS
Create a new group for the USB0 OVC/VBUS pin by itself. This
allows us to monitor PWEN as GPIO on the Lager board.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11 09:35:19 +01:00
Young-Gun Jang 9a8b607972 pinctrl: exynos: add exynos5260 SoC specific data
Adds pinctrl support for all platforms based on EXYNOS5260 SoC.

Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11 09:35:19 +01:00
Bjorn Andersson ed118a5fd9 pinctrl-msm: Support output-{high,low} configuration
Add support for configuring pins as output with value as from the
pinconf-generic interface.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11 09:35:18 +01:00
Rongjun Ying 58ffe7a025 pinctrl: sirf: add pin group for USP0 for atlas6
USP0 has multiple functions, and has RX and TX frame sync signals,
for some scenarios like audio PCM, we don't need both of them.
so here we add two possibilities for USP0 only holding one of TX
and RX frame sync.

commit 8385af02ba only added this group for prima2, and missed
atlas6. This patch fixes it.

Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Chao Xie 4bd7547756 pinctrl: single: add low power mode support
For some silicons, the pin configuration register can control
the output of the pin when the pad including the pin enter
low power mode.
For example, the pin can be "Drive 1", "Drive 0", "Float" when
the pad including the pin enter low power mode.
It is very useful when you want to control the power leakeage
when the SOC enter low power mode, and can save more power for
the low power mode.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Sonic Zhang b81e57e6ac pinctrl-adi2: fix coding style issue
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Sonic Zhang b4eef7b225 pinctrl-adi2: change irq_base from usigned int to int
Negative irq_base means this gpio port doens't support interrupts.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Sonic Zhang 1e6f8e3c92 pinctrl: Move pint PM storage structure out of blackfin architecture.
It is better to keep this structure in the pinctrl-adi2 driver.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Jean-Jacques Hiblot 94e692071a pinctrl: at91: use gpiolib API to mark a GPIO used as an IRQ
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:08 +01:00
Geert Uytterhoeven 2d0c386f13 pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)

Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-02-10 10:13:07 +01:00
Srinivas Kandagatla 155795b9d1 pinctrl: st: Add software edge trigger interrupt support
ST pin controller does not have hardware support for detecting edge
triggered interrupts, It only has level triggering support.
This patch attempts to fake up edge triggers from hw level trigger
support in software. With this facility now the gpios can be easily used
for keypads, otherwise it would be difficult for drivers like keypads to
work with level trigger interrupts.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:07 +01:00
Srinivas Kandagatla 727b0f71a5 pinctrl: st: Add Interrupt support
This patch add interrupt support to the pincontroller driver.

ST Pincontroller GPIO bank can have one of the two possible types of
interrupt-wirings.

First type is via irqmux, single interrupt is used by multiple gpio
banks. This reduces number of overall interrupts numbers required. All
these banks belong to a single pincontroller.
		  _________
		 |	   |----> [gpio-bank (n)    ]
		 |	   |----> [gpio-bank (n + 1)]
	[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
		 |	   |----> [gpio-bank (...  )]
		 |_________|----> [gpio-bank (n + 7)]

Second type has a dedicated interrupt per gpio bank.

	[irqN]----> [gpio-bank (n)]

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10 10:13:07 +01:00
Laxman Dewangan 5b232c5add pinctrl: tegra: return correct error type
When memory allocation failed, drive should return error as ENOMEM.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-06 14:21:19 +01:00
Florian Vaussard e7f2a44489 pinctrl: do not init debugfs entries for unimplemented functionalities
Commit c420619 "pinctrl: pinconf: remove checks on ops->pin_config_get"
removed the check on (ops != NULL) when performing pinconf_pins_show() or
pinconf_groups_show(). As these entries are always enabled, even if
pinconf is not supported, reading will result in an oops due to NULL
ops.

Instead of checking for ops, remove the corresponding debugfs entries if
pinconf and/or pinmux are not implemented.

Tested on OMAP3 (pinctrl-single).

Cc: stable@vger.kernel.org
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-06 13:48:17 +01:00
Stanislaw Gruszka 7b320cb1ed pinctrl: protect pinctrl_list add
We have few fedora bug reports about list corruption on pinctrl,
for example:
https://bugzilla.redhat.com/show_bug.cgi?id=1051918

Most likely corruption happen due lack of protection of pinctrl_list
when adding new nodes to it. Patch corrects that.

Fixes: 42fed7ba44 ("pinctrl: move subsystem mutex to pinctrl_dev struct")
Cc: stable@vger.kernel.org
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04 21:59:45 +01:00
Qipan Li fa74d0d3e3 pinctrl: sirf: correct the pin index of ac97_pins group
according to datasheet and ac97_muxmask assignment, ac97_pins should be
corrected.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-03 09:08:17 +01:00
Chris Ruehl e3365d0974 pinctrl: imx27: fix offset calculation in imx_read_2bit
The offset for the 2bit register calculate wrong, this patch
fixes the problem. The debugfs printout for oconf, iconfa, iconfb
now shows the real values.

Cc: stable@vger.kernel.org
Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk>
Reviewed-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-03 09:08:09 +01:00
Tony Prisk f17248ed86 pinctrl: vt8500: Change devicetree data parsing
Due to an assumption in the VT8500 pinctrl driver, the value passed
from devicetree for 'wm,pull' was not explicitly translated before
being passed to pinconf.

Since v3.10, changes to 'enum pin_config_param', PIN_CONFIG_BIAS_PULL_(UP/DOWN)
no longer map 1-to-1 with the expected values in devicetree.

This patch adds a small translation between the devicetree values (0..2)
and the enum pin_config_param equivalent values.

Cc: <stable@vger.kernel.org> # v3.10+
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-03 09:08:01 +01:00
Chris Ruehl 795779df22 pinctrl: imx27: fix wrong offset to ICONFB
The offset to ICONFB was incorrect, this patch set the correct value 0x14.
dev_dbg in function imx1_write_2bit print the wrong address and had been
moved after address calculation.

Cc: stable@vger.kernel.org
Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk>
Reviewed-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-03 09:07:52 +01:00
Nicolas Ferre b0dcfd8732 pinctrl: at91: use locked variant of irq_set_handler
When setting the gpio irq type, use the __irq_set_handler_locked()
variant instead of the irq_set_handler() to prevent false
spinlock recursion warning.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: stable <stable@vger.kernel.org> # v3.12
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-03 09:07:30 +01:00
Linus Torvalds 9b6d351a75 ARM: SoC DT updates for 3.14
DT and DT-conversion-related changes for various ARM platforms. Most
 of these are to enable various devices on various boards, etc, and not
 necessarily worth enumerating.
 
 New boards and systems continue to come in as new devicetree files that
 don't require corresponding C changes any more, which is indicating that
 the system is starting to work fairly well.
 
 A few things worth pointing out:
 
 * ST Ericsson ux500 platforms have made the major push to move over to fully
   support the platform with DT.
 * Renesas platforms continue their conversion over from legacy platform devices
   to DT-based for hardware description.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJS4Vg8AAoJEIwa5zzehBx3tRkP/2dXiXerdB6V63HQ2UjA0J1w
 wnEqOrHXhIBPHVsAjRs+JOqG1iHxwQ+6qPtpxy//OZy5EN/hTamU5HBAKwcJvbbS
 He+a2xhOK6nsjr5QrEk2wupXOodhXDXoaU2mqJ51HAN9AOS68QVbHFh1jHs0f7S0
 RaPVqHTlpXiiWMZ1ScVwl6qqM/hVcK6H3WOrHz09RWG2V/rFth4cJ6hkXBgqBeYU
 Zl24Z9mzStaTI7epDEZXq7jZTMX5lzArL2mCA0jKA+YdEy7KSh5GEzqDGu2qi230
 wwmJ3g5X1WxDvedXPL0+gUffL7UcHWlEV1nl5KtwVsPf/vpsAUvwPLdlObUgA2nr
 /cVrdwQYLaPJKg6xq8IWxaS0K34kLdJyUwiNjKxw5s2GayWEwqGRWALn9TANdKz7
 Wg+RT0UxjHPL8zj/N1uQV/fTdayHE6PnTPorESKDK0a6q9qqzdUypV3j13d9faIS
 FbASmq35zO2iOo4ji7SX6wP4ZwPWV1Yx9UBl4RNDlWu9MyB6jsjiJFT1nyr5PxGo
 WCf8U1Nv4tqCo01gE8AHR1qzlW7cOoya7VMTwDme6J5N9K3GpN+OXqCVItT1lfL2
 s2I0OI6TiD7pTAM4WkgCZaKAhPaE/i2Vc9xlGdZ8L77J4allBtLXTAPpIAZj1Lfl
 a7NT9hbUIiEkTnO8BhHm
 =4o2d
 -----END PGP SIGNATURE-----

Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates from Olof Johansson:
 "DT and DT-conversion-related changes for various ARM platforms.  Most
  of these are to enable various devices on various boards, etc, and not
  necessarily worth enumerating.

  New boards and systems continue to come in as new devicetree files
  that don't require corresponding C changes any more, which is
  indicating that the system is starting to work fairly well.

  A few things worth pointing out:

   * ST Ericsson ux500 platforms have made the major push to move over
     to fully support the platform with DT
   * Renesas platforms continue their conversion over from legacy
     platform devices to DT-based for hardware description"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits)
  ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync
  ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6
  ARM: dts: sirf: add lost minigpsrtc device node
  ARM: dts: sirf: add clock, frequence-voltage table for CPU0
  ARM: dts: sirf: add lost bus_width, clock and status for sdhci
  ARM: dts: sirf: add lost clocks for cphifbg
  ARM: dts: socfpga: add pl330 clock
  ARM: dts: socfpga: update L2 tag and data latency
  arm: sun7i: cubietruck: Enable the i2c controllers
  ARM: dts: add support for EXYNOS4412 based TINY4412 board
  ARM: dts: Add initial support for Arndale Octa board
  ARM: bcm2835: add USB controller to device tree
  ARM: dts: MSM8974: Add MMIO architected timer node
  ARM: dts: MSM8974: Add restart node
  ARM: dts: sun7i: external clock outputs
  ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style
  ARM: dts: sun7i: Add pin muxing options for clock outputs
  ARM: dts: sun7i: Add rtp controller node
  ARM: dts: sun5i: Add rtp controller node
  ARM: dts: sun4i: Add rtp controller node
  ...
2014-01-23 18:45:38 -08:00
Linus Torvalds ac26663572 MFD changes due for the v3.14 merge window
New drivers
  - Samsung Maxim 14577; Micro USB, Regulator, IRQ Controller and Battery Charger
  - TI/National Semiconductor LP3943 I2C GPIO Expander and PWM Generator
 
 Existing driver adaptions
  - Expansion of Wolfson Arizona DSP and High-Pass filter controls
  - TI TWL6040 default Regmap support and Regcache addition/bypass
  - Some nice Smatch catch fixes
  - Conversion of TI OMAP-USB and TI TWL6030 to endian neutralness
  - ChromeOS EC timing (delay) adaptions and added dependency on OF
  - Many constifications of 'struct {mfd_cell,regmap_irq,et. al}'
  - Watchdog support added for NVIDIA AS3722
  - Convert functions to static in TI AM335x
  - Realigned previously defeated functionality in TI AM335x
  - IIO ADC-TSC concurrency dead-lock/timeout resolution
  - Addition of Power Management and Clock support for Samsung core
  - DEFINE_PCI_DEVICE_TABLE macro removal from MFD Subsystem
  - Greater use of irqdomain functionality in ST-E AB8500
  - Removal of 'include/linux/mfd/abx500/ab8500-gpio.h'
  - Wolfson WM831x PMIC Power Management changes s/poweroff/shutdown/
  - Device Tree documentation added for TI/Nat Semi LP3943
  - Version detection and voltage tables for TI TPS6586x PMIC devices
  - Simplification of Freescale MC13XXX (de-)initialisation routines
  - Clean-up and simplification of the Realtek parent driver
  - Added support for RTL8402 Realtek PCI-Express card reader
  - Resource leak fix for Maxim 77686
  - Possible suspend BUG() fix in OMAP USB TLL
  - Support for new Wolfson WM5110 Revision (D)
  - Testing of automatic assignment of of_node in mfd_add_device()
    - Reversion of the above when it started to cause issues
  - Remove legacy Platform Data from;
               TI TWL Core, Qualcomm SSBI and ST-E ABx500 Pinctrl
  - Clean-ups; tabbing issues, function name changes, 'drvdata = NULL' removal,
               unused uninitialised warning mitigation, error message clarity,
               removal of redundant/duplicate checks, licensing (GPL -> GPL2),
               coding consistency, duplicate function declaration, ret checks,
               commit corrections, redundant of_match_ptr() helper removal,
               spelling, #if-deffery removal and header guards name changes
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIbBAABAgAGBQJS3pLGAAoJEFGvii+H/HdhmkkP93Hrd9FBjVpmUQcOrghFDd//
 vte2LVDovXDcwm7i+BdZNG3+2aWtliTQXIw8PaAziUTwMlDNtT2B6GBFnIff4aXB
 Em/Oh6Je7r1gom1gMPCuefRrInTk0xEXy9Oazp4Hn4in71T+8PHNlEHdxEojakEm
 H5FnjAfgISEsA5twSyO9efVLNqPd3UQqg3O571oKwfuSED70YSCW2Yyaoiz4pnE5
 0WwZ9cel+sP7CIuyuR4TumUSDeBIAnYnZWqjqXZ1ueMWcm2RNVqeFrt/w0uoZjOA
 yBg8ZMfkBcePd6qnifqVqagRW/jW1bxmUeIHkp0bWeMqWN6Yyypitz8ZW+Qi7Swa
 OcmgM9V7OW1WG9FF7HoLbYHIPzmBb6duGtcCfAir4m8HJjyPfTuJpOshBW1F3+VG
 yEf5a1fj2NO34kvIbLec2f7MveIMmZxzWaoOx+ET9/WPknilifgyp7eDH24pQwI4
 5Lo5Z5uAfBCT3roOzHxCLl2nVXQoC66iTwdnneiEOn4rB/ApjfGVvGGd0VT6TD+g
 z3RqxpTdkd0AtjfeF778uTDBEKu7HZkqmlBP8HKWCBEAzqcKg7BpjYw0ajgmVwKr
 QiuBuWcEZ/2vVt8Qot7y5Vx89Q4AQwOqc24SldtQLu46iPAuKt+GizzHRw3IxBiQ
 VU9Aq/VoaTHBLS91tDE=
 =PuTE
 -----END PGP SIGNATURE-----

Merge tag 'mfd-3.14-1' of git://git.linaro.org/people/ljones/mfd

Pull MFD changes from Lee Jones:
 "New drivers
   - Samsung Maxim 14577; Micro USB, Regulator, IRQ Controller and
     Battery Charger
   - TI/National Semiconductor LP3943 I2C GPIO Expander and PWM
     Generator

  Existing driver adaptions
   - Expansion of Wolfson Arizona DSP and High-Pass filter controls
   - TI TWL6040 default Regmap support and Regcache addition/bypass
   - Some nice Smatch catch fixes
   - Conversion of TI OMAP-USB and TI TWL6030 to endian neutralness
   - ChromeOS EC timing (delay) adaptions and added dependency on OF
   - Many constifications of 'struct {mfd_cell,regmap_irq,et.al}'
   - Watchdog support added for NVIDIA AS3722
   - Convert functions to static in TI AM335x
   - Realigned previously defeated functionality in TI AM335x
   - IIO ADC-TSC concurrency dead-lock/timeout resolution
   - Addition of Power Management and Clock support for Samsung core
   - DEFINE_PCI_DEVICE_TABLE macro removal from MFD Subsystem
   - Greater use of irqdomain functionality in ST-E AB8500
   - Removal of 'include/linux/mfd/abx500/ab8500-gpio.h'
   - Wolfson WM831x PMIC Power Management changes s/poweroff/shutdown/
   - Device Tree documentation added for TI/Nat Semi LP3943
   - Version detection and voltage tables for TI TPS6586x PMIC devices
   - Simplification of Freescale MC13XXX (de-)initialisation routines
   - Clean-up and simplification of the Realtek parent driver
   - Added support for RTL8402 Realtek PCI-Express card reader
   - Resource leak fix for Maxim 77686
   - Possible suspend BUG() fix in OMAP USB TLL
   - Support for new Wolfson WM5110 Revision (D)
   - Testing of automatic assignment of of_node in mfd_add_device()
   - Reversion of the above when it started to cause issues
   - Remove legacy Platform Data from;
              TI TWL Core, Qualcomm SSBI and ST-E ABx500 Pinctrl
   - Clean-ups; tabbing issues, function name changes, 'drvdata = NULL'
              removal, unused uninitialised warning mitigation, error
              message clarity, removal of redundant/duplicate checks,
              licensing (GPL -> GPL2), coding consistency, duplicate
              function declaration, ret checks, commit corrections,
              redundant of_match_ptr() helper removal, spelling,
              #if-deffery removal and header guards name changes"

* tag 'mfd-3.14-1' of git://git.linaro.org/people/ljones/mfd: (78 commits)
  mfd: wm5110: Add register patch for rev D chip
  mfd: omap-usb-tll: Don't hold lock during pm_runtime_get/put_sync()
  gpio: lp3943: Remove redundant of_match_ptr helper
  mfd: sta2x11-mfd: Use named constants for pci_power_t values
  Documentation: mfd: Fix LDO index in s2mps11.txt
  mfd: Cleanup mfd-mcp-sa11x0.h header
  mfd: max8997: Use "IS_ENABLED(CONFIG_OF)" for DT code.
  mfd: twl6030: Fix endianness problem in IRQ handler
  mfd: sec-core: Add cells for S5M8767-clocks
  mfd: max14577: Remove redundant of_match_ptr helper
  mfd: twl6040: Fix sparse non static symbol warning
  mfd: Revert "mfd: Always assign of_node in mfd_add_device()"
  mfd: rtsx: Fix sparse non static symbol warning
  mfd: max77693: Set proper maximum register for MUIC regmap
  mfd: max77686: Fix regmap resource leak on driver remove
  mfd: Represent correct filenames in file headers
  mfd: rtsx: Add support for card reader rtl8402
  mfd: rtsx: Add set pull control macro and simplify rtl8411
  mfd: max8997: Enforce mfd_add_devices() return value check
  mfd: mc13xxx: Simplify probe() & remove()
  ...
2014-01-21 10:58:17 -08:00
Linus Torvalds a547df99aa Bulk pin control changes for the v3.14 cycle:
- New driver for the Qualcomm TLMM pin controller and its
   msm8x74 subdriver.
 
 - New driver for the Broadcom Capri BCM281xx SoC.
 
 - New subdriver for the imx25 pin controller.
 
 - New subdriver for the Tegra124 pin controller.
 
 - Lock GPIO lines as IRQs for select combined pin control and
   GPIO drivers for baytrail and sirf.
 
 - Some semi-big refactorings and extenstions to the sirf
   driver.
 
 - Lots of patching, cleanup and fixing in the Renesas "PFC"
   driver and associated subdrivers as usual. It is settling
   down a little bit now it seems.
 
 - Minor fixes and incremental updates here and there as usual.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJS3mvwAAoJEEEQszewGV1zc3wP/RYjFaS4WGXX/QnvXGlTwpyb
 3IIQM4l507ds97ipjip9OO31od8HqkWw4lREwKvRdtqItZJiSzG3oYwn+ro+X2E5
 tif0kDxae1tFWieVjA2+zuvjZ76ve8FsVUuUTY7qdd4jdD3OO6P9BgDT0QqwN1Uh
 QToszugQzeOqJARn/DKHg2hkBlg0NorasskCvy6qALbXkWIpLm0U4di2HmGgvV2e
 5YqRCA8uAf48fE6Q93PQNYQU7Zux1Lyr59y0Wl/pnfKKvi1qG2KPnHDJhMmUbxJk
 tWi2VcB1Msrhccv+o0onNMfILG0xInmss3NELTTJJEhSjDvaETkng9fCbw4XDaKY
 KLQ7aRjodbGlvdAONqzZR6e0Ra+piGKDdm94+hvOn0BS1SVfjVA7d6AaeTdR6g+6
 GD+EVqzczAtla8g1xwNKp69SDN1I3yddMQzjQProSE/eGaQYN6aJW+2hDpD3SoOD
 uezFyktzehCIJ5WOIcth8RapN7p33w7bbDOuGVESCesF4NcaUqF+19ukAN9kzVhd
 6oksU1RsxLUdBg/zO7Dwyuhx0XzOuBvrP3EADU37MpnTyCGz4ko4vH0T7JHaA5Oe
 lN9otYBZT0p/kYUEdINjF3foc7f2yc8adC5kDUB9p/zdzyPIwCijGGD6shJGr11/
 7SQ8DvyJZeq3lSNs8+RG
 =ol2E
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull bulk pin control changes from Linus Walleij:
 "This has been queued and tested for a while.  Lots of action here,
  like in the GPIO tree, embedded stuff like this is really hot now it
  seems.  Details in the signed tag.  I'm especially happy about the
  Qualcomm driver as it is used in such a huge subset of mobile handsets
  out there, and these platforms in general need better upstream support

   - New driver for the Qualcomm TLMM pin controller and its msm8x74
     subdriver.

   - New driver for the Broadcom Capri BCM281xx SoC.

   - New subdriver for the imx25 pin controller.

   - New subdriver for the Tegra124 pin controller.

   - Lock GPIO lines as IRQs for select combined pin control and GPIO
     drivers for baytrail and sirf.

   - Some semi-big refactorings and extenstions to the sirf driver.

   - Lots of patching, cleanup and fixing in the Renesas "PFC" driver
     and associated subdrivers as usual.  It is settling down a little
     bit now it seems.

   - Minor fixes and incremental updates here and there as usual"

* tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: sunxi: Honor GPIO output initial vaules
  pinctrl: capri: add dependency on OF
  ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs
  ARM: pinctrl: Add Broadcom Capri pinctrl driver
  pinctrl: Add pinctrl binding for Broadcom Capri SoCs
  pinctrl: Add void * to pinctrl_pin_desc
  pinctrl: st: Fix a typo in probe
  pinctrl: Fix some typos and grammar issues in the documentation
  pinctrl: sirf: lock IRQs when starting them
  pinctrl: sirf: put gpio interrupt pin into input status automatically
  pinctrl: sirf: use only one irq_domain for the whole device node
  pinctrl: single: fix infinite loop caused by bad mask
  pinctrl: single: fix pcs_disable with bits_per_mux
  pinctrl: single: fix DT bindings documentation
  pinctrl: as3722: Set pin to output mode for some function
  pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync
  pinctrl: sirf: fix the pins of sdmmc5 connected with TriG
  pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6
  pinctrl: sunxi: Add Allwinner A20 clock output pin functions
  pinctrl/lantiq: fix typo
  ...
2014-01-21 10:14:10 -08:00
Linus Torvalds 8e50966072 GPIO tree bulk changes for v3.14
A big set this merge window, as we have much going on in
 this subsystem. Major changes this time:
 
 - Some core improvements and cleanups to the new GPIO
   descriptor API. This seems to be working now so we can
   start the exodus to this API, moving gradually away from
   the global GPIO numberspace.
 
 - Incremental improvements to the ACPI GPIO core, and move
   the few GPIO ACPI clients we have to the GPIO descriptor
   API right *now* before we go any further. We actually
   managed to contain this *before* we started to litter
   the kernel with yet another hackish global numberspace for
   the ACPI GPIOs, which is a big win.
 
 - The RFkill GPIO driver and all platforms using it have
   been migrated to use the GPIO descriptors rather than
   fixed number assignments. Tegra machine has been migrated
   as part of this.
 
 - New drivers for MOXA ART, Xtensa GPIO32 and SMSC SCH311x.
   Those should be really good examples of how I expect a
   nice GPIO driver to look these days.
 
 - Do away with custom GPIO implementations on a major
   part of the ARM machines: ks8695, lpc32xx, mv78xx0.
   Make a first step towards the same in the horribly
   convoluted Samsung S3C include forest. We expect to
   continue to clean this up as we move forward.
 
 - Flag GPIO lines used for IRQ on adnp, bcm-kona, em,
   intel-mid and lynxpoint.
   This makes the GPIOlib core aware that a certain GPIO line
   is used for IRQs and can then enforce some semantics such
   as disallowing a GPIO line marked as in use for IRQ to be
   switched to output mode.
 
 - Drop all use of irq_set_chip_and_handler_name().
   The name provided in these cases were just unhelpful
   tags like "mux" or "demux".
 
 - Extend the MCP23s08 driver to handle interrupts.
 
 - Minor incremental improvements for rcar, lynxpoint, em
   74x164 and msm drivers.
 
 - Some non-urgent bug fixes here and there, duplicate
   #includes and that usual kind of cleanups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJS3i/MAAoJEEEQszewGV1zVB8P/Rjzgx8To0gQPn49M4u/A1Mk
 mAzpUoKa05ILTKBm/bpWPYZPpg9PDqUxOYPsIDEAkc70BKMPTXxrYiE+LSfIzwaJ
 a8IRwOzNL7Iwc+zPNS/GrmRJyxymb4lmMD/fypk/YaumZ6j4Hbo+9R8Zct9gbZ5Q
 ZbKtz6kLhbkbNCc71bVMgk6yacSBx1ak8Xpd12HlW85NgOCoBj7/DI1Lb61x1ImY
 NYpSpmtfGGTkQLtBl5dTLefZOvL1dKSct9TMOsA2jzNqf3zA1YA6XOxPGHK/qtjq
 3s9cN1sIVF/g7sm1+qoKXe0OTQrXHT7SX8BH9/tb3MiKO8ItactlQUJlYNR3WFSN
 zm1PNe5zWr+GWzV0iUrqoMN4XX8nThiFDOxZpOwBTZcUD6qtDFIZp41M3qxwFTbJ
 hCtSQ8gUO1Ce+xtOQYYOwEkRS7FZa1Z+p/lendTFuGDh6DcXy97SrKkTktM4Q98B
 LhqrwUzCdES0ecNDi2+P5y4Fc7M0cMMn9SnFvbSBObLB89TF9uzMIn8jUBCZMvrM
 eAeZlRBYk8F+6F12higaWqZyiBKIEubXo/Z8T0L2KEDm/z/ddJvhQgBKvWlf3rqi
 RToD446rda+RhFBnxLZ3mTui5nZ2WyKTOqhVqeBuriJhE/cTUaQHUBUrbOwx20kE
 Xb9mQ2n3GRk2157n1CLY
 =lW2i
 -----END PGP SIGNATURE-----

Merge tag 'gpio-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO tree bulk changes from Linus Walleij:
 "A big set this merge window, as we have much going on in this
  subsystem.  The changes to other subsystems (notably a slew of ARM
  machines as I am doing away with their custom APIs) have all been
  ACKed to the extent possible.

  Major changes this time:

   - Some core improvements and cleanups to the new GPIO descriptor API.
     This seems to be working now so we can start the exodus to this
     API, moving gradually away from the global GPIO numberspace.

   - Incremental improvements to the ACPI GPIO core, and move the few
     GPIO ACPI clients we have to the GPIO descriptor API right *now*
     before we go any further.  We actually managed to contain this
     *before* we started to litter the kernel with yet another hackish
     global numberspace for the ACPI GPIOs, which is a big win.

   - The RFkill GPIO driver and all platforms using it have been
     migrated to use the GPIO descriptors rather than fixed number
     assignments.  Tegra machine has been migrated as part of this.

   - New drivers for MOXA ART, Xtensa GPIO32 and SMSC SCH311x.  Those
     should be really good examples of how I expect a nice GPIO driver
     to look these days.

   - Do away with custom GPIO implementations on a major part of the ARM
     machines: ks8695, lpc32xx, mv78xx0.  Make a first step towards the
     same in the horribly convoluted Samsung S3C include forest.  We
     expect to continue to clean this up as we move forward.

   - Flag GPIO lines used for IRQ on adnp, bcm-kona, em, intel-mid and
     lynxpoint.

     This makes the GPIOlib core aware that a certain GPIO line is used
     for IRQs and can then enforce some semantics such as disallowing a
     GPIO line marked as in use for IRQ to be switched to output mode.

   - Drop all use of irq_set_chip_and_handler_name().  The name provided
     in these cases were just unhelpful tags like "mux" or "demux".

   - Extend the MCP23s08 driver to handle interrupts.

   - Minor incremental improvements for rcar, lynxpoint, em 74x164 and
     msm drivers.

   - Some non-urgent bug fixes here and there, duplicate #includes and
     that usual kind of cleanups"

Fix up broken Kconfig file manually to make this all compile.

* tag 'gpio-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (71 commits)
  gpio: mcp23s08: fix casting caused build warning
  gpio: mcp23s08: depend on OF_GPIO
  gpio: mcp23s08: Add irq functionality for i2c chips
  ARM: S5P[v210|c100|64x0]: Fix build error
  gpio: pxa: clamp gpio get value to [0,1]
  ARM: s3c24xx: explicit dependency on <plat/gpio-cfg.h>
  ARM: S3C[24|64]xx: move includes back under <mach/> scope
  Documentation / ACPI: update to GPIO descriptor API
  gpio / ACPI: get rid of acpi_gpio.h
  gpio / ACPI: register to ACPI events automatically
  mmc: sdhci-acpi: convert to use GPIO descriptor API
  ARM: s3c24xx: fix build error
  gpio: f7188x: set can_sleep attribute
  gpio: samsung: Update documentation
  gpio: samsung: Remove hardware.h inclusion
  gpio: xtensa: depend on HAVE_XTENSA_GPIO32
  gpio: clps711x: Enable driver compilation with COMPILE_TEST
  gpio: clps711x: Use of_match_ptr()
  net: rfkill: gpio: convert to descriptor-based GPIO interface
  leds: s3c24xx: Fix build failure
  ...
2014-01-21 10:09:12 -08:00
Linus Walleij 97b583f3b4 mfd/pinctrl: Delete platform data header
This deletes the special AB8500 GPIO platform data passing
header and merges the few remaining contents down into the
abx500 pinctrl driver which handles the abx500 GPIO device.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-01-21 08:27:42 +00:00
Linus Walleij ac99a037bc pinctrl: abx500: Delete non-devicetree probe path
All instances of this device are now coming from device tree-
enabled platforms probing without using platform data.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-01-21 08:13:39 +00:00
Chen-Yu Tsai fa8cf57c92 pinctrl: sunxi: Honor GPIO output initial vaules
Some GPIO users, such as fixed-regulator, request GPIO output with
initial value of 1. This was ignored by sunxi driver.

Cc: stable@vger.kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-20 09:19:17 +01:00
Rafael J. Wysocki 2b844ba79f Revert "ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs"
This reverts commit f6308b36c4 (ACPI: Add BayTrail SoC GPIO and LPSS
ACPI IDs), because it causes the Alan Cox' ASUS T100TA to "crash and
burn" during boot if the Baytrail pinctrl driver is compiled in.

Fixes: f6308b36c4 (ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs)
Reported-by: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk>
Requested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2014-01-18 14:04:58 +01:00
Linus Walleij fe0ec0ee07 pinctrl: capri: add dependency on OF
As this driver is using pinconf_generic_dt_node_to_map_pin() it
needs to depend on OF so as not to cause build problems on
archs that do not support OF.

Cc: Sherman Yin <syin@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-16 23:44:25 +01:00
Sherman Yin 54b1aa5a5b ARM: pinctrl: Add Broadcom Capri pinctrl driver
Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs.

v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig
    - make use of regmap
    - change CAPRI_PIN_UPDATE from macro to inline function.
    - Handle pull-up strength arg in Ohm instead of enum
v3: Re-work driver to be based on generic pin config. Moved config selection
    from Kconfig to bcm_defconfig.
v2: Use hyphens instead of underscore in DT property names.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Christian Daudt <bcm@fixthebug.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-16 14:25:38 +01:00
Srinivas Kandagatla c9dd66b73c pinctrl: st: Fix a typo in probe
Probe function had commas instead of semi-colons on some of the lines.
This patch just fixes those lines. No functional chagnes done in this
patch.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 13:59:51 +01:00
Linus Walleij 655dada627 pinctrl: sirf: lock IRQs when starting them
This uses the new API for tagging GPIO lines as in use by
IRQs. This enforces a few semantic checks on how the underlying
GPIO line is used.

Also assign the gpio_chip.dev pointer to be used for error
messages.

Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 13:59:44 +01:00
Barry Song b07ddcdcb2 pinctrl: sirf: put gpio interrupt pin into input status automatically
busses like i2c, spi and so on can parse the virq of their subnode automatically by
irq_of_parse_and_map(). for example, i2c will do that in of_i2c_register_devices().
people can put hwirq number attached to a gpio controller in dts, and drivers can
directly request the parsed virq.

for example, for an i2c client as below,
tangoc-ts@5c{
	compatible = "pixcir,tangoc-ts";
	interrupt-parent = <&gpio>;
	interrupts = <3 0>;
	reg = <0x5c>;
};
in i2c client probe(), it will request_irq(client->irq, ...) without
calling gpio_direction_input().
so here when we set irq type, we also put the pin to input direction.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 09:10:00 +01:00
Barry Song 8daeffb058 pinctrl: sirf: use only one irq_domain for the whole device node
in sirfsoc gpio probe(), we create 5 irq_domains for 5 gpio banks. but
in irq_create_of_mapping() of irqchip core level, irq_find_host() can
only return the 1st irq_domain attached the pinctrl dt device node as
we can see from the codes:

unsigned int irq_create_of_mapping(struct device_node *controller,
				   const u32 *intspec, unsigned int intsize)
{
	struct irq_domain *domain;
	...
	domain = controller ? irq_find_host(controller) : irq_default_domain;
}

struct irq_domain *irq_find_host(struct device_node *node)
{
	struct irq_domain *h, *found = NULL;
	int rc;

	/* We might want to match the legacy controller last since
	 * it might potentially be set to match all interrupts in
	 * the absence of a device node. This isn't a problem so far
	 * yet though...
	 */
	mutex_lock(&irq_domain_mutex);
	list_for_each_entry(h, &irq_domain_list, link) {
		if (h->ops->match)
			rc = h->ops->match(h, node);
		else
			rc = (h->of_node != NULL) && (h->of_node == node);

		if (rc) {
			found = h;
			break;
		}
	}
	mutex_unlock(&irq_domain_mutex);
	return found;
}

for sirfsoc, the 1st irq_domain attached to the device_node(controller) only
can do linear for the 1st 32 gpios. so for devices who use gpio hwirq above
32 and put the information in dt like:
                                tangoc-ts@5c{
                                        compatible = "pixcir,tangoc-ts";
+                                       interrupt-parent = <&gpio>;
+                                       interrupts = <34 0>;
                                };

we will fail to get the virq for these devices as hwirq will be bigger than
domain->revmap_data.linear.size in:
unsigned int irq_linear_revmap(struct irq_domain *domain,
			       irq_hw_number_t hwirq)
{

	/* Check revmap bounds; complain if exceeded */
	if (WARN_ON(hwirq >= domain->revmap_data.linear.size))
		return 0;

	return domain->revmap_data.linear.revmap[hwirq];
}

this patch drops redundant irq_domain and keep only one to fix the problem.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 09:07:56 +01:00
Tomi Valkeinen ad5d25fef8 pinctrl: single: fix infinite loop caused by bad mask
commit 4e7e8017a8 (pinctrl: pinctrl-single:
enhance to configure multiple pins of different modules) improved
support for pinctrl-single,bits option, but also caused a regression
in parsing badly configured mask data.

If the masks in DT data are not quite right,
pcs_parse_bits_in_pinctrl_entry() can end up in an infinite loop,
trashing memory at the same time.

Add a check to verify that each loop actually removes bits from the
'mask', so that the loop can eventually end.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 08:31:53 +01:00
Tomi Valkeinen dd4c2b3cb3 pinctrl: single: fix pcs_disable with bits_per_mux
pcs_enable() uses vals->mask instead of pcs->fmask when bits_per_mux is
enabled. However, pcs_disable() always uses pcs->fmask.

Fix pcs_disable() to use vals->mask with bits_per_mux.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15 08:30:08 +01:00
Mallikarjun Kasoju f8720e5ec7 pinctrl: as3722: Set pin to output mode for some function
If pins are used for function output like pwm, clk32k,
power good etc then set it as output mode default.

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-14 10:34:18 +01:00
Mika Westerberg 664e3e5ac6 gpio / ACPI: register to ACPI events automatically
Instead of asking each driver to register to ACPI events we can just call
acpi_gpiochip_register_interrupts() for each chip that has an ACPI handle.
The function checks chip->to_irq and if it is set to NULL (a GPIO driver
that doesn't do interrupts) the function does nothing.

We also add the a new header drivers/gpio/gpiolib.h that is used for
functions internal to gpiolib and add ACPI GPIO chip registering functions
to that header.

Once that is done we can remove call to acpi_gpiochip_register_interrupts()
from its only user, pinctrl-baytrail.c

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 15:07:28 +01:00
Rongjun Ying 8385af02ba pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync
USP0 has multiple functions, and has RX and TX frame sync signals,
for some scenarios like audio PCM, we don't need both of them.
so here we add two possibilities for USP0 only holding one of TX
and RX frame sync.

Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: Barry Song <Barry.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:51:10 +01:00
Bin Shi cbc3b873c8 pinctrl: sirf: fix the pins of sdmmc5 connected with TriG
sdmmc5 has only 3 pins CMD, CLK, DATA which are connected with CSR
TriG RF multi-GNSS. The hardware connection is like:
DATA -- GPS_SGN
CLK  -- GPS_RF_CLK
CMD  -- GPS_MAG
here we drop redundant pins in sdmmc5 group.

Signed-off-by: Bin Shi <Bin.Shi@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:50:21 +01:00
Qipan Li 6225633d71 pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6
commit af614b2301 adds lost USP-based UART pin groups for prima2,
but missed usp1_uart_nostreamctrl group for atlas6, this patch fixes it.

this makes USP(Universal Serial Ports) port1 can work as uart without
stream ctrl.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:48:38 +01:00
Chen-Yu Tsai b6a32a28cd pinctrl: sunxi: Add Allwinner A20 clock output pin functions
This patch adds the clock output pin functions on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:46:28 +01:00
Antonios Vamporakis a1edd49e42 pinctrl/lantiq: fix typo
Signed-off-by: Antonios Vamporakis <ant@area128.com>
CC: John Crispin <blogic@openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-08 10:13:38 +01:00
Valentine Barshak a5ffaf6445 pinctrl: sh-pfc: r8a7791: Add I2C pins
This adds I2C[0-4] pinmux support to R8A7791 SoC.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07 16:48:54 +01:00
Valentine Barshak 8e32c9671f pinctrl: sh-pfc: r8a7791: Add VIN pins
This adds VIN[0-2] pinmux support to r8a7791 SoC.
VIN1 B mirror is also added along with the primary
configuration since it's the only one that provides
access to all 24 data bits on VIN1.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07 16:48:50 +01:00
Valentine Barshak 5e5a298cdb pinctrl: sh-pfc: r8a7791: Group USB PWEN and OVC pins together
This groups USB PWEN and OVC pins together on R8A7791 SoC,
the same way it's done on R8A7790, since both are needed
for a USB device.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07 16:48:46 +01:00
Valentine Barshak 646ae3ef7e pinctrl: sh-pfc: r8a7790: Fix vsync value in the vin3_sync_mux array
This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/).

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07 16:48:35 +01:00
Olof Johansson 11b35a3525 Third Round of Renesas ARM Based SoC DT Updates for v3.14
* r8a7791 (R-Car M2) and r8a7790 (R-Car H2) SoCSs
   - Add SSI, QSPI and MSIOF  clocks in device tree
 
 r8a7791 (R-Car M2) based Koelsch and r8a7790 (R-Car H2) based Lager boards
   - Remove reference DTS
   - Specify external clock frequency in DT
   - Sync non-reference DTS with referene DTS
   - Add clocks to DTS
 
 * r8a7740 (R-Mobile A1) based Armadillo board
   - Add gpio-keys device
   - Add PWM backlight enable GPIO
   - Add PWM backlight power supply
 
 * r8a73a0 (SH-Mobile AG5), r8a7740 (R-Mobile A1) and
   r8a73a4 (SH-Mobile APE6) SoCs
   - Specify PFC interrupts in DT
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJSuZPxAAoJENfPZGlqN0++G1cP/j2A/bL1NA1MeYSYmTeaW50X
 vbEseiL4vbme3TJ6c+yJMd8ayV2V3W+fzua+s4R6+9Q1oyfCwigbS+lfrjx6e2+Q
 KanklWZOJyj6NerSoHtF4e9ayE+YN4IuMR0fLKr7W4cqn3+EHuBMAxOhd70JxYfD
 tEI9t9fJEjMTDFQlzlkDGyYJX5ryg3jXs3WC96pqHafdHlznSsS2l+aANKWBDrjO
 hPeqWygK2Wz56ifO5A2/N8skGtHTaqDVGdhXSqa6vcH1wWdM9yK8cnpE7ktwrFyo
 dOD2uu1mmNv4NiaW5fyKNKjdde3YRY/wJ7S0CSuYdShnbEaIQbyqPDMUmZErEF2j
 9S/GXPnyVjmDeaQ8cnhr8+NIsn/hM72mOaQB/jyrF979dlCkYov3pr+5TiupKXCG
 hqOaHG8OtlusG0p19oO8DWgzHZsgrYwwBdaDSRF/NCilk5wOgQg2gf8sWr6W/Kiz
 8TFZvS99tlzhAXUthhINf4cHg1otAuMt4xKiDlpy2dzd1LGaHRxtCFFecF3b6PIF
 zTa2rjdUV8mNXB4jhG7EdoLqMamuHifIY9TngQg+f1CjQH0BkR4BgOYY6FnlHI36
 NGjRqUJBY0tDBRL3yER0s9QIPhtZgkYGO3PrniGlT9575VNK1CuwW4JwNBkwZyPC
 xVbIpoJqG5cXMN4ENLFe
 =NpbK
 -----END PGP SIGNATURE-----

Merge tag 'renesas-dt3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

From Simon Horman:
Third Round of Renesas ARM Based SoC DT Updates for v3.14

* r8a7791 (R-Car M2) and r8a7790 (R-Car H2) SoCSs
  - Add SSI, QSPI and MSIOF  clocks in device tree

r8a7791 (R-Car M2) based Koelsch and r8a7790 (R-Car H2) based Lager boards
  - Remove reference DTS
  - Specify external clock frequency in DT
  - Sync non-reference DTS with referene DTS
  - Add clocks to DTS

* r8a7740 (R-Mobile A1) based Armadillo board
  - Add gpio-keys device
  - Add PWM backlight enable GPIO
  - Add PWM backlight power supply

* r8a73a0 (SH-Mobile AG5), r8a7740 (R-Mobile A1) and
  r8a73a4 (SH-Mobile APE6) SoCs
  - Specify PFC interrupts in DT

* tag 'renesas-dt3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (72 commits)
  ARM: shmobile: r8a7791: Add SSI clocks in device tree
  ARM: shmobile: r8a7790: Add SSI clocks in device tree
  ARM: shmobile: r8a7791: Add QSPI module clock in device tree
  ARM: shmobile: r8a7790: Add QSPI module clock in device tree
  ARM: shmobile: r8a7791: Add MSIOF clocks in device tree
  ARM: shmobile: r8a7790: Add MSIOF clocks in device tree
  ARM: shmobile: Remove Koelsch reference DTS
  ARM: shmobile: Remove Lager reference DTS
  ARM: shmobile: koelsch: Specify external clock frequency in DT
  ARM: shmobile: lager: Specify external clock frequency in DT
  ARM: shmobile: Sync Koelsch DTS with Koelsch reference DTS
  ARM: shmobile: Sync Lager DTS with Lager reference DTS
  ARM: shmobile: r8a7791: Add clocks
  ARM: shmobile: r8a7790: Reference clocks
  ARM: shmobile: r8a7790: Add clocks
  ARM: shmobile: armadillo: dts: Add gpio-keys device
  ARM: shmobile: sh73a0: Specify PFC interrupts in DT
  ARM: shmobile: r8a7740: Specify PFC interrupts in DT
  ARM: shmobile: r8a73a4: Specify PFC interrupts in DT
  ARM: shmobile: armadillo: dts: Add PWM backlight enable GPIO
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-01-03 21:09:51 -08:00
Rafael J. Wysocki bfde19c4c2 Merge branches 'powercap' and 'acpi-lpss' with new device IDs
* powercap:
  powercap / RAPL: add support for ValleyView Soc

* acpi-lpss:
  ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs
2013-12-27 00:43:24 +01:00
Olof Johansson 770039fef4 Merge branch 'tegra/dma-reset-rework' into next/dt
Bringing in the tegra dma/reset framework cleanup as a base for the DT changes.

* tegra/dma-reset-rework: (320 commits)
  spi: tegra: checking for ERR_PTR instead of NULL
  ASoC: tegra: update module reset list for Tegra124
  clk: tegra: remove bogus PCIE_XCLK
  clk: tegra: remove legacy reset APIs
  ARM: tegra: remove legacy DMA entries from DT
  ARM: tegra: remove legacy clock entries from DT
  USB: EHCI: tegra: use reset framework
  Input: tegra-kbc - use reset framework
  serial: tegra: convert to standard DMA DT bindings
  serial: tegra: use reset framework
  spi: tegra: convert to standard DMA DT bindings
  spi: tegra: use reset framework
  staging: nvec: use reset framework
  i2c: tegra: use reset framework
  ASoC: tegra: convert to standard DMA DT bindings
  ASoC: tegra: allocate AHUB FIFO during probe() not startup()
  ASoC: tegra: call pm_runtime APIs around register accesses
  ASoC: tegra: use reset framework
  dma: tegra: register as an OF DMA controller
  dma: tegra: use reset framework
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-26 11:03:29 -08:00
Laurent Pinchart 44a45b55a7 pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arrays
The arrays are never modified, declare them as const.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:28:40 +01:00
Laurent Pinchart f41a1efe63 pinctrl: sh-pfc: sh: Constify pins and cfg_regs arrays
The arrays are never modified, declare them as const.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:27:43 +01:00
Laurent Pinchart 6d5bddd525 pinctrl: sh-pfc: Constify IRQ GPIOs arrays
The arrays are never modified, make them const.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:26:54 +01:00
Laurent Pinchart 9aecff583e pinctrl: sh-pfc: Constify enum_ids and var_field_width compound literals
The enum_ids and var_field_width fields of struct pinmux_data_reg and
pinmux_cfg_reg are initialized using compound literals. Cast them to
const to store them in .rodata.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:25:59 +01:00
Axel Lin e476e77fe0 pinctrl: msm: Fix set gpio setting
Set g->out_bit bit for gpio output high, clear g->out_bit bit for gpio output
low.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 10:13:23 +01:00
Simon Horman 236573d240 Linux 3.13-rc3
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.15 (GNU/Linux)
 
 iQEcBAABAgAGBQJSogqUAAoJEHm+PkMAQRiGM2MIAJrr5KEXEWuuAR4+JkkWBK7A
 +dVT4n1MM4wP/aCIyriSlq7kgT03Wxk4Q4wKsj2wZvDQkNgEQjrctgIihc75jqi5
 126nmT3YXJLwgDpFA3RHZUWve3j3vfUG53rRuk7K9Xx1sGWU3Ls7BuInvQZ//+QS
 6UB4UuEAalmose5U8ToXQfMqZhjwreZKeb64TEZwFvu2klv4cnka1L/zHbmQGgRg
 2Pfv+aUrjsYE8s9lkEKX8MIQsDn28Q5Lsv7XIEQwo2at4rYbJaxX6usuC1OI0MQ5
 BLUn1GgtvOidq6FzSg6kXiA/MJYH3J0S+p4uULWAprxA+KeJRbWNRroM94W1qAk=
 =1Wcq
 -----END PGP SIGNATURE-----

Merge tag 'v3.13-rc3' into dt3-base

Linux 3.13-rc3

Conflicts:
	drivers/pinctrl/sh-pfc/pfc-r8a7740.c
	drivers/pinctrl/sh-pfc/pfc-sh7372.c
2013-12-19 17:14:25 +09:00
Boris BREZILLON 37ef1d9243 pinctrl: at91: replace clk_prepare + clk_enable by clk_prepare_enable
Replace the clk_prepare and clk_enable calls by a single
clk_prepare_enable call.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 14:22:57 +01:00
Boris BREZILLON 795f9953ea pinctrl: at91: fix clk_unprepare and clk_disable order
clk_unprepare shall be called before clk_disable.
Fix the issue by replacing the clk_unprepare and clk_disable calls by a
single clk_disable_unprepare call.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 14:21:43 +01:00
Sherman Yin 8ba3f4d000 pinctrl: Adds slew-rate, input-enable/disable
This commit adds slew-rate and input-enable/disable support for pinconf
-generic.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:55:03 +01:00
Bjorn Andersson b31d100e92 pinctrl-msm: Rename compatible to be more specific
Use the more specific form 8974 for the compatible to reduce the
risk of future mishaps.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:33:42 +01:00
Bjorn Andersson 408e3c66da pinctrl-msm: Remove separate allocation of bitmaps
Make the bitmaps part of the msm_pinctrl allocation instead of
separately allocating them.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:32:50 +01:00
Bjorn Andersson f393e489c7 pinctrl-msm: Tidy up error handling
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:31:37 +01:00
Bjorn Andersson 1f2b239815 pinctrl-msm: Fix spelling misstakes and missing consts
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:30:25 +01:00
Bjorn Andersson 376f413a7d pinctrl: msm: Update Kconfig for PINCTRL_MSM8X74
Add GPIOLIB and OF as dependencies for PINCTRL_MSM8X74, to fix
build errors from i386-randconfig.
Also add help text and make the entries tristate, while touching
these entries.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
[Rebased on top of pin control development branch]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-16 10:29:25 +01:00
Alexandre Belloni b5728cf766 pinctrl: pinconf: remove warning: unused variable 'ops'
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-13 13:55:15 +01:00
Alexandre Belloni 4d9b8a8e46 pinctrl: at91: implement at91_pinconf_dbg_show
This allows to get the pin configuration by using debugfs. On my system:
 # cat /sys/kernel/debug/pinctrl/pinctrl.3/pinconf-pins

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-13 10:34:07 +01:00
Ashwini Ghuge 1a16bee6bc pinctrl: tegra: add pinmux controller driver for Tegra124
This adds a driver for the Tegra124 pinmux, and required
parameterization data for Tegra124.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra124-pinmux".

Originally written by Ashwini Gguhe.
Thierry:
 - Cleanups in patches.
ldewangan:
 - Fix some entries for groups.
 - Fix MUX enums and group sequence.

Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
CC: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:28:06 +01:00
Laurent Pinchart 70c8f01a35 sh-pfc: Support GPIO to IRQ mapping specified IRQ resources
On non-DT platforms IRQ controllers associated with the GPIOs have a
fixed IRQ base value known at compile time. The sh-pfc driver translates
GPIO number to IRQ numbers using a hardcoded table. This mechanism
breaks on DT platforms, as the IRQ base values are dynamic in that case.

Fix this by specifying IRQs associated with GPIOs in IRQ resources,
populated automatically from the device tree. When IRQ resources are
specified the driver requires one IRQ resource per GPIO able to generate
an interrupt, and uses the translation table to compute the IRQ resource
offset instead of the IRQ number.

Cc: devicetree@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:28 +01:00
Laurent Pinchart 5b46ac3a77 sh-pfc: Rename sh_pfc window field to windows
There's more than one window, name the field windows.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:23 +01:00
Laurent Pinchart de55c71feb sh-pfc: sh73a0: Sort IRQ entries by IRQ number
This makes catching duplicate entries easier. Merge the two IRQ9 entries
found after sorting.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:18 +01:00
Laurent Pinchart c48ca30341 sh-pfc: sh73a0: Add missing IRQ15
The external IRQ15 input multiplexed on GPIO 0 is missing. Add it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:12 +01:00
Laurent Pinchart 316b255001 sh-pfc: Terminate gpios array by -1
0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ
lists.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:07:06 +01:00
Laurent Pinchart 8d72a7fc8d sh-pfc: Turn unsigned indices into unsigned int
Some indices take positive values only, make them unsigned.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 22:06:49 +01:00
Alexandre Belloni c420619d51 pinctrl: pinconf: remove checks on ops->pin_config_get
ops->pin_config_get() is only used in one specific path that will only be taken
for generic pinconf drivers (ops->is_generic == true) when dumping the pinconf
by using debugfs.

By removing the check in pinconf_check_ops(), let's stop pressuring people to
write a pin_config_get() function that will never be used and so will probably
never be tested.

Removing the check in pinconf_pins_show() allows driver to not implement
pin_config_get() but still get a dump of the pinconf in debugfs by implementing
pin_config_dbg_show().

Finally, not implementing pin_config_get() now results in returning -ENOTSUPP
instead of -EINVAL. While this doesn't have any real impact for now, this feels
more right.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 19:11:07 +01:00
Alexandre Belloni 1292e69366 pinctrl: at91: initialize config parameter to 0
When passing a not initialized config parameter, at91_pinconf_get() would return
a bogus value. Fix that by initializing it to zero before using it.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 15:43:36 +01:00
Alexandre Belloni c2eb9e7f02 pinctrl: at91: correct a few typos
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12 15:41:35 +01:00
Valentine Barshak 054d425909 pinctrl: sh-pfc: pfc-r8a7790: Add VIN2 and VIN3 pins
There are VIN2 and VIN3 channels available on the R8A7790 SoC.
VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit.
Add both here, covering all possible data pin configurations.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:39 +01:00
Valentine Barshak 317a03a9cb pinctrl: sh-pfc: pfc-r8a7790: Add missing VIN1 pins
Both VIN0 and VIN1 channels support identical input interfaces.
Add missing VIN1 pins here and organize them in the same pin
groups as VIN0.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:36 +01:00
Valentine Barshak 64fe8abc73 pinctrl: sh-pfc: pfc-r8a7790: Reorganize VIN0 data pins
This reorganizes and renames VIN0 data pin groups to cover
all possible configurations. There's total of eight data
pin groups, one per each configuration. Most of the groups
share the same pin/mux array. Only the 18-bit configuration
needs a separate pin/mux array since in combines interleaved
data pins.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:33 +01:00
Valentine Barshak a9e4c7bb46 pinctrl: sh-pfc: pfc-r8a7790: Group VIN0 HSYNC and VSYNC together
This groups VIN0 HSYNC and VSYNC pins together
since one cannot be used without another.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:30 +01:00
Valentine Barshak 7a57be873a pinctrl: sh-pfc: pfc-r8a7790: Rename VIN pin groups
This drops superfluous "signal" word from the pin group names
and renames data_enable group to clkenb as in the h/w manual.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10 20:42:16 +01:00
Takashi Yoshii 2ef3967ef5 sh-pfc: r8a7791: Fix msiof groups to follow GROUP
SH_PFC_PIN_GROUP(), pins[], mux[], defines
 clk, sync, ss1, ss2, rx, tx
But, msiof?_groups[] defines
 clk, ctrl, data

Fix msiof[012]_groups members to be consistent to PIN_GROUP.

Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10 16:22:55 +01:00
Kuninori Morimoto fcec5b2254 sh-pfc: r8a7790: Add Audio pin support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10 16:22:54 +01:00
Kuninori Morimoto 1d7b59a077 sh-pfc: r8a7790: Add SSI pin support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10 16:22:54 +01:00
Laurent Pinchart 3f9c126815 sh-pfc: Share common PORTCR macro definition
The macro is defined identically in four different locations. Share it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-10 16:18:08 +01:00
Laurent Pinchart 8620f394c4 sh-pfc: Fix PINMUX_GPIO macro
Commit 7cbb0e55e2 ("sh-pfc: Don't duplicate argument to PINMUX_GPIO
macro") erronesouly modified the PINMUX_GPIO macro in a way that
resulted in all pins being named "name". Fix the macro to name the pins
correctly.

Cc: stable@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-10 13:12:28 +01:00
Linus Walleij 18334c8e18 pinctrl: make the MSM SoC driver depend on OF
We had a compilation failure on x86_64 due to missing OF support
as this was an implicit dependency. Add an explicit dependency
on OF and OF_IRQ on the SoC driver.

Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Total failure with older approaches: what we need to do is
  have the *SoC subdriver* depend on OF and OF_IRQ. This is
  because the placeholder bool PINCTRL_MSM cannot cascade its
  dependencies when a subdriver selects it, Kconfig is smart
  but not that smart.
ChangeLog v1->v2:
- OK so "depends on OF" did not work here let's try to simply
  select OF and OF_IRQ for this then? It's one of those
  "warning: (PINCTRL_MSM8X74) selects PINCTRL_MSM which has
  unmet direct dependencies (PINCTRL && OF)" that I simply
  cannot find my way out of :-/
2013-12-10 10:03:47 +01:00
Linus Walleij 1d2d8ce61f pinctrl: baytrail: lock IRQs when starting them
This uses the new API for tagging GPIO lines as in use by
IRQs. This enforces a few semantic checks on how the underlying
GPIO line is used.

Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Mathias Nyman <mathias.nyman@linux.intel.com>
Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-09 15:16:31 +01:00
Linus Walleij bdc54ef45d Linux 3.13-rc3
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.15 (GNU/Linux)
 
 iQEcBAABAgAGBQJSogqUAAoJEHm+PkMAQRiGM2MIAJrr5KEXEWuuAR4+JkkWBK7A
 +dVT4n1MM4wP/aCIyriSlq7kgT03Wxk4Q4wKsj2wZvDQkNgEQjrctgIihc75jqi5
 126nmT3YXJLwgDpFA3RHZUWve3j3vfUG53rRuk7K9Xx1sGWU3Ls7BuInvQZ//+QS
 6UB4UuEAalmose5U8ToXQfMqZhjwreZKeb64TEZwFvu2klv4cnka1L/zHbmQGgRg
 2Pfv+aUrjsYE8s9lkEKX8MIQsDn28Q5Lsv7XIEQwo2at4rYbJaxX6usuC1OI0MQ5
 BLUn1GgtvOidq6FzSg6kXiA/MJYH3J0S+p4uULWAprxA+KeJRbWNRroM94W1qAk=
 =1Wcq
 -----END PGP SIGNATURE-----

Merge tag 'v3.13-rc3' into devel

Linux 3.13-rc3
2013-12-09 14:04:37 +01:00
Bjorn Andersson 55aaf8342d pinctrl: Add msm8x74 configuration
Add initial definition of parameters for pinctrl-msm for the msm8x74
platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-06 14:58:34 +01:00
Bjorn Andersson f365be0925 pinctrl: Add Qualcomm TLMM driver
This adds a pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-06 14:58:33 +01:00
Linus Walleij 9fb1f39eb2 gpio/pinctrl: make gpio_chip members typed boolean
This switches the two members of struct gpio_chip that were
defined as unsigned foo:1 to bool, because that is indeed what
they are. Switch all users in the gpio and pinctrl subsystems
to assign these values with true/false instead of 0/1. The
users outside these subsystems will survive since true/false
is 1/0, atleast we set some kind of more strict typing example.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-04 14:42:46 +01:00
Laurent Pinchart 71493de7e5 sh-pfc: sh7372: Fix pin bias setup
When computing the pin configuration register offset the bias setup code
erroneously compares the pin number range with the loop index instead of
the pin number. Fix it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-03 10:38:41 +01:00
Laurent Pinchart 5d27619498 sh-pfc: r8a7740: Fix pin bias setup
When computing the pin configuration register offset the bias setup code
erroneously compares the pin number range with the loop index instead of
the pin number. Fix it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-03 10:38:39 +01:00
Mathias Nyman a4d8d6da48 pinctrl-baytrail: show pin label with the reset of the gpio debug data
The default gpiolib debug output shows pin labels.
We want baytrail custom debug output to have the same functionality.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-03 10:08:46 +01:00
Axel Lin a9e51fe5e6 pinctrl: abx500: Fix header file include guard
Fix a trivial typo.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-02 11:37:48 +01:00
Paul Drews f6308b36c4 ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs
This adds the new ACPI ID (INT33FC) for the BayTrail GPIO
banks as seen on a BayTrail M System-On-Chip platform.  This
ACPI ID is used by the BayTrail GPIO (pinctrl) driver to
manage the Low Power Subsystem (LPSS).

Signed-off-by: Paul Drews <paul.drews@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-11-30 15:07:36 +01:00
Linus Walleij f4b3f523b3 pinctrl: nomadik: decomission non-DT boot path
After the patches deleting the last board registering this
pin controller as a platform device has been deleted,
proceed to remove the non-DT boot patch and depend on
OF being available and the device to be coming up by
a DT node.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-26 21:01:58 +01:00
Linus Walleij 8d99339710 pinctrl: nomadik: move platform data handling into driver
This decomissions the platform data header (which is no longer
in use after the systems using this driver were switched to
a pure device-tree config path) and merges the result into
the driver file or local driver header.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-26 21:01:58 +01:00
Denis Carikli b4a87c9b96 pinctrl: pinctrl-imx: add imx25 pinctrl driver
This is mostly cut and paste from the imx35 pinctrl driver.
The data was generated using sed and awk on
  arch/arm/plat-mxc/include/mach/iomux-mx25.h.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Denis Carikli <denis@eukrea.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25 09:08:30 +01:00
Markus Pargmann 31d610f196 pinctrl: imx1-core populate subdevices
Support gpio devicetree subnodes to allow a more detailed DT hardware
description.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25 09:08:30 +01:00
Shawn Guo b9f2f2ecce pinctrl: imx: drop redundant OF dependency
The IMX/MXC selects USE_OF at architecture level, so the OF dependency
at individual SoC pinctrl driver level can just be dropped.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25 09:08:30 +01:00
Linus Walleij 4705845b30 pinctrl: nomadik: always display IRQ in debugfs
As we now grab IRQs also without first reserving the GPIO
line, let's print the mapped IRQ unconditionally in the
debugfs file as well.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25 09:08:30 +01:00
Laurent Pinchart bc41f9f138 sh-pfc: r8a7791: Fix DU pin groups organisation
Rename the sync_1 group to sync as the device has a single sync pin
group for the DU, move the cde_disp mux array right after the
corresponding pins array, and split the clk_in pins in three separate
groups as the pins can be used independently.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25 09:08:29 +01:00
Dan Carpenter d32c3e260f pinctrl: rockchip: missing unlock on error in rockchip_set_pull()
We need to unlock here before returning -EINVAL.

Fixes: 6ca5274d1d ('pinctrl: rockchip: add rk3188 specifics')

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25 09:08:18 +01:00
Dan Carpenter c590854dff pinctrl: abx500: fix some more bitwise AND tests
I sent a patch to fix some bitwise AND tests but I guess I missed some.
Sorry about that.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25 09:08:18 +01:00
Dan Carpenter 38d321c899 pinctrl: rockchip: testing the wrong variable
There is a copy and paste bug so we test "info->reg_base" instead of
"info->reg_pull".

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25 09:08:18 +01:00
Roger Quadros c9b3a7d227 pinctrl: single: call pcs_soc->rearm() whenever IRQ mask is changed
On OMAPs the IO ring must be rearmed each time the pad wakeup
configuration is changed. So call pcs_soc->rearm() from
pcs_irq_set().

As pinctrl-single is now an interrupt controller in some cases,
we should follow the standards and keep the interrupts enabled
constantly, and not just for wake-up events. The tracking of
runtime vs wake-up interrupts can be handled separately for
the automated runtime PM solution when we have it in the
future.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
[tony@atomide.com: removed wrong comment, updated description]
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-11-14 10:43:17 -08:00
Linus Torvalds c2d3306991 GPIO bulk changes for the v3.13 development cycle
- Merged the GPIO descriptor API from Alexandre Courbot.
   This is a first step toward trying to get rid of the
   global GPIO numberspace for the future.
 
 - Add an API so that driver can flag that a certain GPIO
   line is being used by a irqchip backend for generating
   IRQs, so that we can enforce checks, like not allowing
   users to switch that line to an output at runtime, since
   this makes no sense. Implemented corresponding calls
   in a few select drivers.
 
 - ACPI GPIO cleanups, refactorings and switch to using the
   descriptor-based interface.
 
 - Support for the TPS80036 Palmas GPIO variant.
 
 - A new driver for the Broadcom Kona GPIO SoC IP block.
 
 - Device tree support for the PCF857x driver.
 
 - A set of ARM GPIO refactorings with the goal of getting
   rid of a bunch of custom GPIO implementations from the
   arch/arm/* tree:
 
   - Move the IOP GPIO driver to the GPIO subsystem and
     fix all users to use the gpiolib API for accessing
     GPIOs. Delete the old custom GPIO implementation.
 
   - Delete the unused custom PXA GPIO implemention.
 
   - Convert all users of the IXP4 custom GPIO
     implementation to use gpiolib and delete the custom
     implementation.
 
   - Delete the custom Gemini GPIO implementation, also
     completely unused.
 
 - Various cleanups and renamings.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.15 (GNU/Linux)
 
 iQIcBAABAgAGBQJSgNF3AAoJEEEQszewGV1zPiwP/RdQTL8KTe2ULL2QpKAj2TSP
 wuqbvSfW0AOUVf7SvUwXYctxnA718orH2rFKRM9UjK2XFEYgNrtsL4e2Igtbo057
 uZ1sr+dytxgLC67CqkbYTfFxQZZ97ZCO3j8VWtVRxcpMEpoE10Y09ZW7nzvF3Lhq
 0lRd+Cf4KirurOAVfQOVA0Fv+zKuSKSD0i8FLq60li/5EaxXPrYlene4SNY/B+ue
 IWvLJfeDRkv8dR11LYdI/WIET7ljMfIb4MEA5FQ0hae0SSlQtZHQBQi8PjnWnHX0
 n+kxFBFMhWPqBDVwbheD4u6U0RFrm8IVfgdVG94G7wlIQXd5TY4d9Nzd2Y5+bzDF
 THHZiM9PdzU2rjV2QN5gV+AHJuLw/7tSB9pBpcAtKbwb0FFholUDImWI45YoJAdx
 d949YAblh7QZ2nFJJtNgzerco0XAT6BA5/Bs9TPx3L4tij2e+YZzhJbW/EeNmICo
 rE98wUdpV9pk6siv56bsoLowCjNOwaWmI6aYErBdh21mTNx65kwd40xWb3ylM3sy
 X1QC/oLhqxc7Il/KvF9DbGvpgg5QUB1mY9eb2B+gOhRO0cg+qiWvvvqi0dcTHkaT
 aqg7BPXVGUMO73qSsV1x7hmOWsqSFxCBSkVFyWJO7GxqarmWvsXiVh72E85pK60P
 RSyJ/5TghCiGAPFWsg/7
 =881E
 -----END PGP SIGNATURE-----

Merge tag 'gpio-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO changes from Linus Walleij:
 "Here is the bulk of GPIO changes for the v3.13 development cycle.

  I've got ACKs for the things that affect other subsystems (or it's my
  own subsystem, like pinctrl).  Most of that pertain to an attempt from
  my side to consolidate and get rid of custom GPIO implementations in
  the ARM tree.  I will continue doing this.

  The main change this time is the new GPIO descriptor API, background
  for this can be found in Corbet's summary from this january in LWN:

    http://lwn.net/Articles/533632/

  Summary:

   - Merged the GPIO descriptor API from Alexandre Courbot.  This is a
     first step toward trying to get rid of the global GPIO numberspace
     for the future.

   - Add an API so that driver can flag that a certain GPIO line is
     being used by a irqchip backend for generating IRQs, so that we can
     enforce checks, like not allowing users to switch that line to an
     output at runtime, since this makes no sense.  Implemented
     corresponding calls in a few select drivers.

   - ACPI GPIO cleanups, refactorings and switch to using the
     descriptor-based interface.

   - Support for the TPS80036 Palmas GPIO variant.

   - A new driver for the Broadcom Kona GPIO SoC IP block.

   - Device tree support for the PCF857x driver.

   - A set of ARM GPIO refactorings with the goal of getting rid of a
     bunch of custom GPIO implementations from the arch/arm/* tree:

     * Move the IOP GPIO driver to the GPIO subsystem and fix all users
       to use the gpiolib API for accessing GPIOs.  Delete the old
       custom GPIO implementation.

     * Delete the unused custom PXA GPIO implemention.

     * Convert all users of the IXP4 custom GPIO implementation to use
       gpiolib and delete the custom implementation.

     * Delete the custom Gemini GPIO implementation, also completely
       unused.

   - Various cleanups and renamings"

* tag 'gpio-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (85 commits)
  gpio: gpio-mxs: Remove unneeded dt checks
  gpio: pl061: don't depend on CONFIG_ARM
  gpio: bcm-kona: add missing .owner to struct gpio_chip
  gpiolib: provide a declaration of seq_file in gpio/driver.h
  gpiolib: include gpio/consumer.h in of_gpio.h for desc_to_gpio()
  gpio: provide stubs for devres gpio functions
  gpiolib: devres: add missing headers
  gpiolib: make GPIO_DEVRES depend on GPIOLIB
  gpiolib: devres: fix devm_gpiod_get_index()
  gpiolib / ACPI: document the GPIO descriptor based interface
  gpiolib / ACPI: allow passing GPIOF_ACTIVE_LOW for GpioInt resources
  gpiolib / ACPI: add ACPI support for gpiod_get_index()
  gpiolib / ACPI: convert to gpiod interfaces
  gpiolib: add gpiod_get() and gpiod_put() functions
  gpiolib: port of_ functions to use gpiod
  gpiolib: export descriptor-based GPIO interface
  Fixup "MAINTAINERS: GPIO-INTEL-MID: add maintainer"
  gpio: bcm281xx: Don't print addresses of GPIO area in probe()
  gpio: tegra: use new gpio_lock_as_irq() API
  gpio: rcar: Include linux/of.h header
  ...
2013-11-12 15:50:46 +09:00
Linus Torvalds 8a5dc585d5 Main pin control pull request for the v3.13 cycle:
- Blackfin ADI pin control driver, we move yet another
   architecture under this subsystem umbrella.
 
 - Incremental updates to the Renesas Super-H PFC pin control
   driver. New subdriver for the r8a7791 SoC.
 
 - Non-linear GPIO ranges from the gpiolib side of things,
   this enabled simplified device tree bindings by referring
   entire groups of pins on some pin controller to act as
   back-end for a certain GPIO-chip driver.
 
 - Add the Abilis TB10x pin control driver used on the ARC
   architecture. Also the corresponding GPIO driver is merged
   through this tree, so the ARC has full support for pins
   and GPIOs after this.
 
 - Subdrivers for Freescale i.MX1, i.MX27 and i.MX50 pin
   controller instances. The i.MX1 and i.MX27 is an entirely
   new family (silicon) of controllers whereas i.MX50 is
   a variant of the previous supported controller.
 
 - Then the usual slew of fixes, cleanups and incremental
   updates.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.15 (GNU/Linux)
 
 iQIcBAABAgAGBQJSgHrbAAoJEEEQszewGV1zX/gP/R4mAl5rixzu7RDC0nlUHz2S
 F7zf3nhtsAM9GnvJjh9lE43nrisDdCnnBMFeqb7fEr3sp3j+BjQZLp4w/gbkakfY
 6xx6dQ+1+fGojd/gqZI9Le6afpBasAz2E8trariOXW5TmET9ai1y9JCmE2l9K3xA
 jX3h138iUZ4SihBW7c/Ib46TWfe7vaeAF0WKpfNie/uMHYyc+nXQXNNvtzxtk+N3
 +MMuxr9io+d3OyORHD5PlbwWs+jhEPKXfy/isudlkeGbPrA+CMxTCmRc5iu8AvTv
 L0wE6FnBhrdbTUHp9fGmdo1sxmIsijYbbc16yVQOn5kAr/hZvmltjV8efBytEep/
 268ruds2l3TWypaPotuj8Z3Fxm0Jr/+tcQ9Ck8CTMdrGG3J5D78U8fLwVKTcfzJ5
 QjaG0c39MYBbDPO29wfr93MJF7BoNm0D4AyypOCQiH17jL0Q7sXMpeW2WYqlgFf7
 uIWnN3Vsh5V4DcYSCrXoHtts1Wn7i8QEkjyj5gQYvXBU47vGToX5xO6Llvr34lVV
 VGMhivC3f5Z1UmTImwhi+FkfdDVwBYEuiAo3J9ezGvls4Ywq4AjZV/QZB563CztE
 riZ/Xpw3djrxMLKMjGvebTRGpFHcVoh9XV3FetIk+2SCyK7DK1jyYRE1+tvKudAF
 TEIV8476kb7xIVbKt8Oy
 =z9SM
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Main pin control pull request for the v3.13 cycle.

  The changes hitting arch/blackfin are ACKed by the Blackfin
  maintainer, and the device tree bindings are ACKed to the extent
  possible by someone from the device tree maintainers group.

   - Blackfin ADI pin control driver, we move yet another architecture
     under this subsystem umbrella.

   - Incremental updates to the Renesas Super-H PFC pin control driver.
     New subdriver for the r8a7791 SoC.

   - Non-linear GPIO ranges from the gpiolib side of things, this
     enabled simplified device tree bindings by referring entire groups
     of pins on some pin controller to act as back-end for a certain
     GPIO-chip driver.

   - Add the Abilis TB10x pin control driver used on the ARC
     architecture.  Also the corresponding GPIO driver is merged through
     this tree, so the ARC has full support for pins and GPIOs after
     this.

   - Subdrivers for Freescale i.MX1, i.MX27 and i.MX50 pin controller
     instances.  The i.MX1 and i.MX27 is an entirely new family
     (silicon) of controllers whereas i.MX50 is a variant of the
     previous supported controller.

   - Then the usual slew of fixes, cleanups and incremental updates"

The ARC DT changes are apparently still pending, that hopefully gets
sorted out in a timely manner.

* tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
  pinctrl: imx50: add pinctrl support code for the IMX50 SoC
  pinctrl: at91: copy define to driver
  pinctrl: remove minor dead code
  pinctrl: imx: fix using pin->input_val wrongly
  pinctrl: imx1: fix return value check in imx1_pinctrl_core_probe()
  gpio: tb10x: fix return value check in tb10x_gpio_probe()
  gpio: tb10x: use module_platform_driver to simplify the code
  pinctrl: imx27: imx27 pincontrol driver
  pinctrl: imx1 core driver
  pinctrl: sh-pfc: r8a7791 PFC support
  sh-pfc: r8a7778: Add CAN pin groups
  gpio: add TB10x GPIO driver
  pinctrl: at91: correct a few typos
  pinctrl: mvebu: remove redundant of_match_ptr
  pinctrl: tb10x: use module_platform_driver to simplify the code
  pinctrl: tb10x: fix the error handling in tb10x_pinctrl_probe()
  pinctrl: add documentation for pinctrl_get_group_pins()
  pinctrl: rockchip: emulate both edge triggered interrupts
  pinctrl: rockchip: add rk3188 specifics
  pinctrl: rockchip: remove redundant check
  ...
2013-11-12 15:40:03 +09:00
Greg Ungerer 9da8312048 pinctrl: imx50: add pinctrl support code for the IMX50 SoC
Add code to support the specific pin arrangements of the Freescale IMX50 SoC.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-06 10:06:59 +01:00
Linus Walleij 94daf85e3c pinctrl: at91: copy define to driver
The #define for the maximum number of GPIO blocks was retrieved
into pinctrl-at91.c by implicit inclusion of <mach/gpio.h>
from <linux/gpio.h> creating a dependency on machine-local
<mach/gpio.h>. Break the depenency by copying this single
define into the driver.

Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-05 10:54:27 +01:00
Michael Opdenacker 808e657c5c pinctrl: remove minor dead code
This removes a test whether the 'desc' variable is NULL.
This possibility has already been eliminated by the
below test earlier in the loop:

                if (desc == NULL) {
                        dev_warn(pctldev->dev,
                                 "could not get pin desc for pin %d\n",
                                 pins[i]);
                        continue;
                }

Found with Coverity: CID #1090078

Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-04 13:07:05 +01:00
Peter Chen a3183c60e3 pinctrl: imx: fix using pin->input_val wrongly
The commit: "pinctrl: imx: Use struct type for pins" relaced
pin->input_reg by pin->input_val wrongly, fix it at this commit.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-04 13:04:26 +01:00
Linus Walleij de91a3789d Merge branch 'pinmux/next/pfc' of git://linuxtv.org/pinchartl/fbdev into devel 2013-11-04 13:02:37 +01:00
Wei Yongjun 5e1109adde pinctrl: imx1: fix return value check in imx1_pinctrl_core_probe()
In case of error, the function devm_ioremap_nocache() returns NULL
pointer not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-04 12:49:56 +01:00
Markus Pargmann e16dbf6011 pinctrl: imx27: imx27 pincontrol driver
imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-29 08:58:06 -07:00
Markus Pargmann 30612cd900 pinctrl: imx1 core driver
Core driver for register formats of imx1/imx21/imx27 processors.

The pins of those processors are grouped into ports. Each port has 32
pins. The pins mux configuration is controlled by registers with 1 or 2
bit per pin, depending on the specific control register.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-29 06:54:37 -07:00
Hisashi Nakamura 5088451962 pinctrl: sh-pfc: r8a7791 PFC support
Add PFC support for the r8a7791 SoC V2 including pin groups for
on-chip devices such as MSIOF, SCIF, USB, MMC, SDHI, DU.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Kunihito Higashiyama <kunihito.higashiyama.ur@renesas.com>
Signed-off-by: Yoshikazu Fujikawa <yoshikazu.fujikawa.ue@renesas.com>
Signed-off-by: Nobuyuki HIRAI <nobuyuki.hirai.xe@renesas.com>
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
[damm@opensource.se: Forward ported to upstream, minor fixes]
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-10-27 16:40:52 +01:00
Sergei Shtylyov 24799c22ae sh-pfc: r8a7778: Add CAN pin groups
Add CAN data and clock pin groups to R8A7778 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-10-27 16:40:51 +01:00
Alexandre Belloni 61e310a1ed pinctrl: at91: correct a few typos
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-23 11:07:21 +02:00
Sachin Kamat f2e9394d1a pinctrl: mvebu: remove redundant of_match_ptr
The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-23 10:55:04 +02:00
Wei Yongjun 7ddd183738 pinctrl: tb10x: use module_platform_driver to simplify the code
module_platform_driver() makes the code simpler by eliminating
boilerplate code.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-23 10:46:00 +02:00
Wei Yongjun 86467ff2dd pinctrl: tb10x: fix the error handling in tb10x_pinctrl_probe()
This patch fix the error handling in tb10x_pinctrl_probe():
 - devm_ioremap_resource() return ERR_PTR() and never return NULL
 - remove the dev_err call to avoid redundant error message
 - pinctrl_register() returns NULL not ERR_PTR()

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-23 10:41:22 +02:00
Tony Lindgren 1b9c0fb365 pinctrl: single: Fix build when not built on ARM
Looks like we need a little bit of arch specific handling
with the generic IRQ. Fix the issue with an ifdef the
same way as other drivers do.

ARM needs things set to IRQF_VALID, which also then sets
noprobe. Others seem to use just irq_set_noprobe().

Otherwise we can get:

drivers/pinctrl/pinctrl-single.c: In function 'pcs_irqdomain_map':
drivers/pinctrl/pinctrl-single.c:1750:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration]
drivers/pinctrl/pinctrl-single.c:1750:21: error: 'IRQF_VALID' undeclared (first use in this function)
drivers/pinctrl/pinctrl-single.c:1750:34: error: 'IRQF_PROBE' undeclared (first use in this function)

Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-18 16:43:06 -07:00
Heiko Stübner 5a92750133 pinctrl: rockchip: emulate both edge triggered interrupts
The gpio interrupt controller on Rockchip socs can do edge triggers only
for single edges but not both. Nevertheless a lot of gpio users rely on
the availability of both-edge triggered interrupts - i.e. gpio-keys.

Therefore implement a solution similar to pinctrl-coh901 re-setting the
triggering edge depending on the gpio value in the interrupt demuxer.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:55 +02:00
Heiko Stübner 6ca5274d1d pinctrl: rockchip: add rk3188 specifics
Besides the pull registers sitting in a separate place, the rk3188 also
has the peculiarity that the pull registers of the first bank are split
and the first half is sitting in the register space of the pmu.

Therefore this adds a special bank-type for the first bank, to handle
the two register sources.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:54 +02:00
Heiko Stübner d1358f90e3 pinctrl: rockchip: remove redundant check
The check limiting bias options to supported ones is already
done thru rockchip_pinconf_pull_valid. Therefore this check is
redundant and can be removed.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:53 +02:00
Heiko Stübner 65fca613b0 pinctrl: rockchip: add support for multiple bank types
There are Rockchip SoCs, namely the rk3188, that combine a set of
regular banks with banks that need special handling for some settings.

Therefore add the possibility for the driver to handle more than one
bank type.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:53 +02:00
Heiko Stübner a282926d65 pinctrl: rockchip: separate different sub-types more
Further investigation of the different Rockchip SoCs showed that
the differences especially in the pull settings are quite deep.
As further patches will show, the register layout for the pulls of
the rk3188 is quite strange. Also it is to assume, that later
Rockchip SoCs may introduce even more quirks in this regard, making
it hard to support all of those using the current generic pull_*
variables.

Therefore move the driver to hold the type of controller in an enum
and do the handling according to it in the necessary places. Also
instead of calculating the register in the get and set pull functions
move it to a type-specific callback.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:52 +02:00
Roel Kluin 6d0a4ed2b9 pinctrl: dove: unset twsi option3 for gconfig as well
This fixes a typo which left twsi config3 option enabled.

Cc: stable@vger.kernel.org
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:51 +02:00
Christian Ruppert 5aad0db1c1 pinctrl: add TB10x pin control driver
The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs.
Used to control the pinmux and is a prerequisite for the GPIO driver.

Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:51 +02:00
Christian Ruppert 586a87e6ed pinctrl/gpio: non-linear GPIO ranges accesible from gpiolib
This patch adds the infrastructure required to register non-linear gpio
ranges through gpiolib and the standard GPIO device tree bindings.

Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:50 +02:00
Linus Walleij 263c43a447 Linux 3.12-rc4
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQEcBAABAgAGBQJSUc9zAAoJEHm+PkMAQRiG9DMH/AtpuAF6LlMRPjrCeuJQ1pyh
 T0IUO+CsLKO6qtM5IyweP8V6zaasNjIuW1+B6IwVIl8aOrM+M7CwRiKvpey26ldM
 I8G2ron7hqSOSQqSQs20jN2yGAqQGpYIbTmpdGLAjQ350NNNvEKthbP5SZR5PAmE
 UuIx5OGEkaOyZXvCZJXU9AZkCxbihlMSt2zFVxybq2pwnGezRUYgCigE81aeyE0I
 QLwzzMVdkCxtZEpkdJMpLILAz22jN4RoVDbXRa2XC7dA9I2PEEXI9CcLzqCsx2Ii
 8eYS+no2K5N2rrpER7JFUB2B/2X8FaVDE+aJBCkfbtwaYTV9UYLq3a/sKVpo1Cs=
 =xSFJ
 -----END PGP SIGNATURE-----

Merge tag 'v3.12-rc4' into devel

Linux 3.12-rc4
2013-10-16 10:05:53 +02:00
Linus Walleij 873ee9ed2c pinctrl: coh901: mark GPIO lines used for IRQ
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 09:59:55 +02:00
Linus Walleij 494336f3a6 pinctrl: nomadik: mark GPIO lines used for IRQ
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.

Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 09:59:55 +02:00
Tony Lindgren dc7743aa3c pinctrl: single: Add support for auxdata
For omaps, we still have dependencies to the legacy code
for handling the PRM (Power Reset Management) interrupts,
and also for reconfiguring the io wake-up chain after
changes.

Let's pass the PRM interrupt and the rearm functions via
auxdata. Then when at some point we have a proper PRM
driver, we can get the interrupt via device tree and
set up the rearm function as exported function in the
PRM driver.

By using auxdata we can remove a dependency to the
wake-up events for converting omap3 to be device
tree only.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Prakash Manjunathappa <prakash.pm@ti.com>
Cc: Roger Quadros <rogerq@ti.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-10 15:30:47 -07:00
Tony Lindgren 3e6cee1786 pinctrl: single: Add support for wake-up interrupts
The pin control registers can have interrupts for example
for device wake-up. These interrupts can be treated as a
chained interrupt controller as suggested earlier by
Linus Walleij <linus.walleij@linaro.org>.

This patch adds support for interrupts in a way that
should be pretty generic, and works for the omaps that
support wake-up interrupts. On omaps, there's an
interrupt enable and interrupt status bit for each pin.
The two pinctrl domains on omaps share a single interrupt
from the PRM chained interrupt handler. Support for
other similar hardware should be easy to add.

Note that this patch does not attempt to handle the
wake-up interrupts automatically unlike the earlier
patches. This patch allows the device drivers to do
a request_irq() on the wake-up pins as needed. I'll
try to do also a separate generic patch for handling
the wake-up events automatically.

Also note that as this patch makes the pinctrl-single
an irq controller, the current bindings need some
extra trickery to use interrupts from two different
interrupt controllers for the same driver. So it
might be worth waiting a little on the patches
enabling the wake-up interrupts from drivers as there
should be a generic way to handle it coming. And also
there's been discussion of interrupts-extended binding
for using interrupts from multiple interrupt controllers.

In any case, this patch should be ready to go allowing
handling the wake-up interrupts in a generic way, or
separately from the device drivers.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Prakash Manjunathappa <prakash.pm@ti.com>
Cc: Roger Quadros <rogerq@ti.com>
Cc: linux-kernel@vger.kernel.org
Cc: Benoît Cousson <bcousson@baylibre.com>
Cc: devicetree@vger.kernel.org
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-10 15:30:30 -07:00
Laxman Dewangan c8ce878206 pincntrl: add support for ams AS3722 pin control driver
The AS3722 is a compact system PMU suitable for mobile phones, tablets etc.

Add a driver to support accessing the GPIO, pinmux and pin configuration
of 8 GPIO pins found on the ams AS3722 through pin control driver and
gpiolib.

The driver will register itself as the pincontrol driver and gpio driver.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-10 17:38:29 +02:00
Tony Lindgren 02e483f66d pinctrl: single: Prepare for supporting SoC specific features
Let's replace is_pinconf with flags and add struct pcs_soc_data
so we can support SoC specific features like pin wake-up events.

Done in collaboration with Roger Quadros <rogerq@ti.com>.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Prakash Manjunathappa <prakash.pm@ti.com>
Cc: linux-kernel@vger.kernel.org
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-09 14:47:54 -07:00
Sonic Zhang d3224ed140 pinctrl: pinctrl-adi2: disable IRQ when setting value
GPIO output value should be set after the GPIO interrupt is disabled.
Use BIT macro as well.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
[Edited commit message]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-09 13:09:41 +02:00
Sonic Zhang 010c51e189 pinctrl: pinctrl-adi2: Remove nested lock+irqsave that resue flags.
Also avoid use NULL pointer in error message.

v2-changes:
- use port pinter only after checking

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-09 13:07:05 +02:00
Laxman Dewangan a047914e7f pinctrl: palmas: remove pin config BIAS_PULL_PIN_DEFAULT support
Palmas devices do not support the default bias configuration
and hence removing this option from valid pin config parameters.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-08 13:27:27 +02:00
Linus Walleij bfabb59433 Linux 3.12-rc4
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQEcBAABAgAGBQJSUc9zAAoJEHm+PkMAQRiG9DMH/AtpuAF6LlMRPjrCeuJQ1pyh
 T0IUO+CsLKO6qtM5IyweP8V6zaasNjIuW1+B6IwVIl8aOrM+M7CwRiKvpey26ldM
 I8G2ron7hqSOSQqSQs20jN2yGAqQGpYIbTmpdGLAjQ350NNNvEKthbP5SZR5PAmE
 UuIx5OGEkaOyZXvCZJXU9AZkCxbihlMSt2zFVxybq2pwnGezRUYgCigE81aeyE0I
 QLwzzMVdkCxtZEpkdJMpLILAz22jN4RoVDbXRa2XC7dA9I2PEEXI9CcLzqCsx2Ii
 8eYS+no2K5N2rrpER7JFUB2B/2X8FaVDE+aJBCkfbtwaYTV9UYLq3a/sKVpo1Cs=
 =xSFJ
 -----END PGP SIGNATURE-----

Merge tag 'v3.12-rc4' into devel

Linux 3.12-rc4
2013-10-08 13:27:11 +02:00
Rong Wang 6a08a92ec4 pinctrl: sirf: add USB1/UART1 pinmux usb/uart share
dn and dp of USB1 can share with UART1(UART1 can route rx,tx to dn and dp pins of USB1).
here we add this pinmux capability.
USB1/UART1 mode selection has dedicated control register in RSC module, here we attach
the register offset of private data of related pin groups.

Signed-off-by: Rong Wang <Rong.Wang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-08 10:19:26 +02:00
Qipan Li af614b2301 pinctrl: sirf: add lost USP-based UART pin groups for prima2
USP(Universal Serial Ports) can be UART as commit 5df831117b,
this patch defines the USP-based UART function pin groups for prima2.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-08 10:18:15 +02:00
Qipan Li fb85f4290d pinctrl: sirf: add lost uart0-no-stream-control pingroup for prima2
the old codes defined uart0_nostreamctrl_pins, but missed pingroup
and padmux definition for it. this patch fixes it.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-08 10:16:34 +02:00
Sachin Kamat 606fca94f7 pinctrl: remove redundant of_match_ptr
The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.

This is a squash commit of:
pinctrl: at91: Remove redundant of_match_ptr
pinctrl: exynos5440: Remove redundant of_match_ptr
pinctrl: imx35: Remove redundant of_match_ptr
pinctrl: imx51: Remove redundant of_match_ptr
pinctrl: imx53: Remove redundant of_match_ptr
pinctrl: imx6dl: Remove redundant of_match_ptr
pinctrl: imx6q: Remove redundant of_match_ptr
pinctrl: samsung: Remove redundant of_match_ptr
pinctrl: vf610: Remove redundant of_match_ptr
pinctrl: imx6sl: Remove redundant of_match_ptr
pinctrl: plgpio: Remove redundant of_match_ptr

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-08 10:02:25 +02:00
Laxman Dewangan 7fd9ddd5f7 pinctrl: palmas: do not abort pin configuration for BIAS_DEFAULT
Recent movement of all configurations of pin in the single call of
pin_config_set(), it is aborting configuration if BIAS_PULL_PIN_DEFAULT
is selected as return of configuration.

The original idea was to just avoid any update on register for pull up/down
configuration if this option is selected.

Fixing this by just bypassing any register update for BIAS_PULL_PIN_DEFAULT
and continuing the remaining configuration.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-27 16:22:43 +02:00
Linus Walleij fdc07cc13a Merge branch 'pinmux/next' of git://linuxtv.org/pinchartl/fbdev into devel 2013-09-27 15:58:56 +02:00
Laxman Dewangan 6090e9a6ea pinctrl: palmas: remove non-require function
Palmas pinmux and pin configuration support the single pin level
configuration in place of pin group.

Hence it is only require to pin_config_{set|get} and do not require
pin_config_group_{set|get}. As core framework already check for
require APIs availability, it is not require to implement as dummy
for non-require ops and so removing it.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-27 15:53:12 +02:00
Mateusz Krawczuk 4880292556 pinctrl: Correct number of pins for s5pv210
Values of pins in table s5pv210 bank are incorrect. This patch correct values.

Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-27 15:50:22 +02:00
Axel Lin fe4315c3b0 pinctrl: adi2: Fix dead lock in adi_gpio_direction_output
Current code hold port->lock spinlock and then try to grab the lock again
in adi_gpio_set_value(). Fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-27 14:19:59 +02:00
Axel Lin c8690d6d29 pinctrl: adi2: Convert to devm_ioremap_resource
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-27 14:18:54 +02:00
Boris BREZILLON c8dba02e7d pinctrl: at91: fix sam9x5 debounce/deglitch functions
Replace at91_mux_get_deglitch with at91_mux_pio3_get_deglitch when using
sam9x5 (pio3) IP.
at91_mux_get_deglitch only test the activation of the "Input Filter" which
may be overloaded by the activation of the "Input Filter Slow Clock" to use
the input filter as a debounce filter instead of a deglitch filter.

Fix at91_mux_pio3_get_debounce to test the activation of the Input Filter
before testing the activation of the debounce filter (Input Filter Slow
Clock depends on Input Filter).

Fix at91_mux_pio3_set_debounce function to avoid disabling the deglitch
filter ("Input Filter") when debounce filter is disabled.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-27 14:11:34 +02:00
Boris BREZILLON 77966ad7b6 pinctrl: at91: fix typos
Fix AT91_PINCTRL_DEBOUNCE_VAL dt macro typo.
Fix at91_pinctrl_mux_ops callback typos.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-27 14:10:09 +02:00
Guennadi Liakhovetski f6aaaac999 sh-pfc: r8a7790: add pin definitions for the I2C3 interface
There are four I2C interfaces on r8a7790, each of them can be connected to
one of the two respective I2C controllers, e.g. interface #0 can be
configured to work with I2C0 or with IIC0. Additionally some of those
interfaces can also use one of several pin sets. Interface #3 is special,
because it can be used in automatic mode for DVFS. It only has one set
of pins available and those pins cannot be used for anything else, they
also lack the GPIO function.

This patch uses the sh-pfc ability to configure pins, not associated with
GPIOs and adds support for I2C3 to the r8a7790 PFC set up.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-09-27 02:03:52 +02:00
Ulrich Hecht 70702bfc13 sh-pfc: r8a7790: Add I2C pin groups and functions
Adds pinmux for i2c bus 1 and 2. (Pins for 0 and 3 are not multiplexed.)

Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-09-24 12:23:42 +02:00
Kuninori Morimoto 3ad8219a50 sh-pfc: r8a7778: Add SRU/SSI pin support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-09-24 12:23:42 +02:00
Linus Walleij cfa8b3f54e Merge branch 'devel' into for-next 2013-09-23 11:26:59 +02:00
Dan Carpenter 81d36c4fff pinctrl: remove an unnecessary cast
sizeof() is already size_t so there is no need to cast here.  Generally,
casting inside the min() macro instead of using min_t() is considered
bad style.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-23 10:47:14 +02:00
Vincent Stehlé 3b59e432ec pinctrl: fix pinconf_dbg_config_write return type
Have pinconf_dbg_config_write() return a ssize_t. This fixes the following
compilation warning:

  drivers/pinctrl/pinconf.c:617:2: warning: initialization from incompatible pointer type [enabled by default]
  drivers/pinctrl/pinconf.c:617:2: warning: (near initialization for ‘pinconf_dbg_pinconfig_fops.write’) [enabled by default]

Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-23 10:47:03 +02:00
Sonic Zhang 7330e345ee pinctrl: pinctrl-adi2-bf60x: remove useless and duplicated GPIO definition for PPI2.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-23 09:45:33 +02:00
Sonic Zhang 9d7278d0b4 pinctrl: pinctrl-adi2: Add dependency to arch BLACKFIN in Kconfig.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-23 09:43:04 +02:00
Sonic Zhang e9a03add0c pinctrl: ADI PIN control driver for the GPIO controller on bf54x and bf60x.
The new ADI GPIO2 controller was introduced since the BF548 and BF60x
processors. It differs a lot from the old one on BF5xx processors. So,
create a pinctrl driver under the pinctrl framework.

- Define gpio ports and pin interrupt controllers as individual platform
  devices.
- Register a pinctrl driver for the whole GPIO ports and pin interrupt
  devices.
- Probe pint devices before port devices. Put device instances into
  the global gpio and pint lists.
- Define peripheral, irq and gpio reservation bit masks for each gpio
  port as runtime resources.
- Save and restore gpio port and pint status MMRs in syscore PM functions.
- Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
  and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
  in pin controller probe function. Get the pin groups and functions via
  the soc data reference.
- Call gpiochip_add_pin_range() in gpio device probe function to register
  range cross reference between gpio device and pin control device.
- Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object
  by container_of() and find adi_pinctrl by pin control device name.
- Handle peripheral and gpio requests in pinctrl operation functions.
- Demux gpio IRQs via the irq_domain created by each GPIO port.

v2-changes:
- Remove unlinke() directive.

v3-changes:
- Rename struct adi_pmx to adi_pinctrl.
- Fix the comments of struct gpio_pint.
- Remove unused pin_base in struct gpio_port.
- Change pint_assign into bool type.
- Add comments about the relationship between pint device and port device
to the driver header.
- Use BIT macro to shift bit.
- Remove all bitmap reservation help functions. Inline reservation functions
into the actual code.
- Remove gpio and offset mutual reference help functions.
- Remove all help functions to find gpio_port and adi_pinctrl structs. Get
range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by
container_of() and find adi_pinctrl by pin control device name.
- Pass bool type usage variable to port_setup help function.
- Separate long bit operations into several lines and add comments.
- Use debugfs to output all GPIO request information.
- Avoid to set drvdata to NULL
- Add explanation to function adi_gpio_init_int()
- Call gpiochip_add_pin_range() in gpio device probe function to register
range cross reference between gpio device and pin control device.
- Remove the reference to pin control device from the gpio_port struct.
Remove the reference list to gpio device from the adi_pinctrl struct.
Replace the global adi_pinctrl list with adi_gpio_port_list. Walk through
the gpio list to do power suspend and resume operations.
- Remove the global GPIO base from struct adi_pinctrl, define pin base in
the platform data for each GPIO port device.
- Initialize adi_pinctrl_setup in arch_initcall().
- print the status of triggers, whether it is in GPIO mode, if it is
flagged to be used as IRQ, etc in adi_pin_dbg_show().
- Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
in pin controller probe function. Get the pin groups and functions via
the soc data reference.

v4-changes:
- remove useless system_state checking.
- replace dev_err with dev_warn in both irq and gpio pin cases.
- comment on relationship between irq type and invert operation.
- It is not necessary to check the reservation mode of the requested
pin in IRQ chip operation. Remove the reservation map.
- Use existing gpio/pinctrl subsystem debugfs files. Remove pinctrl-adi2
driver specific debugfs output.
- Add linkport group and function information for bf60x.
- Separate uart and ctsrts pins into 2 groups.
- Separate APAPI and alternative ATAPI pins into 2 groups.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-19 14:37:27 +02:00
Thierry Reding de059be983 pinctrl: tegra114: Remove MODULE_ALIAS
The driver cannot be built as a module, so having a MODULE_ALIAS() isn't
useful.

While at it, fix a small typo in the file header comment and make the
module description string consistent with those for earlier Tegra SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-19 14:35:24 +02:00
Linus Torvalds 27703bb4a6 PTR_RET() is a weird name, and led to some confusing usage. We ended
up with PTR_ERR_OR_ZERO(), and replacing or fixing all the usages.
 
 This has been sitting in linux-next for a whole cycle.
 
 Thanks,
 Rusty.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJSJo+1AAoJENkgDmzRrbjxIC4QALJK95o8AUXuwUkl+2fmFkUt
 hh2/PJ1vDYgk4Xt0J6hyoK7XMa0H1RkbBrROuDdsBnorMFpEsGcgdkUZte9ufoAS
 97Bg+7N0KPbTB/S8vOwtW1vbERTJIVPN2uf6h1Wqm9Xc2puCh3HbMMr1AWMGu0WQ
 NqY5+Zz8zecy1UOrMhEP6H1CjeQcL1w1DO6YM5ydeqlKNzAz+JMfDXriLPDwiE7+
 XFPDF/O3Vtd2ckA7L70Lio7hfHwxV5U4WwFVfiwls98XB4jcZqDKIoh1r8z4SRgR
 +0Rae2DN3BaOabGMr//5XdrzQVpwJTh5m2w8BAOHJvCJ9HR7Sq29UIN4u+TowZBy
 L2xYo4dvFxkympwu5zEd3c7vHYWKIaqmSq5PIjr4gF/uIo2OeOTrpPIK782ZEYb7
 e+qUgOEM05V9AmQZCrSZeP9u474Sj8ow3sCtWxfdRtwNfoEIcUXsNNJd/zDHlVtW
 cEtXqc2xXIpcuUJQWlSaGp8fmRQjVZPzrLKYLM2m39ZcOOJbf5rzQAYS7hHPosIa
 SK+YVux/+Zzi+Xo/vXq1OlM/SruCr5S7JOgCxLowoQ88vupgXME6uPyC8EO+QQ50
 GsrHes5ZNLbk0uVsfcexIyojkUnyvDmmnDpv+1zdC6RgZLJQn8OXp5yNhHhnhrFT
 BiHX6YFWtDDqRlVv8Q0F
 =LeaW
 -----END PGP SIGNATURE-----

Merge tag 'PTR_RET-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux

Pull PTR_RET() removal patches from Rusty Russell:
 "PTR_RET() is a weird name, and led to some confusing usage.  We ended
  up with PTR_ERR_OR_ZERO(), and replacing or fixing all the usages.

  This has been sitting in linux-next for a whole cycle"

[ There are still some PTR_RET users scattered about, with some of them
  possibly being new, but most of them existing in Rusty's tree too.  We
  have that

      #define PTR_RET(p) PTR_ERR_OR_ZERO(p)

  thing in <linux/err.h>, so they continue to work for now  - Linus ]

* tag 'PTR_RET-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux:
  GFS2: Replace PTR_RET with PTR_ERR_OR_ZERO
  Btrfs: volume: Replace PTR_RET with PTR_ERR_OR_ZERO
  drm/cma: Replace PTR_RET with PTR_ERR_OR_ZERO
  sh_veu: Replace PTR_RET with PTR_ERR_OR_ZERO
  dma-buf: Replace PTR_RET with PTR_ERR_OR_ZERO
  drivers/rtc: Replace PTR_RET with PTR_ERR_OR_ZERO
  mm/oom_kill: remove weird use of ERR_PTR()/PTR_ERR().
  staging/zcache: don't use PTR_RET().
  remoteproc: don't use PTR_RET().
  pinctrl: don't use PTR_RET().
  acpi: Replace weird use of PTR_RET.
  s390: Replace weird use of PTR_RET.
  PTR_RET is now PTR_ERR_OR_ZERO(): Replace most.
  PTR_RET is now PTR_ERR_OR_ZERO
2013-09-04 17:31:11 -07:00
Axel Lin c9e3b2d8f7 pinctrl: sunxi: Fix off-by-one for valid offset range checking
The valid offset range should be 0 ... chip->ngpio - 1.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-30 10:37:36 +02:00
Linus Walleij 07b7eb9279 pinctrl: sunxi: drop lock on error path
I forgot to drop the lock for the return inside the loop
protected by the spinlock in the pin config routine when
merging in -rc7 in commit 6ad30ce046

Reported-by: Sherman Yin <syin@broadcom.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-30 09:57:27 +02:00
Axel Lin acf564a8f3 pinctrl: pinconf-generic: Remove ti prefix in dev_err messages
It does not make sense to show ti prefix in pinconf_generic_dt_subnode_to_map()
dev_err messages.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-29 09:48:13 +02:00
Linus Walleij 6ad30ce046 Linux 3.11-rc7
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.19 (GNU/Linux)
 
 iQEcBAABAgAGBQJSGqS5AAoJEHm+PkMAQRiGFxEH/3VrqF6WAkcviNiW/0DCdO8k
 v6Wi7Sp5LxVkwzmOCHCV1tTHwLRlH3cB9YmJlGQ0kHCREaAuEQAB0xJXIW7dnyYj
 Qq7KoRZEMe3wizmjEsj8qsrhfMLzHjBw67hBz2znwW/4P7YdgzwD7KRiEat+yRC9
 ON3nNL2zIqpfk92RXvVrSVl4KMEM+WNbOfiffgBiEP24Ja1MJMFH1d4i6hNOaB0x
 9Pb3Lw8let92x+8Ao5jnjKdKMgVsoZWbN/TgQR8zZOHM38AGGiDgk18vMz+L+hpS
 jqfjckxj1m30jGq0qZ9ZbMZx3IGif4KccVr30MqNHJpwi6Q24qXvT3YfA3HkstM=
 =nAab
 -----END PGP SIGNATURE-----

Merge tag 'v3.11-rc7' into devel

Merged in this to avoid conflicts with the big locking fixes
from upstream.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Conflicts:
	drivers/pinctrl/pinctrl-sunxi.c
2013-08-29 09:46:30 +02:00
Axel Lin 0351c28795 pinctrl: rockchip: Implement .request() and .free() callbacks
Implement .request() and .free() callbacks on the GPIO chips to
inform pinctrl when a GPIO is requested or freed.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-29 09:11:00 +02:00
Boris BREZILLON 05d3534a32 pinctrl: at91: fix get_pullup/down function return
In PIO_PUSR and PIO_PPDSR register if a given bit is set 1 this means the
pullup/down for this pin (pin is represented as a bit position) is
disabled.

Cc: stable <stable@vger.kernel.org> # 3.8+
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 21:21:42 +02:00
Jingoo Han db8ed17429 pinctrl: sh-pfc: remove unnecessary platform_set_drvdata()
The driver core clears the driver data to NULL after device_release
or on probe failure. Thus, it is not needed to manually clear the
device driver data to NULL.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 21:14:37 +02:00
Mateusz Krawczuk 608a26a7bc pinctrl: Add s5pv210 support to pinctrl-exynos
This patch implements pinctrl support and adds device tree bindings
for s5pv210.

Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 15:56:06 +02:00
Laxman Dewangan 2f62eb9d64 pinctrl: utils: include export.h to avoid warnings
Include "linux/export.h" to avoid following warnings during compilation:

/***
pinctrl/pinctrl-utils.c:53:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:53:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:53:1: warning: parameter names (without types) in function declaration [enabled by default]
pinctrl/pinctrl-utils.c:70:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:70:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:70:1: warning: parameter names (without types) in function declaration [enabled by default]
pinctrl/pinctrl-utils.c:98:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:98:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:98:1: warning: parameter names (without types) in function declaration [enabled by default]
pinctrl/pinctrl-utils.c:122:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:122:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:122:1: warning: parameter names (without types) in function declaration [enabled by default]
pinctrl/pinctrl-utils.c:135:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:135:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:135:1: warning: parameter names (without types) in function declaration [enabled by default]
**/

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 15:50:33 +02:00
Dan Carpenter 774e2d981f pinctrl: s3c24xx: off by one in s3c24xx_eint_init()
If "irq == NUM_EINT" then it writes one space beyond the end of the
eint_data->domains[] array.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 14:44:25 +02:00
Dan Carpenter ddb6c45fb7 pinctrl: mvebu: testing the wrong variable
We wanted to test "*map" here instead of "map".

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 14:35:44 +02:00
Dan Carpenter 6da33dbdcb pinctrl: abx500: fix bitwise AND test
The intent here was to test if the bit was set or not but there is a
logical vs bitwise AND typo so it is true if any bits are set.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 14:32:06 +02:00
Jisheng Zhang a8a364bd27 pinctrl: mvebu: Convert to use devm_ioremap_resource
The resource mapped by of_iomap() isn't unmapped in error path. This
patch fix the resource leakage by using devm_ioremap_resource() instead
of of_iomap().

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 14:17:44 +02:00
Sherman Yin 03b054e969 pinctrl: Pass all configs to driver on pin_config_set()
When setting pin configuration in the pinctrl framework, pin_config_set() or
pin_config_group_set() is called in a loop to set one configuration at a time
for the specified pin or group.

This patch 1) removes the loop and 2) changes the API to pass the whole pin
config array to the driver.  It is now up to the driver to loop through the
configs.  This allows the driver to potentially combine configs and reduce the
number of writes to pin config registers.

All c files changed have been build-tested to verify the change compiles and
that the corresponding .o is successfully generated.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:34:41 +02:00
Axel Lin f5ba9c52bf pinctrl: tz1090-pdc: Convert to devm_ioremap_resource
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:34:19 +02:00
Axel Lin 6fc6c61c99 pinctrl: tz1090: Convert to devm_ioremap_resource
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:34:19 +02:00
Axel Lin 394a8ff8bb pinctrl: tegra: Convert to devm_ioremap_resource
Using the new devm_ioremap_resource() we can greatly simplify resource handling.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:34:18 +02:00
Axel Lin 51578b9b1f pinctrl: rockchip: Simplify pin_to_bank equation
If (b->pin_base + b->nr_pins - 1) < pin is true, pin >= b->pin_base is always
true because b->nr_pins is never less than 0.
Thus this patch simplify the equation.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:34:18 +02:00
Axel Lin dff5a99c2a pinctrl: spear: Convert to devm_ioremap_resource
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:34:18 +02:00
Axel Lin 0be9e70d58 pinctrl: rockchip: Remove of_match_ptr macro for DT only driver
This is a DT only driver and rockchip_pinctrl_dt_match is always compiled in.
Thus remove of_match_ptr macro.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:16:22 +02:00
Axel Lin 63ca8db757 pinctrl: palmas: PINCTRL_PALMAS needs to select PINMUX
Fix below build error if !PINMUX.

  CC      drivers/pinctrl/pinctrl-palmas.o
drivers/pinctrl/pinctrl-palmas.c:741:21: error: variable 'palmas_pinmux_ops' has initializer but incomplete type
drivers/pinctrl/pinctrl-palmas.c:742:2: error: unknown field 'get_functions_count' specified in initializer
drivers/pinctrl/pinctrl-palmas.c:742:2: warning: excess elements in struct initializer [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:742:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:743:2: error: unknown field 'get_function_name' specified in initializer
drivers/pinctrl/pinctrl-palmas.c:743:2: warning: excess elements in struct initializer [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:743:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:744:2: error: unknown field 'get_function_groups' specified in initializer
drivers/pinctrl/pinctrl-palmas.c:744:2: warning: excess elements in struct initializer [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:744:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:745:2: error: unknown field 'enable' specified in initializer
drivers/pinctrl/pinctrl-palmas.c:745:2: warning: excess elements in struct initializer [enabled by default]
drivers/pinctrl/pinctrl-palmas.c:745:2: warning: (near initialization for 'palmas_pinmux_ops') [enabled by default]
make[2]: *** [drivers/pinctrl/pinctrl-palmas.o] Error 1
make[1]: *** [drivers/pinctrl] Error 2
make: *** [drivers] Error 2

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:14:37 +02:00
Axel Lin 9b77ace409 pinctrl: core: Add proper mutex lock in pinctrl_request_gpio
This one is missed in commit 42fed7ba "pinctrl: move subsystem mutex to
pinctrl_dev struct".

I think this fixes the race between pin_free() and pin_request() calls.
It protects accessing the members of pctldev->desc.
(e.g. update desc->mux_usecount, desc->gpio_owner, desc->mux_owner, etc)
Current code grabs pctldev->mutex before calling pinmux_free_gpio(),
but did not grab the mutex while calling pinmux_request_gpio().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:13:05 +02:00
Sascha Hauer 406044695f pinctrl: imx: Fix compilation with DEBUG enabled
This became broken with converting the pinmux arrays into struct
types. While at it replace the preprocessor magic with a simple
dev_dbg.

Reported-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 20:52:46 +02:00
Axel Lin 1cb9539587 pinctrl: rockchip: Simplify for loop iteration
Just return once a match found makes the code simpler and shorter.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:32 +02:00
Laxman Dewangan 1ede12d491 pinctrl: tegra: use pinctrl-utils APIs for mapping
Pin control utility functions provides the function for creating
map lists.

In place of implementing APIs locally in Tegra pin control driver
for creating map lists, use the utility functions. This reduces
the code size and avoid duplication.

Changes from V1:
- Rebased change on top of V1.
- Use pinctrl_utils_dt_free_map

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:32 +02:00
Laxman Dewangan 3287c24088 pinctrl: utils : add support to pass config type in generic util APIs
Add support to pass the config type like GROUP or PIN when using
the utils or generic pin configuration APIs. This will make the
APIs more generic.

Added additional inline APIs such that it can be use directly as
callback for the pinctrl_ops.

Changes from V1:
- Remove separate implementation for pins and group for
  pinctrl_utils_dt_free_map and improve this function
  to support both i.e. PINS and GROUPs.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:32 +02:00
Tomasz Figa 529301c19c pinctrl: samsung: Parse pin groups before calling pinctrl_register()
Calling pinctrl_register() means that the driver is fully initialized
and might accept pinmux/pinconf requests, so pin groups must be parsed
before.

This patch fixes this problem by moving device tree parsing before call
to pinctrl_register(). In addition, this fixes support for hogs on
pin controllers handled by pinctrl-samsung driver.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:31 +02:00
Mark Brown 736658c5eb pinctrl: palmas: Fix device name in Kconfig text
The device family is called Palmas so there should be a 's' on the end of
the name.

Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:31 +02:00
Axel Lin 13ceb77aef pinctrl: SPEAr310: Pass correct of_device_id table name to MODULE_DEVICE_TABLE
The symbol SPEAr310_pinctrl_of_match does not exist at all. Fix it.
We didn't hit the compile error because this driver can only be built-in now.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:30 +02:00
Maxime Ripard 23ac6df451 pinctrl: sunxi: Add Allwinner A20 pins set
The Allwinner A20 is pin-compatible with the older A10, so the two pin
set are quite similar. However, since the A20 has new features, we can't
just use the A10 pin set as is, and we need to define our own for the
A20.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:30 +02:00
Maxime Ripard de0c9029d5 pinctrl: sunxi: Add Allwinner A31 pins set
The Allwinner A31 SoC uses the same IP than the one found in the
A10/A13, with only different pins. Add the pins and the associated
functions found in the A31.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:29 +02:00
Maxime Ripard 30e7166323 pinctrl: sunxi: Fix inconsistent indentation
Some pin functions in the array were not indented like the other
functions in this array. Fix this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:29 +02:00
Axel Lin 6c325f874c pinctrl: core: Remove unnecessary test for desc->name
The implementation in pinctrl_register_one_pin() ensures pindesc->name is always
not NULL before insert the pindesc to radix tree.
If the desc return from pin_desc_get is not NULL, desc->name is always not NULL.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:29 +02:00
Axel Lin 5ffbe2e613 pinctrl: core: Hold pctldev->mutex mutex lock while traversing gpio_ranges list
Hold pctldev->mutex mutex_lock when traverse the list.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:28 +02:00
Axel Lin f005902108 pinctrl: core: Hold pinctrldev_list_mutex mutex while traversing pinctrldev_list
This one is missed in commit 44d5f7bb "pinctrl: sink pinctrldev_list_mutex".

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:27 +02:00
Qipan Li 031b8ce01b pinctrl: sirf: add lost atlas6 uart0-no-stream-control pingroup
the old codes defined uart0_nostreamctrl_pins, but missed pingroup
and padmux definition for it. this patch fixes it.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:27 +02:00
Sascha Hauer 8f903f8a34 pinctrl: imx: Use struct type for pins
The i.MX pinctrl driver uses 5 different arrays for storing the
informations for pins. This requires five allocations. Instead,
use a struct type which is more cache friendly, readable and
requires less allocations. One array of integers is still needed
since the pinctrl framework forces us to maintain it.
This also adds checks whether the allocations are succesful which
were missing.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-16 14:43:56 +02:00
Sascha Hauer 7ea46e0f9d pinctrl: imx: do not fail when parsing a function fails
When parsing a function fails this is no reason to make the whole
driver fail. Just continue with the next function.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-15 22:13:21 +02:00
Sascha Hauer 5e13762cf8 pinctrl: imx: do not fail when parsing a group fails
The i.MX pinctrl driver completely bails out when it detects an error
in the pinctrl nodes. This usually means that whatever error a
devicetree has the user is left blind because even the console cannot
be initialized without working pinmux.

Instead of bailing out completely, just continue probing. This makes
the pinctrl driver work, only the erroneous groups will fail later
during pin request time.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-15 22:13:17 +02:00
Sascha Hauer 1bf1fea95f pinctrl: imx: Catch no fsl,pins property
Instead of crashing the kernel print an error message when
the fsl,pins property is missing.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-15 22:13:11 +02:00
Sascha Hauer 01312513c4 pinctrl: imx: make error messages more informative
When printing error messages about errors in the devicetree also print
the offending node to give the use a hint what might be wrong.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-15 22:12:59 +02:00
Julia Lawall 690ebabb0b pinctrl: nomadik: simplify use of devm_ioremap_resource
Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.

Move the call to platform_get_resource adjacent to the call to
devm_ioremap_resource to make the connection between them more clear.

A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@

- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  ... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
  ... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  e = devm_ioremap_resource(e1, res);
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-15 22:12:47 +02:00
Linus Walleij f84b417131 pinctrl: nomadik: shut up a warning for flags
The irq flags variable gets a warning like this after
commit bf4dae5ce1
"pinctrl: nomadik: delete ancient pin control API":

In file included from include/linux/seqlock.h:29:0,
                 from include/linux/time.h:5,
                 from include/linux/stat.h:18,
                 from include/linux/module.h:10,
                 from
drivers/pinctrl/pinctrl-nomadik.c:14:
drivers/pinctrl/pinctrl-nomadik.c: In function 'nmk_pmx_enable':
include/linux/spinlock.h:348:122: warning:
'flags' may be used uninitialized in this function
[-Wmaybe-uninitialized]
  raw_spin_unlock_irqrestore(&lock->rlock, flags);
                                                   ^
drivers/pinctrl/pinctrl-nomadik.c:1515:16: note:
'flags' was declared here
  unsigned long flags;

The function is question was never changed but it appears
the semantic checker could previously determine that the code
path that would use the flags was going to either use it or
not, but now it can't for some reason. Just fix it up.

Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-15 22:12:46 +02:00
John Crispin 0fabc83543 pinctrl/lantiq: add missing gphy led setup
We found out how to set the gphy led pinmuxing.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 22:49:24 +02:00
Thomas Langer 89ebefe389 pinctrl/lantiq: add missing pin definition to falcon pinctrl driver
The pps pin definition is missing in the current code.

Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 22:49:24 +02:00
Laurent Pinchart 62783b714f sh-pfc: r8a7790: Add DU pin groups and functions
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 22:49:22 +02:00
Laurent Pinchart f06812095e sh-pfc: r8a7790: Rename DU1_DOTCLKIN to DU_DOTCLKIN1
Name the DU clock input 1 consistently with clock inputs 0 and 2.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 22:49:22 +02:00
Linus Walleij 1c8e794432 pinctrl: improve warning messages
Print out the affected group name on activation of pin mux
settings, and warn if you cannot free a pin that should have
been part of a certain setting.

ChangeLog v1->v2:
- Also print the pin name in the error messages.

Cc: Sonic Zhang <sonic.zhang@analog.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 22:49:14 +02:00
Laxman Dewangan 0a8d3e2412 pinctrl: palmas: add pincontrol driver
TI Palmas series Power Management IC have multiple pins which can be
configured for different functionality. This pins can be configured
for different function. Also their properties like pull up/down,
open drain enable/disable are configurable.

Add support for pincontrol driver Palmas series device like TPS65913,
TPS80036. The driver supports to be register from DT only.

Changes from V1:
- Add generic property for pins and functions in pinconf-generic.
- Add APIs to map the DT and subnode.
- Move common utils APIs to the pinctrl-utils from this file.
- Update the binding document accordingly.
Changes from V2:
- Add ack by Lee.
- Correct the binding docs.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 21:00:42 +02:00
Laxman Dewangan e81c8f18af pinctrl: pinconf-generic: add generic APIs for mapping pinctrl node
Add generic APIs to map the DT node and its sub node in pinconf generic
driver. These APIs can be used from driver to parse the DT node who
uses the pinconf generic APIs for defining their nodes.

Changes from V1:
- Add generic property for pins and functions in pinconf-generic.
- Add APIs to map the DT and subnode.
- Move common utils APIs to the pinctrl-utils from this file.
- Update the binding document accordingly.
Changes from V2:
- Rebased the pinctrl binding doc on top of Stephen's cleanup.
- Rename properties "pinctrl-pins" and "pinctrl-function" to
  "pins" and "function".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 21:00:41 +02:00
Laxman Dewangan 1eb207a9ec pinctrl: add utility functions for add map/configs
Some of pincontrol driver needs the utility function to create map
list. The utility function needed for adding mux, configs etc.

In place of duplicating this in each driver, add the common utility
function in common file and use from device specific driver. This will
reduce the duplicating of code across drivers.

Changes from V1:
- Add this files in this patch and add common utility APIs to here.

Changes from V2:
- Nothing in code.
- Added Reviewed by Stephen.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 21:00:41 +02:00
Sonic Zhang 744f0a9adb pinctrl: pinmux: Don't free pins requested by other devices in pinmux_disable_setting.
One peripheral may share part of its pins with the 2nd
peripheral and the other pins with the 3rd. If it requests all pins
when part of them has already be requested and owned by the 2nd
peripheral, this request fails and pinmux_disable_setting() is called.
The pinmux_disable_setting() frees all pins of the first peripheral
without checking if the pin is owned by itself or the 2nd, which
results in the malfunction of the 2nd peripheral driver.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 17:52:18 +02:00
Linus Walleij bf4dae5ce1 pinctrl: nomadik: delete ancient pin control API
The pin control subsystem was created to do away with custom pin
control APIs such as this one. It was kept for backward-compatibility
but is completely unused in the current kernel, so let's delete
it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:30:58 +02:00
Jingoo Han 2c9fdcf17e pinctrl: sirf: add missing __iomem annotation
Added missing __iomem annotation in order to fix the following
sparse warnings:

drivers/pinctrl/sirf/pinctrl-sirf.c:846:14: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/sirf/pinctrl-sirf.c:846:14:    expected void *regs
drivers/pinctrl/sirf/pinctrl-sirf.c:846:14:    got void [noderef] <asn:2>*
drivers/pinctrl/sirf/pinctrl-sirf.c:869:33: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/sirf/pinctrl-sirf.c:869:33:    expected void [noderef] <asn:2>*regs
drivers/pinctrl/sirf/pinctrl-sirf.c:869:33:    got void *regs
drivers/pinctrl/sirf/pinctrl-sirf.c:909:17: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/sirf/pinctrl-sirf.c:909:17:    expected void volatile [noderef] <asn:2>*addr
drivers/pinctrl/sirf/pinctrl-sirf.c:909:17:    got void *regs

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:30:40 +02:00
Jingoo Han 9b6803542e pinctrl: pinconf: fix comparison of different types
Fix the following sparse warning:

drivers/pinctrl/pinconf.c:521:20: error: incompatible types in comparison expression (different type sizes)

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:30:32 +02:00
Boris BREZILLON 99fce0295e pinctrl: at91: choose appropriate handler for level interrupts
The current implementation handle both edge and level interrupts with the
'handle_simple_irq' handler.

Level interrupts are active as long as the pin stays at the configured
level (low or high). In this case we have to use 'handle_level_irq' which
mask the interrupt until the handle has treated it.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:30:16 +02:00
Sachin Kamat ef75bfd5d1 pinctrl: st: Staticize local symbols
Symbols used only in this file are made static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:30:06 +02:00
Sachin Kamat 656445f3e2 pinctrl: st: Convert to use devm_ioremap_resource
devm_request_and_ioremap is deprecated. Use devm_ioremap_resource
instead.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:29:57 +02:00
Shawn Guo 94176faf27 pinctrl: imx: work around select input quirk
The select input for some pin may not be implemented using the regular
select input register but the general purpose register.  A real example
is that imx6q designers found the select input for USB OTG ID pin is
missing at the very late stage, and can not add a new select input
register but have to use a general purpose register bit to implement it.

The patch adds a workaround for such select input quirk by interpreting
the input_val cell of pin function ID in a different way, so that all
the info that needed for setting up select input bits in general purpose
register could be decoded from there.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:29:48 +02:00
Sachin Kamat 3efa921d5b pinctrl: sunxi: Fix incorrect NULL check
*map should be tested for NULL instead of map as kmalloc pointer
is assigned to it. This also fixes a potential null pointer dereference
bug later in the code.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:29:39 +02:00
Russell King - ARM Linux 8a9dcc3ffe pinctrl: shut up a couple of pinctrl warnings
So, I notice that we get a couple of warnings from the pinctrl code:

drivers/pinctrl/pinconf.c: In function 'pinconf_dbg_config_print':
drivers/pinctrl/pinconf.c:433:36: warning: 'configs' may be used uninitialized in this function
drivers/pinctrl/pinconf.c: In function 'pinconf_dbg_config_write':
drivers/pinctrl/pinconf.c:511:36: warning: 'configs' may be used uninitialized in this function

While the compiler might not be able to work out that "configs" is
safe, the code doesn't lend itself very well to identifying that
fact when reading it either.  This can be trivially solved by a slight
restructuring of the code - which also reduces the LOC.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:29:30 +02:00
Wolfram Sang cdaf0645db drivers/pinctrl: don't check resource with devm_ioremap_resource
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:29:21 +02:00
Heiko Stübner 7e865abb52 pinctrl: rockchip: include correct clk header
The correct header to include for clock handling is clk.h .
clk-provider.h should not be used in simple clock consumers.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:29:09 +02:00
Maxime Ripard 1bee963db9 pinctrl: sunxi: Add spinlocks
The current code use no locking at all, which is obviously not that
great and can lead to concurrency issues, especially with the newer SMP
SoCs from Allwinner.

Add some locking where it's needed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07 21:57:17 +02:00
Maxime Ripard df7b34f4c3 pinctrl: sunxi: Fix gpio_set behaviour
The current gpio_set function is ignoring the previous value set in the
GPIO value register, which leads in erasing the values already set for
the other GPIOs in the same bank when setting the value of a given GPIO.

Add the usual read/mask/write pattern to fix this brown paper bag bug.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07 21:57:13 +02:00
Maxime Ripard 2aaaddff8d pinctrl: sunxi: Read register before writing to it in irq_set_type
The current irq_set_type code doesn't read the current register value
before writing to it, leading to the older programmed values being
overwritten and everything but the latest value being reset.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07 20:39:25 +02:00
Linus Walleij f7a3427f3e Merge branch 'pinmux/next/fixes' of git://linuxtv.org/pinchartl/fbdev into devel
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-07-29 16:33:57 +02:00
Linus Walleij da52faa571 Merge branch 'pinmux/next/pin-no-gpio' of git://linuxtv.org/pinchartl/fbdev into devel
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-07-29 16:30:55 +02:00
Shinobu Uehara e120cacfaa sh-pfc: r8a7790: Add VIN pin groups and functions
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29 15:52:14 +02:00
Shinobu Uehara dac896e221 sh-pfc: r8a7790: Add USB pin groups and functions
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29 15:52:14 +02:00