Commit Graph

85 Commits

Author SHA1 Message Date
Swapnil Jakhade 48ac6085bd phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation
PIPE PHY status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-10-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:44 +05:30
Swapnil Jakhade 84f55df836 phy: cadence-torrent: Add debug information for PHY configuration
Add debug information in probe regarding PHY configuration parameters
like single link or multilink protocol along with number of lanes
used for each protocol link.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-9-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:44 +05:30
Swapnil Jakhade 8f3ced2fd4 phy: cadence-torrent: Add separate functions for reusable code
Torrent PHY driver currently supports single link DP configuration.
Prepare driver to support multilink DP configurations by adding
separate functions for common initialization sequence.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210728145454.15945-8-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:44 +05:30
Swapnil Jakhade 1cc455150b phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock
Add PHY configuration registers for single link DP with 100MHz reference
clock and NO_SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-7-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:44 +05:30
Swapnil Jakhade da055e5503 phy: cadence-torrent: Add PHY registers for DP in array format
Add PHY registers for single link DP in array format to simplify
code and to improve readability. This supports already supported
frequencies for DP of 19.2MHz and 25MHz.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-6-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:44 +05:30
Swapnil Jakhade 6a2338a5bf phy: cadence-torrent: Configure PHY registers as a function of input reference clock rate
Torrent PHY supports multiple serdes standards with different input
reference clock frequencies. PHY register values differ based on the
reference clock rate. Add PHY input reference clock frequency as a
new dimension to select proper register configuration. No functional
change is intended.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-5-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:43 +05:30
Swapnil Jakhade 3b40162516 phy: cadence-torrent: Add enum for supported input reference clock frequencies
Torrent PHY supports different input reference clock frequencies.
Register configurations will be different based on reference clock value.
Prepare driver to support such multiple reference clock frequencies.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210728145454.15945-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:43 +05:30
Swapnil Jakhade 5b16a790f1 phy: cadence-torrent: Reorder few functions to remove function declarations
Reorder some functions to avoid function declarations.
No functional change.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-3-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:43 +05:30
Swapnil Jakhade e956d4fceb phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK message
Script checkpatch with --strict option gives message:
CHECK: Avoid CamelCase: <REF_CLK_19_2MHz>
CHECK: Avoid CamelCase: <REF_CLK_25MHz>
Fix this by removing CamelCase usage. No functional change.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210728145454.15945-2-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-17 15:42:43 +05:30
Wang Wensheng 6411e386db phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()
Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.

Fixes: a43f72ae13 ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wang Wensheng <wangwensheng4@huawei.com>
Link: https://lore.kernel.org/r/20210517015749.127799-1-wangwensheng4@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-31 13:50:05 +05:30
Kishon Vijay Abraham I b20da3c6b9 phy: cadence-torrent: Add delay for PIPE clock to be stable
The Torrent spec specifies delay of 660.5us after phy_reset is
asserted by the controller. To be on the safe side provide a delay
of 5ms to 10ms in ->phy_on() callback where the SERDES is already
configured in bootloader.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210330110138.24356-6-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:45:47 +05:30
Kishon Vijay Abraham I e0611d6d96 phy: cadence-torrent: Explicitly request exclusive reset control
No functional change. Since the reset controls obtained in
Torrent is exclusively used by the Torrent device, use
exclusive reset control request API calls.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-5-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:45:47 +05:30
Kishon Vijay Abraham I b69d39f684 phy: cadence-torrent: Do not configure SERDES if it's already configured
Do not configure torrent SERDES if it's already configured.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-4-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:45:47 +05:30
Kishon Vijay Abraham I d44b4bf49e phy: cadence-torrent: Group reset APIs and clock APIs
No functional change intended. Group reset APIs and clock APIs in
preparation for adding support to skip configuration if the SERDES
is already configured by bootloader.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-3-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:45:47 +05:30
Kishon Vijay Abraham I 1436ec309e phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-14-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:43:21 +05:30
Kishon Vijay Abraham I 28081b7285 phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's
possible to select one of these two inputs from device tree.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:43:21 +05:30
Kishon Vijay Abraham I 29c2d02adb phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback
commit 44d30d6228 ("phy: cadence: Add driver for Sierra PHY") enabled
the clock in probe and failed to disable in remove callback. Add missing
clk_disable_unprepare() in cdns_sierra_phy_remove().

Fixes: 44d30d6228 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210319124128.13308-11-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:43:21 +05:30
Kishon Vijay Abraham I a0c30cd783 phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-10-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:43:21 +05:30
Kishon Vijay Abraham I fd7abc3c5b phy: cadence-torrent: Use a common header file for Cadence SERDES
No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:43:20 +05:30
Kishon Vijay Abraham I 15b0b82d51 phy: cadence: Sierra: Explicitly request exclusive reset control
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-8-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:43:20 +05:30
Kishon Vijay Abraham I 1d5f40e021 phy: cadence: Sierra: Move all reset_control_get*() to a separate function
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-7-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:43:20 +05:30
Kishon Vijay Abraham I 7e016cbc52 phy: cadence: Sierra: Move all clk_get_*() to a separate function
No functional change. Group all devm_clk_get_optional() to a
separate function.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-6-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:43:20 +05:30
Kishon Vijay Abraham I 03ada5a37c phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-4-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:42:51 +05:30
Kishon Vijay Abraham I 5b4f5757f8 phy: cadence: Sierra: Fix PHY power_on sequence
Commit 44d30d6228 ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.

Fixes: 44d30d6228 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Cc: <stable@vger.kernel.org> # v5.4+
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31 16:42:51 +05:30
Swapnil Jakhade ed9e07f815 phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clock
Update PCIe + USB register sequences for correct PLL1 clock configuration.
Also, update sequences for other USB configurations with dependent changes.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1614838096-32291-5-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30 23:34:14 +05:30
Kishon Vijay Abraham I 70901a7d64 phy: cadence-torrent: Update SGMII/QSGMII configuration specific to TI
Update SGMII/QSGMII configuration specific to TI.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1614838096-32291-4-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30 23:34:14 +05:30
Swapnil Jakhade e25c9dbcfc phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clock
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was
expecting 10GHz clock, configuration was giving 8GHz clock. Update
register sequences to get correct PLL1 configuration.

Also, update single link PCIe and single link SGMII/QSGMII configurations
with related changes.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30 23:34:13 +05:30
Kishon Vijay Abraham I 2cca0228f3 phy: cadence-torrent: Add support to drive refclk out
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_<p/m> can also be configured to output the
reference clock. Model this derived reference clock as a "clock" so that
platforms like AM642 EVM can enable it.

This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210310120840.16447-7-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30 23:33:40 +05:30
Dan Carpenter 266df28f9a phy: cadence-torrent: Fix error code in cdns_torrent_phy_probe()
This error path should return -EINVAL, but currently it returns
success.

Fixes: d09945eaca ("phy: cadence-torrent: Check total lane count for all subnodes is within limit")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/X9s7Wxq+b6ls0q7o@mwanda
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13 17:31:02 +05:30
Chunfeng Yun fa62909400 phy: cadence: convert to devm_platform_ioremap_resource
Use devm_platform_ioremap_resource to simplify code

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Peter Chen <peter.chen@nxp.com>
Link: https://lore.kernel.org/r/1604642930-29019-4-git-send-email-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 12:47:46 +05:30
Swapnil Jakhade 6fd428f780 phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configuration
Add USB + SGMII/QSGMII multilink configuration sequences.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-14-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:22 +05:30
Swapnil Jakhade 4acea473f3 phy: cadence-torrent: Add PCIe + USB multilink configuration
Add PCIe + USB Unique SSC multilink configuration sequences.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-13-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:22 +05:30
Swapnil Jakhade 9855d84b6b phy: cadence-torrent: Add single link USB register sequences
Add support for single link USB configuration.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-12-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:21 +05:30
Swapnil Jakhade 9f33b76a35 phy: cadence-torrent: Add single link SGMII/QSGMII register sequences
Add support for single link SGMII/QSGMII configuration.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-11-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:21 +05:30
Swapnil Jakhade d66a636669 phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals
Include PHY_PLL_CFG as a first register value to configure in
link_cmn_vals array values.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-10-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:21 +05:30
Swapnil Jakhade cd9aa94737 phy: cadence-torrent: Add PHY link configuration sequences for single link
Add support to configure link_cmn_vals and xcvr_diag_vals in case of single
link PHY configuration.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-9-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:20 +05:30
Swapnil Jakhade 07084c9566 phy: cadence-torrent: Add clk changes for multilink configuration
Prepare and enable clock in probe instead of phy_init.
Also, remove phy_exit callback.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-8-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:20 +05:30
Swapnil Jakhade f0f1fa0458 phy: cadence-torrent: Update PHY reset for multilink configuration
For multilink configuration, deassert PHY and link reset after PHY
registers are configured in probe and only check link status in
power_on callback.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-7-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:20 +05:30
Swapnil Jakhade 6bcf3cb300 phy: cadence-torrent: Add support for PHY multilink configuration
Added support for multilink configuration of Torrent PHY. Currently,
maximum two links are supported. In case of multilink configuration,
PHY needs to be configured for both the protocols simultaneously at
the beginning as per the requirement of Torrent PHY.
Also, register sequences for PCIe + SGMII/QSGMII Unique SSC PHY multilink
configurations are added.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-6-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:19 +05:30
Swapnil Jakhade 15c6a048e5 phy: cadence-torrent: Add PHY APB reset support
Add support for PHY APB reset and make it optional.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-4-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:19 +05:30
Swapnil Jakhade 8e4c95b9c9 phy: cadence-torrent: Check cmn_ready assertion during PHY power on
Check if cmn_ready is set after both PLL0 and PLL1 are locked.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-3-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:18 +05:30
Swapnil Jakhade b54b47bd03 phy: cadence-torrent: Add single link PCIe support
Add single link PCIe register sequences in Torrent PHY driver.
Also, add support for getting SSC type from DT.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-2-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:47:18 +05:30
Swapnil Jakhade d09945eaca phy: cadence-torrent: Check total lane count for all subnodes is within limit
Add checking if total number of lanes for all subnodes is not greater than
number of lanes supported by PHY.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-6-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:34:47 +05:30
Swapnil Jakhade 2e70c84995 phy: cadence-torrent: Add separate regmap functions for torrent and DP
Added separate functions for regmap initialization of torrent PHY
generic registers and DP specific registers.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-5-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:34:47 +05:30
Swapnil Jakhade 7c12b46c63 phy: cadence-torrent: Enable support for multiple subnodes
Enable support for multiple subnodes in torrent PHY to
include multi-link combinations.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-4-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:34:47 +05:30
Swapnil Jakhade 46d205af30 phy: cadence-torrent: Use devm_platform_ioremap_resource() to get reg addresses
Use devm_platform_ioremap_resource() to get register addresses instead of
boilerplate code.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-3-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:34:46 +05:30
Swapnil Jakhade 29d1fd2f2c phy: cadence-torrent: Use of_device_get_match_data() to get driver data
Use of_device_get_match_data() to get driver data instead of boilerplate
code.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-2-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-18 10:34:46 +05:30
Rikard Falkeborn 57d39c7697 phy: cadence: torrent: Constify regmap_config structs
The regmap_config structs are never modified and can be made const to
allow the compiler to put them in read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200912204639.501669-4-rikard.falkeborn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16 17:43:31 +05:30
Rikard Falkeborn 2f4a3d8b7c phy: cadence: salvo: Constify cdns_nxp_sequence_pair
cdns_nxp_sequence_pair[] are never modified and can be made const to allow
the compiler to put them in read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Link: https://lore.kernel.org/r/20200912204639.501669-3-rikard.falkeborn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16 17:43:31 +05:30
Rikard Falkeborn 3cfb0e8e41 phy: cadence: Sierra: Constify static structs
The static cdns_reg_pairs and regmap_config structs are not modified and
can be made const. This allows the compiler to put them in read-only
memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200912204639.501669-2-rikard.falkeborn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16 17:43:31 +05:30