Few drivers still have assumption that ir_raw_event
consists of duration and pulse flag.
Fix that.
Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
The CX23885 and CX25840 modules were using their own simple
IR pulse width measurement record type which required conversion
when passing to the new IR core. This change makes that record type
consistent with the new IR core and removes a data conversion.
Signed-off-by: Andy Walls <awalls@md.metrocast.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Instead of reporting an IR Rx timeout event as a ridiculously
long space, report it as a space of the lenght of the timeout.
This partially fixes operation with LIRC without breaking
interoperation with the in kernel decoders. The gaps lengths
reported to LIRC are still not real however.
Signed-off-by: Andy Walls <awalls@md.metrocast.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Compute and report the maximum IR pulse measurment width, even
if we are set to perform carrier modulation or demodulation and
the number is fixed by the carrier freq.
Signed-off-by: Andy Walls <awalls@md.metrocast.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This patch is primarily a port of the integrated IR controller code in
cx23885/cx23888-ir.c. Right now, only the CX2388[57] AV core will
really try to set up IR. This IR support, by design, still requires the
bridge driver to do final IO pin mux configuration and setup of the IR
controller parameters.
For the CX2388[578] chips, enabling the AV Core for IR also starts
sending Audio and Video interrupts to the bridge driver. For
CX2388[578] chips audio and video interrupts are ignored and
acknowledged when they happen.
IR interrupt handling and status logging is exluded for the CX23888
which does not have an IR controller on the AV core.
Note that experimentation reveals that the IR irq enables on the
CX23885 have an inverted logic sense. The CX23887 likely suffers from
the same quirk. For these chips, those irq enable bits are handled
as interrupt disables.
Signed-off-by: Andy Walls <awalls@md.metrocast.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Maxim Levitsky