Commit Graph

8 Commits

Author SHA1 Message Date
Jia He f5e32344d4 EDAC/igen6: Return the correct error type when not the MC owner
Return -EBUSY instead of -ENODEV just like the other EDAC drivers do.

  [ bp: Rewrite text. ]

Signed-off-by: Jia He <justin.he@arm.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20221018082214.569504-8-justin.he@arm.com
2022-10-25 10:10:54 +02:00
Jia He 315bada690 EDAC: Check for GHES preference in the chipset-specific EDAC drivers
Call ghes_get_devices() to check whether ghes_edac should be used on the
platform where it is preferred over the corresponding chipset-specific
EDAC driver.

Unlike the existing edac_get_owner() check, the ghes_get_devices() check
works independent to the module_init ordering.

  [ bp: Massage. ]

Suggested-by: Toshi Kani <toshi.kani@hpe.com>
Signed-off-by: Jia He <justin.he@arm.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20221010023559.69655-6-justin.he@arm.com
2022-10-21 22:09:54 +02:00
Qiuxu Zhuo ad774bd5a8 EDAC/igen6: Add Intel Alder Lake SoC support
Alder Lake SoC shares the same memory controller and In-Band ECC
(IBECC) IP with Tiger Lake SoC. Like Tiger Lake, it also has two
memory controllers each associated one IBECC instance. The minor
differences include the MMIO offset of each memory controller and
the type of memory error address logged in the IBECC.

So add Alder Lake compute die IDs, adjust the MMIO offset for each
memory controller and handle the type of memory error address logged
in the IBECC for Alder Lake EDAC support.

Tested-by: Vrukesh V Panse <vrukesh.v.panse@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20210611170123.1057025-7-tony.luck@intel.com
2021-06-17 18:20:01 -07:00
Qiuxu Zhuo 0b7338b27e EDAC/igen6: Add Intel Tiger Lake SoC support
Tiger Lake SoC shares the same memory controller and In-Band ECC
(IBECC) IP with Elkhart Lake SoC. The main differences are that Tiger
Lake has two memory controllers each associated with one IBECC and
uses Machine Check for the memory error notification.

So add Tiger Lake compute die IDs, MCE decoding chain registration,
and memory slice decoding for Tiger Lake EDAC support.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20210611170123.1057025-6-tony.luck@intel.com
2021-06-17 18:19:53 -07:00
Qiuxu Zhuo 4e591c0568 EDAC/igen6: Add Intel ICL-NNPI SoC support
The Ice Lake Neural Network Processor for Deep Learning Inference
(ICL-NNPI) SoC shares the same memory controller and In-Band ECC with
Elkhart Lake SoC. Add the ICL-NNPI compute die IDs for EDAC support.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20210611170123.1057025-5-tony.luck@intel.com
2021-06-17 18:19:46 -07:00
kernel test robot 77429eebd9 EDAC/igen6: ecclog_llist can be static
Fixes: 10590a9d4f ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20201123031850.GA20416@aef56166e5fc
Signed-off-by: Tony Luck <tony.luck@intel.com>
2020-11-23 10:11:08 -08:00
Qiuxu Zhuo 2223d8c781 EDAC/igen6: Add debugfs interface for Intel client SoC EDAC driver
Add debugfs support to fake memory correctable errors to test the
error reporting path and the error address decoding logic in the
igen6_edac driver.

Please note that the fake errors are also reported to EDAC core and
then the CE counter in EDAC sysfs is also increased.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2020-11-19 12:52:47 -08:00
Qiuxu Zhuo 10590a9d4f EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC
This driver supports Intel client SoC with integrated memory controller
using In-Band ECC(IBECC). The memory correctable and uncorrectable errors
are reported via NMIs. The driver handles the NMIs and decodes the memory
error address to platform specific address. The first IBECC-supported SoC
is Elkhart Lake.

[Tony: s/#include <linux/nmi.h>/#include <asm/nmi.h>/ to fix randconfig build]

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2020-11-19 12:51:17 -08:00