Commit Graph

23 Commits

Author SHA1 Message Date
Linus Torvalds 4a0225c3d2 spi: Updates for v5.13
The only core work for SPI this time around is the completion of the
 conversion to the new style method for specifying transfer delays,
 meaning we can cope with what most controllers support more directly
 using conversions in the core rather than open coding in drivers.
 Otherwise it's a good stack of cleanups and fixes plus a few new
 drivers.
 
 The conversion to new style transfer delay will cause an issue with a
 newly added staging driver which has a straightforward resolution in
 -next.
 
  - Completion of the conversion to new style transfer delay
    configuration.
  - Introduction and use of module_parport_driver() helper, merged here
    as there's no parport tree.
  - Support for Altera SoCs on DFL buses, NXP i.MX8DL, HiSilicon Kunpeng,
    MediaTek MT8195,
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Merge tag 'spi-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "The only core work for SPI this time around is the completion of the
  conversion to the new style method for specifying transfer delays,
  meaning we can cope with what most controllers support more directly
  using conversions in the core rather than open coding in drivers.

  Otherwise it's a good stack of cleanups and fixes plus a few new
  drivers.

  Summary:

   - Completion of the conversion to new style transfer delay
     configuration

   - Introduction and use of module_parport_driver() helper, merged here
     as there's no parport tree

   - Support for Altera SoCs on DFL buses, NXP i.MX8DL, HiSilicon
     Kunpeng, MediaTek MT8195"

* tag 'spi-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (113 commits)
  spi: Rename enable1 to activate in spi_set_cs()
  spi: Convert Freescale QSPI binding to json schema
  spi: stm32-qspi: fix debug format string
  spi: tools: make a symbolic link to the header file spi.h
  spi: fsi: add a missing of_node_put
  spi: Make error handling of gpiod_count() call cleaner
  spidev: Add Micron SPI NOR Authenta device compatible
  spi: brcm,spi-bcm-qspi: convert to the json-schema
  spi: altera: Add DFL bus driver for Altera API Controller
  spi: altera: separate core code from platform code
  spi: stm32-qspi: Fix compilation warning in ARM64
  spi: Handle SPI device setup callback failure.
  spi: sync up initial chipselect state
  spi: stm32-qspi: Add dirmap support
  spi: stm32-qspi: Trigger DMA only if more than 4 bytes to transfer
  spi: stm32-qspi: fix pm_runtime usage_count counter
  spi: spi-zynqmp-gqspi: return -ENOMEM if dma_map_single fails
  spi: spi-zynqmp-gqspi: fix use-after-free in zynqmp_qspi_exec_op
  spi: spi-zynqmp-gqspi: Resolved slab-out-of-bounds bug
  spi: spi-zynqmp-gqspi: fix hang issue when suspend/resume
  ...
2021-04-26 16:32:11 -07:00
Meng Li ea94191e58
spi: cadence: set cqspi to the driver_data field of struct device
When initialize cadence qspi controller, it is need to set cqspi
to the driver_data field of struct device, because it will be
used in function cqspi_remove/suspend/resume(). Otherwise, there
will be a crash trace as below when invoking these finctions.

Fixes: 31fb632b5d ("spi: Move cadence-quadspi driver to drivers/spi/")
Cc: stable@vger.kernel.org
Signed-off-by: Meng Li <Meng.Li@windriver.com>
Link: https://lore.kernel.org/r/20210311091220.3615-1-Meng.Li@windriver.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-03-11 13:32:32 +00:00
Jay Fang 31890269c0
spi: cadence-quadspi: Silence shiftTooManyBitsSigned warning
drivers/spi/spi-cadence-quadspi.c:267:18: warning: Shifting signed 32-bit
value by 31 bits is undefined behaviour [shiftTooManyBitsSigned]
    return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
                    ^

Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Jay Fang <f.fangjian@huawei.com>
Link: https://lore.kernel.org/r/1614854872-8694-1-git-send-email-f.fangjian@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-03-10 12:47:01 +00:00
Junlin Yang 87d62d8fa6
spi: cadence-quadspi: add missing of_node_put
Fix OF node leaks by calling of_node_put in
for_each_available_child_of_node when the cycle returns.

Generated by: scripts/coccinelle/iterators/for_each_child.cocci

Signed-off-by: Junlin Yang <yangjunlin@yulong.com>
Link: https://lore.kernel.org/r/20210215110425.1012-1-angkery@163.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-03-10 12:46:54 +00:00
Pratyush Yadav d227513964
spi: cadence-quadspi: Use spi_mem_dtr_supports_op()
Use the newly introduced spi_mem_dtr_supports_op() to check DTR op
support. This means the buswidth check does not need to be replicated.
It also happens to fix a bug where STR ops with a 2-byte opcode would be
reported as supported.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20210204141218.32229-2-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-02-11 15:51:37 +00:00
Ramuthevar Vadivel Murugan b436fb7d29
spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-4-vadivel.muruganx.ramuthevar@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13 11:37:03 +00:00
Ramuthevar Vadivel Murugan ad2775dc3f
spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).

This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfe

DAC bit resets to 1 so there is no need to explicitly set it.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-3-vadivel.muruganx.ramuthevar@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13 11:37:02 +00:00
Ramuthevar Vadivel Murugan ab2d28750a
spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
Add QSPI controller support for Intel LGM SoC.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-2-vadivel.muruganx.ramuthevar@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13 11:37:01 +00:00
Pratyush Yadav 2ef0170e90
spi: cadence-quadspi: Fix build warning on 32-bit platforms
The kernel test robot reports the following warning.

drivers/spi/spi-cadence-quadspi.c:966:24: warning: comparison of distinct pointer types ('typeof (len) *' (aka 'unsigned int *') and 'typeof (500UL) *' (aka 'unsigned long *')) [-Wcompare-distinct-pointer-types]
                                            msecs_to_jiffies(max(len, 500UL)))) {
                                                             ^~~~~~~~~~~~~~~
   include/linux/minmax.h:58:19: note: expanded from macro 'max'
   #define max(x, y)       __careful_cmp(x, y, >)
                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/minmax.h:42:24: note: expanded from macro '__careful_cmp'
           __builtin_choose_expr(__safe_cmp(x, y), \
                                 ^~~~~~~~~~~~~~~~
   include/linux/minmax.h:32:4: note: expanded from macro '__safe_cmp'
                   (__typecheck(x, y) && __no_side_effects(x, y))
                    ^~~~~~~~~~~~~~~~~
   include/linux/minmax.h:18:28: note: expanded from macro '__typecheck'
           (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
                      ~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~
   1 warning generated.

This happens because size_t is unsigned long on 64-bit platforms like
arm64 but it is unsigned int on 32-bit platforms like arm. Omitting the
"UL" would result in a warning on 64-bit platforms. Squash it by type
casting the arguments to size_t using max_t(). This way builds on both
type of platforms can be satisfied. There is no chance of any truncation
since 500 is small enough to fit into both int and long.

Fixes: f453f29397 ("spi: cadence-quadspi: Wait at least 500 ms for direct reads")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20210108181457.30291-1-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-11 16:22:50 +00:00
Yanteng Si 8728a81b8f
spi: Fix distinct pointer types warning for ARCH=mips
Fix a new warning report by build for make ARCH=MIPS allmodconfig:

drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_direct_read_execute':
 ./include/linux/minmax.h:18:28: warning: comparison of distinct pointer types lacks a cast
    18 |  (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
       |                            ^~
 ./include/linux/minmax.h:32:4: note: in expansion of macro '__typecheck'
    32 |   (__typecheck(x, y) && __no_side_effects(x, y))
       |    ^~~~~~~~~~~
 ./include/linux/minmax.h:42:24: note: in expansion of macro '__safe_cmp'
    42 |  __builtin_choose_expr(__safe_cmp(x, y), \
       |                        ^~~~~~~~~~
 ./include/linux/minmax.h:58:19: note: in expansion of macro '__careful_cmp'
    58 | #define max(x, y) __careful_cmp(x, y, >)
       |                   ^~~~~~~~~~~~~
 drivers/spi/spi-cadence-quadspi.c:1153:24: note: in expansion of macro 'max'
  1153 |       msecs_to_jiffies(max(len, 500UL)))) {
       |                        ^~~

"len" is unsigned,however,"500" is unsigned long.

Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Link: https://lore.kernel.org/r/20210107115704.3835282-1-siyanteng@loongson.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-08 14:00:45 +00:00
Pratyush Yadav f453f29397
spi: cadence-quadspi: Add DTR support
Double Transfer Rate (DTR) mode transfers data twice per clock cycle.
Add support for parsing DTR ops and set up the registers to allow it.

Most SPI NOR flashes expect 2 byte commands. Parse the 2-byte opcode
from SPI MEM and set it up in the CQSPI_REG_OP_EXT_LOWER register.

Increment the delay needed before issuing indirect writes because larger
delay is needed for DTR mode. With the current delay some writes end up
missing.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-8-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06 13:08:47 +00:00
Pratyush Yadav 0920a32cf6
spi: cadence-quadspi: Wait at least 500 ms for direct reads
When performing a direct read via DMA the timeout for completion is set
equal to the read length. This is fine for larger reads. For a small
read like the Read Status Register command, the timeout would be 1 or 2
milliseconds. This is not enough to cover the overhead needed in setting
up DMA.

Make sure the timeout is at least 500 ms to allow DMA ample time to
finish. For reads larger than 500 bytes, the timeout will continue to be
equal to the read length.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20201222184425.7028-7-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06 13:08:46 +00:00
Pratyush Yadav a273596b9b
spi: cadence-quadspi: Implement a simple supports_op hook
The default SPI MEM supports_op hook rejects DTR ops by default. Add a
simple supports_op hook that very closely imitates the SPI MEM one. It
will be extended in later commits to allow DTR ops.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-6-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06 13:08:45 +00:00
Pratyush Yadav 7512eaf541
spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1
SPI MEM deals with dummy bytes but the controller deals with dummy
cycles. Multiplying bytes by 8 is correct if the dummy phase uses 1S
mode since 1 byte will be sent in 8 cycles. But if the dummy phase uses
4S mode then 1 byte will be sent in 2 cycles.

To correctly translate dummy bytes to dummy cycles, the dummy buswidth
also needs to be taken into account. Divide 8 by the buswidth to get the
correct multiplier for getting the number of cycles.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-5-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06 13:08:44 +00:00
Pratyush Yadav 888d517b99
spi: cadence-quadspi: Set dummy cycles from STIG commands
If a command does not have an address phase it goes via the STIG path.
The dummy cycles are not initialized for the STIG commands. As a result,
STIG commands with dummy cycles will not work.

Initialize the dummy cycle field before issuing the STIG command to make
sure it is sent correctly. Move the code to calculate dummy cycle value
to a separate function so it is not repeated twice. DTR support will add
some more logic here to it is worth it to extract it out in a function.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-4-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06 13:08:43 +00:00
Pratyush Yadav ceeda328ed
spi: cadence-quadspi: Abort read if dummy cycles required are too many
The controller can only support up to 31 dummy cycles. If the command
requires more it falls back to using 31. This command is likely to fail
because the correct number of cycles are not waited upon. Rather than
silently issuing an incorrect command, fail loudly so the caller can get
a chance to find out the command can't be supported by the controller.

Fixes: 1406234105 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-3-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06 13:08:42 +00:00
Pratyush Yadav 3a5c09c8d1
spi: cadence-quadspi: Set master max_speed_hz
As of commit 9326e4f1e5 ("spi: Limit the spi device max speed to
controller's max speed"), the SPI device max speed is set to the
controller's max speed if it is larger. The Cadence QSPI controller does
not set the controller's max speed so it is left at its initial value of
0. This means the SPI device max speed is always set to 0.

The SPI device max speed is used to calculate the baud rate divider when
performing an operation. If this speed is 0, the default divider of 32
is used. No matter what speed is specified by the device tree property
'spi-max-frequency', the device will always operate at ref_clk / 32.

Fix this by setting master->max_speed_hz to the ref clock speed so the
correct divider can be calculated.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-2-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06 13:08:41 +00:00
Zhihao Cheng ac9978fcad
spi: cadence-quadspi: Fix error return code in cqspi_probe
Fix to return the error code from
devm_reset_control_get_optional_exclusive() instaed of 0
in cqspi_probe().

Fixes: 31fb632b5d ("spi: Move cadence-quadspi driver to drivers/spi/")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20201116141836.2970579-1-chengzhihao1@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-16 20:02:42 +00:00
Mark Brown 9887311813
Merge remote-tracking branch 'spi/for-5.10' into spi-next 2020-10-09 16:01:22 +01:00
Krzysztof Kozlowski 436a5c2080
spi: cadence-quadspi: Simplify with dev_err_probe()
Common pattern of handling deferred probe can be simplified with
dev_err_probe().  Less code and the error value gets printed.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200901152713.18629-5-krzk@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-08 18:19:26 +01:00
Vignesh Raghavendra 83048015ff
spi: spi-cadence-quadspi: Fix mapping of buffers for DMA reads
Buffers need to mapped to DMA channel's device pointer instead of SPI
controller's device pointer as its system DMA that actually does data
transfer.
Data inconsistencies have been reported when reading from flash
without this fix.

Fixes: ffa639e069 ("mtd: spi-nor: cadence-quadspi: Add DMA support for direct mode reads")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/20200831130720.4524-1-vigneshr@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-08 15:20:10 +01:00
Vignesh Raghavendra 2ea370a917
spi: spi-cadence-quadspi: Populate get_name() interface
Implement get_name() interface of spi_controller_mem_ops so as to avoid
changing of mtd->name due to driver being moved over to spi-mem
framework from SPI NOR. This avoids breaking of MTD cmdline args being
passed by bootloaders which maybe using old driver name.

Fixes: 31fb632b5d ("spi: Move cadence-quadspi driver to drivers/spi/")
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200825172506.14375-1-vigneshr@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-08-25 21:41:50 +01:00
Ramuthevar Vadivel Murugan 31fb632b5d
spi: Move cadence-quadspi driver to drivers/spi/
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/

Update license header to match SPI subsystem style

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-9-vigneshr@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-19 14:26:54 +01:00