08bcbed747
drm/mediatek: fix connection from RDMA2 to DSI1
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This patch fix connection from RDMA2 to DSI1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27 11:24:37 +08:00
85186efc2a
drm/mediatek: add connection from RDMA2 to DSI0
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This patch add connection from RDMA2 to DSI0
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27 11:24:35 +08:00
0a14785ee3
drm/mediatek: add connection from RDMA1 to DSI0
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This patch add connection from RDMA1 to DSI0
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27 11:24:35 +08:00
48d25d243b
drm/mediatek: add connection from RDMA0 to DSI1
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This patch add connection from RDMA0 to DSI1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27 11:24:35 +08:00
29d32e466e
drm/mediatek: add connection from RDMA0 to DPI1
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This patch add connection from RDMA0 to DPI1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27 11:24:35 +08:00
e6ab087a22
drm/mediatek: Add support for mediatek SOC MT2712
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This patch add support for the Mediatek MT2712 DISP subsystem.
There are two OVL engine and three disp output in MT2712.
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-28 00:27:36 +08:00
16dd757ead
drm/mediatek: add DSI3 support for mutex
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This patch add the DSI3 support for mutex
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:08:44 +08:00
dee8eb4e66
drm/mediatek: add DSI2 support for mutex
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This patch add the DSI2 support for mutex
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:08:29 +08:00
f4f3ec480e
drm/mediatek: add DPI1 support for mutex
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This patch add the DPI1 support for mutex
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:08:12 +08:00
d335369e75
drm/mediatek: add connection from RDMA2 to DSI3
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This patch add the connection from RDMA2 to DSI3
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:07:51 +08:00
46ce9b2dc7
drm/mediatek: add connection from RDMA2 to DSI2
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This patch add the connection from RDMA2 to DSI2
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:07:34 +08:00
0064be8c71
drm/mediatek: add connection from RDMA2 to DSI1
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This patch add the connection from RDMA2 to DSI1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:07:19 +08:00
7ddac09167
drm/mediatek: add connection from RDMA2 to DPI1
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This patch add the connection from RDMA2 to DPI1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:07:02 +08:00
01915b8588
drm/mediatek: add connection from RDMA2 to DPI0
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This patch add the connection from RDMA2 to DPI0
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:06:48 +08:00
15484ae0af
drm/mediatek: add connection from RDMA1 to DSI3
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This patch add the connection from RDMA1 to DSI3
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:06:30 +08:00
5346010f72
drm/mediatek: add connection from RDMA1 to DSI2
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This patch add the connection from RDMA1 to DSI2
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:06:14 +08:00
d46a8f851e
drm/mediatek: add connection from RDMA1 to DSI1
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This patch add the connection from RDMA1 to DSI1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:05:56 +08:00
73fabd5ceb
drm/mediatek: add connection from RDMA1 to DPI1
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This patch add the connection from RDMA1 to DPI1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:05:39 +08:00
89c04d6502
drm/mediatek: add connection from RDMA0 to DSI3
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This patch add the connection from RDMA0 to DSI3
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:05:23 +08:00
49793b7674
drm/mediatek: add connection from RDMA0 to DSI2
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This patch add the connection from RDMA0 to DSI2
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:05:06 +08:00
7b86302401
drm/mediatek: add connection from RDMA0 to DPI0
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This patch add the connection from RDMA0 to DPI0
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:04:50 +08:00
09013b1619
drm/mediatek: Update the definition of connection from RDMA1 to DPI0
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This patch update the definition of connection from RDMA1 to DPI0.
Change the term MOUT to SOUT.
Because our HW datasheet use the term SOUT to match its function for RDMA.
For consistency, changing the name from MOUT to SOUT is better.
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:04:30 +08:00
9b7b38de38
drm/mediatek: add connection from OD1 to RDMA1
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This patch add the connection from OD1 to RDMA1 for ext path.
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:04:11 +08:00
df2dce4e11
drm/mediatek: add ddp component OD1
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This patch add the component OD1 and
rename the OD to OD0
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:01:48 +08:00
d480bbc474
drm/mediatek: add ddp component AAL1
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This patch add component AAL1 and
rename AAL to AAL0
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:01:22 +08:00
8617ec2474
drm/mediatek: support maximum 64 mutex mod
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This patch support that if modules more than 32,
add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24 12:00:27 +08:00
84a5ead18e
drm/mediatek: add support for Mediatek SoC MT2701
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This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.
Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08 00:02:17 +08:00
fb2557de27
drm/mediatek: update display module connections
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update connections for OVL, RDMA, BLS, DSI
Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08 00:02:14 +08:00
9dc84e98a3
drm/mediatek: add shadow register support
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We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.
Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08 00:02:13 +08:00
c5f228ef6c
drm/mediatek: add *driver_data for different hardware settings
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There are some hardware settings changed, between MT8173 & MT2701:
DISP_OVL address offset changed, color format definition changed.
DISP_RDMA fifo size changed.
DISP_COLOR offset changed.
MIPI_TX pll setting changed.
And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod.
Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08 00:02:12 +08:00
119f517362
drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
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This patch adds an initial DRM driver for the Mediatek MT8173 DISP
subsystem. It currently supports two fixed output streams from the
OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: YT Shen <yt.shen@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Mao Huang <littlecvr@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-05-06 17:47:35 +02:00
Stu Hsieh