Commit Graph

257 Commits

Author SHA1 Message Date
Hiromitsu Yamasaki 7cb1ce2688 clk: renesas: r8a7796: Add USB-DMAC clocks
This patch adds USB-DMAC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Hiromitsu Yamasaki c1da6b4b84 clk: renesas: r8a7796: Add Audio-DMAC clocks
This patch adds A-DMAC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[geert: Correct parent clocks, preserve sort order]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi f4c542923d clk: renesas: r8a7796: Add EHCI/OHCI clocks
This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Koji Matsuoka 12390605ac clk: renesas: r8a7796: Add HDMI clock
This patch adds HDMI-IF0 clock for R8A7796 SoC.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Takeshi Kihara f5ca01141c clk: renesas: r8a7795: Add HS-USB ch3 clock
This patch adds valid HS-USB ch3 clock from R8A7795 ES2.0 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Takeshi Kihara 0a12c4400c clk: renesas: r8a7795: Add USB-DMAC ch3 clock
This patch supports the clock of USB-DMAC ch3 module added from R8A7795
ES2.0 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Takeshi Kihara 66fbee35d5 clk: renesas: r8a7795: Add EHCI/OHCI ch3 clock
This patch supports the clock of EHCI/OHCI ch3 module added from R8A7795
ES2.0 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven 5ed793b3b2 clk: renesas: r8a7745: Remove PLL configs for MD19=0
According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's
Manual Rev.1.00, MD19=0 is a prohibited setting.

Hence stop looking at MD19, and remove all PLL configurations for
MD19=0.

Fixes: 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven b93e7eb5ed clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks
RZ/G1E does not have the SCU-SRC[0789] modules and module clocks.

Fixes: 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven b7c563c489 clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2
R-Car V2H and E2 do not have the PLL0CR register, but use a fixed
multiplier (depending on mode pins) and divider.

This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on
R-Car V2H and E2 from 1.5 GHz to 1 GHz.

Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G
Clock Pulse Generator support core.

Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Fixes: 0dce5454d5 ("ARM: shmobile: Initial r8a7794 SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven bb1953067c clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28.

Add support for that, but retain the old behavior for R-Car H3 ES1.x and
M3-W ES1.0 using a quirk.

Inspired by a patch by Takeshi Kihara in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
2017-03-30 13:26:02 +02:00
Geert Uytterhoeven 5573d19412 clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
  - More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
  - Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
    SYS-DMAC, VIN, VSPB, VSPI,
  - Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
    USB3-IF1, VSPD3, VSPI2,
  - Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.

The goal is twofold:
  1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
     for now,
  2. Make it clear which code supports ES1.x, so it can easily be
     identified and removed later, when production SoCs are deemed
     ubiquitous.

This is achieved by:
  - Updating the clock tables for the latest revision (ES2.0), but not
    removing clocks that only exist on earlier revisions (ES1.x),
  - Detecting the SoC revision at runtime using the new soc_device_match()
    API, and fixing up the clocks tables to match the actual SoC
    revision, by:
      - NULLifying core and module clocks of modules that do not exist,
      - Reparenting module clocks that have a different parent on ES1.x.

Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-30 13:25:50 +02:00
Geert Uytterhoeven 48d0341e41 clk: renesas: cpg-mssr: Add support for fixing up clock tables
The same SoC may have different clocks and/or module clock parents,
depending on SoC revision.  One option is to use different sets of clock
tables for each SoC revision.  However, if the differences are small, it
is much more space-efficient to have a single set of clock tables, and
fix those up at runtime instead.

Hence provide three helpers:
  - Two helpers to NULLify core and module clocks that do not exist on
    some revisions (NULLified clocks are skipped during the registration
    phase),
  - One helper to reparent module clocks that have different clock
    parents.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-30 13:25:24 +02:00
Geert Uytterhoeven cecbe87d73 clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and
PLL4 clock frequencies are off by a factor of two.

Inspired by a patch by Dien Pham in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Dien Pham <dien.pham.ry@renesas.com>
2017-03-21 11:12:23 +01:00
Geert Uytterhoeven 5f3a432a44 clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to make some
core clock configuration decisions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:12:23 +01:00
Geert Uytterhoeven c013fc7d23 clk: renesas: r8a7796: Reformat core clock table
For easier comparison with other clock drivers.
No functional changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:12:22 +01:00
Geert Uytterhoeven 3c969cec16 clk: renesas: r8a7795: Reformat core clock table
For easier comparison with other clock drivers.
No functional changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:12:22 +01:00
Geert Uytterhoeven 89aa58a395 clk: renesas: r8a7796: Correct name of watchdog clock
There's only a single watchdog clock, and it's named "rwdt".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:12:21 +01:00
Geert Uytterhoeven 2122b56d30 clk: renesas: r8a7795: Correct name of watchdog clock
There's only a single watchdog clock, and it's named "rwdt".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:12:21 +01:00
Geert Uytterhoeven a843ed3f6c clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which
maps to S3D1 on R-Car H3 ES1.x.
All module clocks must be sorted by clock ID.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
2017-03-21 11:12:07 +01:00
Sergei Shtylyov 6c8a931294 clk: renesas: r8a7796: Add IMR clocks
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[geert: Correct parent clocks]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-06 11:48:33 +01:00
Sergei Shtylyov 7d0a7c7bdf clk: renesas: r8a7795: Add IMR clocks
Add the IMR[0-3] clocks to the R8A7795 CPG/MSSR driver.

Based on the original (and large) patch by Konstantin Kozhevnikov
<Konstantin.Kozhevnikov@cogentembedded.com>.

Signed-off-by: Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-06 11:48:33 +01:00
Chris Brandt f59de56335 clk: renesas: mstp: ensure register writes complete
When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.

Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-16 10:36:05 -08:00
Stephen Boyd d646d812f3 clk: renesas: Updates for v4.11 (take two)
- Use CLK_IS_CRITICAL to handle critical clocks,
   - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
   - Add IIC-DVFS clocks for R-Car H3 and M3-W,
   - Minor cleanups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYiw4ZAAoJEEgEtLw/Ve77TfgQAJexnyItLU6fs3X5gx6smoWQ
 rPYXw0tWWfYEkmHJbF/vcfgC+sh/6sMVIn4IS6HqDWd1HdOtJPYTX8CvwlsQx0Ry
 NrcoConiFlatEM5sNf6w0aAUkwrDxIjZMNNnShfZRkZL7s9Jlhs5UUUbBY4uYPGG
 kJ7qr6hUoxQQ1S3z8iz/ol++tp/A+8zN0J+zLDdxcV0SRjxh/NWOOtjno9tWXXqd
 60eseC5FJNQOYV/6DXkpHsxNLsG6N2i7CVPC3SWxrijTQB1BDYAj/Pc3rD4u7Exo
 g2QTb8ywufWFi5ANhQX2oirewaiw6B2PoQyw7+7a/86OlTQVM7lfRb8hNnOJycqd
 X2YKBCNGeg4sysGURSYIDlzoq0ZDZnw7URc2+0HfeZXJjRCTmswpzRAv/wq4ILLK
 uAy5skI+XWKCuVk/w8lsWBo29hcu9Mm1lTsW739niJR4Kk9WQkK+JgF7x8FxzmLx
 7W8Rpbiz1N1D8ajlJWo/FAMdfx0SqevLlQlhCNVjExl7szmOcsF8RPnx542oRfwe
 wgJLCmCc9msP6FdWWSXB5BLNgPbaCAOoPfzpn5xouOe2xj6V5Ctv5kBTLfTqs+5S
 3SxsU08UZ4mxBeynjtuNwaX35KVs5Y1+FZQQD5MNxq8C2OvDx5ioWkH+YWFjOmgA
 9zghcMX9FG1KNLWh+RUD
 =WluB
 -----END PGP SIGNATURE-----

Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Use CLK_IS_CRITICAL to handle critical clocks,
  - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
  - Add IIC-DVFS clocks for R-Car H3 and M3-W,
  - Minor cleanups.

* tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add IIC-DVFS clock
  clk: renesas: r8a7795: Add IIC-DVFS clock
  clk: renesas: cpg-mssr: Add support for reset control
  clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock
  clk: renesas: cpg-mssr: Document suitability for RZ/G1
  dt-bindings: clock: renesas: cpg-mssr: Document reset control support
  clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff
  clk: renesas: mstp: Make INTC-SYS a critical clock
  clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
2017-01-27 11:51:37 -08:00
Khiem Nguyen d963654e10 clk: renesas: r8a7796: Add IIC-DVFS clock
This patch adds DVFS clock for R8A7796 SoC.

Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-01-27 08:59:24 +01:00
Keita Kobayashi 2c8e79898c clk: renesas: r8a7795: Add IIC-DVFS clock
This patch adds DVFS clock for R8A7795 SoC.

Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-01-27 08:59:00 +01:00
Geert Uytterhoeven 6197aa65c4 clk: renesas: cpg-mssr: Add support for reset control
Add optional support for the Reset Control feature of the Renesas Clock
Pulse Generator / Module Standby and Software Reset module on R-Car
Gen2, R-Car Gen3, and RZ/G1 SoCs.

This allows to reset SoC devices using the Reset Controller API.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-01-27 08:59:00 +01:00
Geert Uytterhoeven a4ea6a0f83 clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock
The spinlock is used to protect Read-Modify-Write register accesses,
which won't be limited to SMSTPCR register accesses.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27 08:58:59 +01:00
Geert Uytterhoeven 67c995b55e clk: renesas: cpg-mssr: Document suitability for RZ/G1
The Renesas CPG/MSSR driver is already in active use for RZ/G1 since
commits c0b2d75d2a ("clk: renesas: cpg-mssr: Add R8A7743 support")
and 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support").

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27 08:58:59 +01:00
Geert Uytterhoeven 1ce87dd2f0 clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff
As the function header of cpg_mstp_clock_register() is split in an
unusual way, "git diff" gets confused when changes to the body of
the function are made, and attributes them to the wrong function.

Reformat the function header to fix this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27 08:58:17 +01:00
Geert Uytterhoeven e34084fb9a clk: renesas: mstp: Make INTC-SYS a critical clock
INTC-SYS is the module clock for the GIC.  Accessing the GIC while it is
disabled causes:

    Unhandled fault: asynchronous external abort (0x1211) at 0x00000000

Currently, the GIC-400 driver cannot enable its module clock for several
reasons:
  - It does not use a platform device, so Runtime PM is not an option,
  - gic_of_init() runs before any clocks are registered, so it cannot
    enable the clock explicitly,
  - gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE()
    doesn't support deferred probing.

Hence we have to keep on relying on the boot loader for enabling the
module clock.

To prevent the module clock from being disabled when the CCF core thinks
it is unused, and thus causing a system lock-up, add a check to the MSTP
clock driver and enable CLK_IS_CRITICAL. This will make sure the module
clock is never disabled.

This is a hard dependency for describing the INTC-SYS clock in DT on
R-Mobile APE6 and R-Car Gen2.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-23 11:04:46 +01:00
Geert Uytterhoeven 72f5df2c2b clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
When the Renesas CPG/MSSR driver was introduced, it was anticipated that
critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag
soon.  However, CLK_ENABLE_HAND_OFF never made it upstream.

Instead, commit 32b9b10961 ("clk: Allow clocks to be marked as
CRITICAL") introduced CLK_IS_CRITICAL, a flag with slightly differing
semantics.  Still, it can be used to prevent e.g. the GIC module clock
from being turned off, until the GIC-400 driver has full support for
Runtime PM.

Hence migrate the Renesas CPG/MSSR driver from CLK_ENABLE_HAND_OFF to
CLK_IS_CRITICAL.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-23 11:04:45 +01:00
Stephen Boyd 3a1ba8ba67 clk: renesas: Updates for v4.11
- Add CAN and MSIOF related clocks for R-Car M3-W.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYeNTsAAoJEEgEtLw/Ve77UMAP/R5ZKHbcI443vlkzkVFQY6h+
 2cYRJPiqRQKCqMYDuLiV+n0aXitrsd8tV1I/vNgvvJhKqabzGtk+rTnLkmtqcnXQ
 oyiIzMxwbBbFeYrvCbhI/CZNbk5/pPAmvzUOLMnX8uxwbKaTF1QbWdu+moS8OtXx
 xFF/En3VC5yOfTqmSMH+dQ+GEdMRqMS53QbIaRxCezxTQ01CqtGDOqu9CmiMeF1O
 QZn2iYobh2bWA0eBXz8zF/VMJ5euxcqOoCa/xlC82p+BV3E6I4WKVwHz+nJHEsLk
 8Fz+jkpuatT1mT9mQ0bra4h+mHLkThy72pcp94NCGmsZGgN3qwcnU5QDE3qD9c2T
 9110rDmvMb0gstX7wFFNipa2qnMN7FPBaJOhV30QJ1kDwqM7h1CBo6NZVf/UCppP
 Wvnv4qz6H6rBvWm/4J1VBflZyYavSfivxNHsZZPGIX/MkxKNVZ5PMhdVC7+kaukF
 5EvbBXGX0CCk4hd5ZcLP9XzzG5O0sfImn6LnRQf8xtJAxRWQZ4YxHduIOSlp2NdH
 lzirS5Z2PU2enhOm/IEEtYCT8l8bQ1HN1PdOMfmDKGJTg+P+JbTW0NLr6MqWtS8a
 ATatzNZQ9ZYPToKzsJ+k5ZExqMRFYLkepSfH4bRAiD8YVscHSQzOH/8IZLD78G3O
 TYHSxujV45Pm6hzweMt8
 =66mZ
 -----END PGP SIGNATURE-----

Merge tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull renesas clk updates from Geert Uytterhoeven:

  - Add CAN and MSIOF related clocks for R-Car M3-W.

* tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add MSIOF controller clocks
  clk: renesas: r8a7796: Add CAN FD peripheral clock
  clk: renesas: r8a7796: Add CANFD clock
  clk: renesas: r8a7796: Add CAN peripheral clock
2017-01-20 15:17:50 -08:00
Hiromitsu Yamasaki e6bdf28eff clk: renesas: r8a7796: Add MSIOF controller clocks
This patch adds MSIOF{0,1,2,3} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:56:08 +01:00
Chris Paterson 0ece46c24f clk: renesas: r8a7796: Add CAN FD peripheral clock
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:56:08 +01:00
Chris Paterson 9e620beecd clk: renesas: r8a7796: Add CANFD clock
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:56:07 +01:00
Chris Paterson e00d20c99d clk: renesas: r8a7796: Add CAN peripheral clock
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:56:07 +01:00
Chris Brandt e2a33c34dd clk: renesas: mstp: Support 8-bit registers for r7s72100
The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.

Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21 16:33:14 -08:00
Sergei Shtylyov 9127d54bb8 clk: renesas: cpg-mssr: Add R8A7745 support
Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-10 15:29:30 +01:00
Sergei Shtylyov c0b2d75d2a clk: renesas: cpg-mssr: Add R8A7743 support
Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-10 15:29:28 +01:00
Sergei Shtylyov 4683893574 clk: renesas: cpg-mssr: Add common R-Car Gen2 support
Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module
Standby and Software Reset support code, using the CPG/MSSR driver
core.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-10 15:29:25 +01:00
Takeshi Kihara 0a30284b9f clk: renesas: r8a7795: Fix HDMI parent clock
Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07 15:16:18 +01:00
Niklas Söderlund e6e3558626 clk: renesas: r8a7796: Add VIN clocks
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07 15:16:18 +01:00
Niklas Söderlund 5fccac6d94 clk: renesas: r8a7796: Add CSI2 clocks
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07 15:16:17 +01:00
Geert Uytterhoeven a05de66ea6 Merge branch 'rcar-rst' into clk-renesas-for-v4.10
soc: renesas: Add R-Car RST driver for obtaining mode pin state
2016-11-02 20:53:26 +01:00
Geert Uytterhoeven 3e91d07bb5 clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()
The R-Car Gen2 board code no longer calls rcar_gen2_clocks_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02 20:44:20 +01:00
Geert Uytterhoeven b9fe9421d0 clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init()
The R-Car H1 board code no longer calls r8a7779_clocks_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02 20:44:17 +01:00
Geert Uytterhoeven 7978a78c82 clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()
The R-Car M1A board code no longer calls r8a7778_clocks_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02 20:44:14 +01:00
Geert Uytterhoeven ddab5aed8e clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()
All R-Car Gen3 clock drivers now obtain the values of the mode pins from
the R-Car RST driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-11-02 20:43:59 +01:00
Geert Uytterhoeven 05972d48d2 clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-11-02 20:43:56 +01:00
Geert Uytterhoeven 969921e0d2 clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driver
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-11-02 20:43:51 +01:00
Geert Uytterhoeven f84c9c3ca9 clk: renesas: rcar-gen2: Obtain mode pin values using RST driver
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.

Fall back to our own private copy of rcar_gen2_read_mode_pins() for
backward-compatibility with old DTs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02 20:43:48 +01:00
Geert Uytterhoeven 931db8a0c6 clk: renesas: r8a7779: Obtain mode pin values from R-Car RST driver
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RESET/WDT module.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02 20:43:45 +01:00
Geert Uytterhoeven 578d601cbc clk: renesas: r8a7778: Obtain mode pin values using R-Car RST driver
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RESET/WDT module.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02 20:43:42 +01:00
Laurent Pinchart dbdcc4f996 clk: renesas: r8a7796: Add DU and LVDS clocks
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:08 +01:00
Laurent Pinchart 88ddc1f8e3 clk: renesas: r8a7796: Add VSP clocks
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:07 +01:00
Laurent Pinchart f4407a6e26 clk: renesas: r8a7796: Add FCP clocks
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:07 +01:00
Geert Uytterhoeven 1b9fe7030c clk: renesas: cpg-mssr: Remove bogus commas from error messages
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:06 +01:00
Ramesh Shanmugasundaram cf31bc71c0 clk: renesas: r8a7796: Add DRIF clock
This patch adds DRIF module clocks for r8a7796 SoC.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:39:55 +01:00
Geert Uytterhoeven bc4725d902 clk: renesas: cpg-mssr: Fix inverted debug check
The intention was to enable the checks if debugging is enabled, not
disabled.

Fixes: f793d1e517 ("clk: shmobile: Add new CPG/MSSR driver core")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 17:18:43 +02:00
Geert Uytterhoeven 30ad3cf00e clk: renesas: rcar-gen3-cpg: Always use readl()/writel()
The R-Car Gen3 CPG/MSSR driver uses a mix of clk_readl()/clk_writel()
and readl()/writel() to access the clock registers. Settle on the
generic readl()/writel().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17 15:56:21 +02:00
Geert Uytterhoeven c1b5371b72 clk: renesas: cpg-mssr: Always use readl()/writel()
The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel()
and readl()/writel() to access the clock registers. Settle on the
generic readl()/writel().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17 15:56:21 +02:00
Ulrich Hecht 878f8baa02 clk: renesas: r8a7796: Add I2C clocks
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:21 +02:00
Ulrich Hecht 28aa831949 clk: renesas: r8a7796: Add HSCIF clocks
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:21 +02:00
Ulrich Hecht 951456c37d clk: renesas: r8a7796: Add SCIF clocks
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:20 +02:00
Ulrich Hecht cf8fe97cad clk: renesas: r8a7796: Add SYS-DMAC clocks
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:20 +02:00
Markus Elfring 0637a4c781 clk/Renesas-MSTP: Use kmalloc_array() in cpg_mstp_clocks_init()
A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16 16:13:09 -07:00
Stephen Boyd 209370566e clk: renesas: Updates for v4.9 (take three)
- External crystal selection for RZ/A1,
   - CMT clocks for R-Car H3 and M3-W,
   - RAVB and Thermal clocks for R-Car M3-W.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJX2P+AAAoJEEgEtLw/Ve77gqkP/R1qaA2sPGC2WntSVyYohD6y
 8ILwLkZl/1yr+tJO9+31io5dP1Bpzl9EbsPp+c1VbnT9Y/1k4LTPRx+8fk6HP/Hv
 L6VOyCgLRwnFr3RxdIeUC+q/2LVzekcsohHXDGRhUku8Und/dZwYjvqYbgKpmFDG
 mAe5vDDIRlJDN0wAWPcyepqc5MCQFn9ln0BlMyVgRyPb2bE2e0J6p3l0WXrHM/WB
 +lH0hOiWrV8SWXQpgVUcdlwA2OHspJcfUQzFdfO/Dih41EflLO/8GON/d/yWinZS
 PUXNYOwwLriDLEcIY8nQNd94WawA7TjKRgqaaXB1GSd6YB8HAhuos/RhVo/dCz2+
 IoRy0eq9Z5VHTH1xfHrqit/4x801wimDTADZV1McVmxGciQnljmJP7zcwodaX+bs
 dcRYt9VpJgQy8/lrPTgBmWkgp0xLld6W8IjCAgO5YsqAoKxb8IJ5TE8QDfyFwsgo
 8lWSxtA2gTl4MWE7nyAy4pj6useRRWpyVAWD6Hh7c4XHF1n0qNr0cT17X82xPwkO
 JWswWkp05zxh7rSbfBcA1DcJDKlmveE2PxiPY+5baX7eis7RJf9Vb4cJRydM0Sqw
 L9AzlYU/7Mhc6tf8IFTsa7PhajObGbkOgBTiTq9IqR8qGLUxtRWR8UHQ3kE8StdK
 tF38JRnHVHp/akk8kDTn
 =YlKA
 -----END PGP SIGNATURE-----

Merge tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull renesas clk driver updates from Geert Uytterhoeven:

  - External crystal selection for RZ/A1,
  - CMT clocks for R-Car H3 and M3-W,
  - RAVB and Thermal clocks for R-Car M3-W.

* tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add CMT clocks
  clk: renesas: r8a7795: Add CMT clocks
  clk: renesas: r8a7796: Add RAVB clock
  clk: renesas: r8a7796: Add THS/TSC clock
  clk: renesas: rz: Select EXTAL vs USB clock
2016-09-14 11:15:03 -07:00
Bui Duc Phuc 5fad71f58f clk: renesas: r8a7796: Add CMT clocks
This patch adds CMT module clocks for r8a7796 SoC.

Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:01 +02:00
Bui Duc Phuc 591d7b145a clk: renesas: r8a7795: Add CMT clocks
This patch adds CMT module clocks for r8a7795 SoC.

Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:00 +02:00
Laurent Pinchart 5576df81d2 clk: renesas: r8a7796: Add RAVB clock
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:00 +02:00
Khiem Nguyen 5086b0d6ce clk: renesas: r8a7796: Add THS/TSC clock
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-05 14:16:25 +02:00
Chris Brandt b452dfe92f clk: renesas: rz: Select EXTAL vs USB clock
Check the MD_CLK pin to determine the current clock mode in order to set
the pll clock parent correctly.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-05 14:16:25 +02:00
Stephen Boyd 911d49c7a0 clk: renesas: r8a7796: Add SDHI clocks
Add all clocks needed to use the SDHI interfaces on the Renesas R-Car M3-W
 (r8a7796) SoC.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJXxZzSAAoJEEgEtLw/Ve778BIQALrIpDRhYct/n1dT1TmEcpQr
 1DCcpxLDZJy4qY746X8clUD93ObG/03t6/VPlW3DnH7yvCSgNLXpE4KQ2KhMRAt/
 wQ6RvroBA0VlVpJePXbBHpfVBtVo5JXBGpcY0KEvppPzo1MAFxaXU+cP6OXcMqhx
 AZrW9fylOfxR5ft90sLGv7KrJpSZMuZt5CcrgdT7DPwO+AR2VHFjMg8Xtc35gqze
 EGD7RCt5mWGdAaiywC7fHx5m1NhezOXYeICHgU+NnoHX/+PYXrCze4jZrvpTa4QM
 LtVD/fOJiN8vQkG7UyyYmj/L9Pxy7BkCL1FQcIfCLNc8j6scF/5s/2222Vk9xya+
 ibEGZWdCDAm0Lbi3Qmuxa5Dd0eksyWMXcaziNqszYQCwDoudLnLj/ldjhbaUwKIA
 fWr5ZSS8ZRLzUdXdQ1UgFNbZkOP+cDWmY54TJxpvniZsZ2SmyJ7gPmlkEkWCy0CN
 CK5OlkgAjdHHWkpIx37xPMxVJOgQJ7NFmaul7zWGZQLZqftJPKi8+0XebVFhhplL
 uYUuRNcLRnBW+KwnvpNHlxi+El1nJx+u3CXxi54c00UE8sDp+4BtW077X9/BrijR
 xcQLG/QQ4Ro+sehWqBL7JiDWwVadcF/Urt0X/EqAusCwcyaz6TeXOFzCXkU3FEAr
 cOzPmKid6m9S6v/+/hns
 =rh+1
 -----END PGP SIGNATURE-----

Merge tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull renesas r8a7796 SDHI clock support from Geert Uytterhoeven:

Add all clocks needed to use the SDHI interfaces on the Renesas R-Car M3-W
(r8a7796) SoC.

* tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add SDIF clocks
  clk: renesas: r8a7796: Add GPIO clocks
2016-08-30 11:49:02 -07:00
Simon Horman 0749698133 clk: renesas: r8a7796: Add SDIF clocks
This patch adds SDIF clocks for R8A7796 SoC.

Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-23 10:30:41 +02:00
Takeshi Kihara 4e09508a89 clk: renesas: r8a7796: Add GPIO clocks
Add GPIO clocks for the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-19 09:38:40 +02:00
Stephen Boyd 91d17dc341 clk: renesas: r8a7796: Add watchdog clocks
Add all clocks related to the Watchdog Timer (WDT) controller on the
 Renesas R-Car M3-W (r8a7796) SoC.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJXtHgSAAoJEEgEtLw/Ve77DgcP/1620tFIcsgBC5bGlbA54+Zh
 z9r4cFiCgR7Xsi45UZijKvs8JtiBF5UwQIPokjHP7/KrQFyiQPga7IMUDDC3GwG2
 K50zK9q+d1pRl3Gjw8TCvfzYx+ooaGryNrvxyxrMSc5oFG3NtiBLiBdY2muPzTY0
 CYMW4dOy33FzG5wsYHEmUQAI+VOW65ovE2j0zoJ8Juj3KHJoe0kvf5dN4Pk0hUCR
 zZjGqUQ+9P5ZJG8/ToR8lrvOm8B6r9WmN9BLFD2eDmyU6osuPcmQ86pIICA9fHQS
 uoVv3qjmSqBenEhOKBB6Jp0fhAwwyu1XVSCmb17Rw93QfKDuy4yB1ZP8L+aTQoG9
 y1k4H80FFZTVoL5DLHGnB7iJMKUP0ROovoLYs1teGhIj8825C4EtxTITKKHwdbKy
 8hOCQBAENxIlX5y7cyhUkdR0O+8kV7r8NYt4LDnYp2oAMD6hgN/7kXf92+QeALxl
 B5u9Z2sKmPjfmXHE8eH2Z4/aAgMTqRfwaW6U8WFndF6IVsmGWz/p5fhvaLJY1zNf
 jK5LJWJmKiIkkpiGLhrhVVfl0pyJLQtmIxPv/fIMxUbp1rynT5o6jFOKaWsNRuA2
 8Stmca2L/8/BfLpk6z5vRZ95U00++LS5GPSr3PGBfg45HrOVAEUSvvj+vjaggkXR
 1YvK2hqYXGZ34pZcFA4i
 =0CHq
 -----END PGP SIGNATURE-----

Merge tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Merge r8a7796 watchdog clk support from Geert Uytterhoeven:

Add all clocks related to the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.

* tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add watchdog module clock
  clk: renesas: r8a7796: Add watchdog core clocks
2016-08-18 16:41:05 -07:00
Yoshihiro Shimoda e0cb1b8416 clk: renesas: r8a7795: Fix SD clocks
According to the datasheet, SDn clocks are from the SDSRC clock. And
the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal
core clock. Otherwise, since the sdhi driver will calculate clock for
a sd card using the wrong parent clock rate, and then performance will
be not good.

Fixes: 90c073e539 ("clk: shmobile: r8a7795: Add SD divider support")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-11 17:47:56 -07:00
Geert Uytterhoeven b51d527501 clk: renesas: r8a7796: Add watchdog module clock
Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
Geert Uytterhoeven 2570d4005d clk: renesas: r8a7796: Add watchdog core clocks
Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
Khiem Nguyen e4c82863fd clk: renesas: r8a7795: Add THS/TSC clock
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21 09:21:06 +02:00
Ramesh Shanmugasundaram 7d6cc0cddb clk: renesas: r8a7795: Add DRIF clock
This patch adds DRIF module clocks for r8a7795 SoC.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21 09:21:06 +02:00
Geert Uytterhoeven f7bb887fb8 clk: renesas: r8a7795: Correct lvds clock parent
According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.

Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-06-21 09:21:05 +02:00
Kieran Bingham a209568042 clk: renesas: r8a7795: Provide FDP1 clocks
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran@bingham.xyz>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21 09:21:05 +02:00
Sergei Shtylyov a233bffb6b clk: renesas: Add R8A7792 support
Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21 09:19:41 +02:00
Geert Uytterhoeven e4e2d7c388 clk: renesas: cpg-mssr: Add support for R-Car M3-W
Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-06 11:58:35 +02:00
Geert Uytterhoeven 5b1defde70 clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code
Extract the code to support parts common to all members of the R-Car
Gen3 SoC family into a separate file, to ease sharing among SoC-specific
drivers.

Note that while the cpg_pll_configs[] arrays and the selection of the
config based on the MODE bits are identical on R-Car H3 and R-Car M3-W,
they are not common, and may be different on other R-Car Gen3 SoCs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-06 11:58:31 +02:00
Geert Uytterhoeven d04a75af45 clk: renesas: cpg-mssr: Use always-on governor for Clock Domain
As a pure Clock Domain does not have the concept of powering the domain
itself, the CPG/MSTP driver does not provide power_off() and power_on()
callbacks.
However, the genpd core may still perform a dummy power down, causing
/sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's
status being "off-0".

Use the always-on governor to make sure the domain is never powered
down, and always shows up as "on" in pm_genpd_summary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-04-28 10:32:55 +02:00
Geert Uytterhoeven 93662500a1 clk: renesas: cpg-mssr: Postpone call to pm_genpd_init()
All local setup of the generic_pm_domain structure should have been
completed before calling pm_genpd_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-04-28 10:32:53 +02:00
Geert Uytterhoeven 20729300ca clk: renesas: mstp: Use always-on governor for Clock Domain
As a pure Clock Domain does not have the concept of powering the domain
itself, the CPG/MSTP driver does not provide power_off() and power_on()
callbacks.
However, the genpd core may still perform a dummy power down, causing
/sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's
status being "off-0".

Use the always-on governor to make sure the domain is never powered
down, and always shows up as "on" in pm_genpd_summary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-04-28 10:32:51 +02:00
Geert Uytterhoeven b3a52d75bc clk: renesas: mstp: Postpone call to pm_genpd_init()
All local setup of the generic_pm_domain structure should have been
completed before calling pm_genpd_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-04-28 10:32:41 +02:00
Niklas Söderlund ccce262de1 clk: renesas: r8a7795: Add VIN clocks
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-04-26 08:59:49 +02:00
Niklas Söderlund 0187d321a5 clk: renesas: r8a7795: Add CSI2 clocks
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-04-26 08:59:43 +02:00
Geert Uytterhoeven 2066390ad4 clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
The R-Car SYSC PM Domain driver has to power manage devices in power
areas using clocks. To reuse code and to share knowledge of clocks
suitable for power management, this is ideally done through the existing
cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks.

Hence these callbacks can no longer rely on their "domain" parameter
pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to
the clock domain in a static variable. cpg_mssr_attach_dev() has to
support probe deferral, as the R-Car SYSC PM Domain may be initialized,
and devices may be added to it, before the CPG/MSSR Clock Domain is
initialized.

Dummy callbacks are provided for the case where CPG/MSTP support is not
included, so the rcar-sysc driver won't have to care about this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-20 09:17:07 +02:00
Geert Uytterhoeven a5bd7f7a72 clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
Currently the decision whether to build the renesas-cpg-mssr and
clk-mstp drivers is handled by Makefile logic.  However, the rcar-sysc
driver will need to know whether CPG/MSSR and/or CPG/MSTP support are
available or not.

To avoid having to duplicate this logic, move it to Kconfig. Provide
non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig
symbols, which can be used by both Makefiles and C code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-20 09:16:58 +02:00
Geert Uytterhoeven 12a56817b3 clk: renesas: mstp: Clarify cpg_mstp_{at,de}tach_dev() domain parameter
Make it clear that the "domain" parameter of the cpg_mstp_attach_dev()
and cpg_mstp_detach_dev() functions is not used.

The cpg_mstp_attach_dev() and cpg_mstp_detach_dev() callbacks are not
only used by the CPG/MSTP Clock Domain driver, but also by the R-Mobile
SYSC PM Domain driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-04-07 17:27:13 +02:00
Geert Uytterhoeven da437d2d09 clk: renesas: cpg-mssr: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF
As of commit 71d076ceb2 ("ARM: shmobile: Enable PM and
PM_GENERIC_DOMAINS for SoCs with PM Domains"),
CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with a CPG/MSSR
block.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-07 17:27:10 +02:00
Geert Uytterhoeven 848fc67da5 clk: renesas: mstp: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF
As of commit 71d076ceb2 ("ARM: shmobile: Enable PM and
PM_GENERIC_DOMAINS for SoCs with PM Domains"),
CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with MSTP
clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-07 17:27:05 +02:00
Wolfram Sang 6248620b30 clk: renesas: r8a7795: add RWDT clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-04-06 09:48:49 +02:00
Wolfram Sang 1e6237e32e clk: renesas: r8a7795: add R clk
R can select between two parents. We deal with it like this: During
initialization, check if EXTALR is populated. If so, use it for R. If
not, use R_Internal. clk_mux doesn't help here because we don't want to
switch parents depending on the clock rate. The clock rate (and source)
should stay constant for the watchdog, so I think a setup like this
during initialization makes sense.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-04-06 09:48:46 +02:00
Wolfram Sang 5524a67f3a clk: renesas: r8a7795: add OSC and RINT clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-04-06 09:48:44 +02:00
Wolfram Sang 5d3927f655 clk: renesas: cpg-mssr: add generic support for read-only DIV6 clocks
Gen3 has two clocks (OSC and R) which look like a DIV6 clock but their
divider value is read-only and depends on MD pins at bootup. Add support
for such clocks by reading the value and adding a fixed clock.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-04-06 09:48:37 +02:00
Wolfram Sang ba8c1a81d4 clk: renesas: r8a7795: make SD clk definition specific for GEN3
About SD clocks: The clock type is Gen3 specific, the callbacks are all
Gen3 specific; I think the clock definition should also be Gen3 specific
and not in the general header file.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-29 09:24:02 +02:00
Ulrich Hecht 847e87920c clk: renesas: r8a7795: add PWM clock
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-29 09:24:02 +02:00
Simon Horman e8087b5b90 clk: renesas: div6: use RENESAS for #define
Name the #define guarding compilation of this header
__RENESAS_CLK_DIV6_H__ rather than __SHMOBILE_CLK_DIV6_H__.

This is a follow-up to renaming the directory in which this file lives from
shmobile to renesas which is in turn part of an ongoing process to migrate
from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that
RENESAS seems to be a more appropriate name than SHMOBILE for the majority
of Renesas ARM based SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 18:13:02 -07:00
Simon Horman 09c32427c9 clk: renesas: Rename header file renesas.h
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.

Along with the above mentioned Kconfig changes it seems appropriate
to also rename files.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 18:12:14 -07:00
Simon Horman b3a33077c0 clk: renesas: move drivers to renesas directory
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.

Along with the above mentioned Kconfig changes it seems appropriate
to also rename directories that only hold drivers for such SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:22:53 -08:00