Since the PIC is attached to UART1, it doesn't need a kernel device driver
of its own; but powering off is something that the kernel should do, so
this patch forcefully configures the UART1 for 19200 baud and sends the
character that tells the PIC to cut the power.
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Cc: Byron Bradley <byron.bbradley@gmail.com>
Acked-by: Nicolas Pitre <nico@marvell.com>
This patch adds support for the Orion/MV88F5182 based QNAP
TS-109/TS-209 NAS device. The driver for the S-35390A RTC
chip on this board has been submitted to LKML separately.
Signed-off-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Oyvind Repvik <repvik@kynisk.com>
Tested-by: Tim Ellis <timtimred@foonas.org>
Tested-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Tzachi Perelstein <tzachi@marvell.com>
The Orion I2C controller is the same one used in the Discovery
family (MV643XX). This patch include the common platform_device
stuff according to the existing i2c_mv64xxx.c conventions.
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
With this patch USB, SATA (via sata_mv), Ethernet, RTC, LEDs and NOR Flash
work.
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
add MV88F5181 support bits required by D-link DNS-323 patch
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Only serial, NOR, NAND, PCI and Ethernet is activated at the moment.
Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
serial, NOR, PCI and Ethernet is activated at the moment.
Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Orion Ethernet port is the same port used in the Discovery
family (MV643XX). This patch include the common platform_device
stuff according to the existing mv643xx_eth conventions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds support for Orion edge sensitive GPIO IRQs.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
CC: Thomas Gleixner <tglx@linutronix.de>
This is a pre-requisite for implementing proper hardware accelerated
GPIO LED flashing, and since we want proper locking, it's sensible to provide
the orion specific orion_gpio_set_blink() implementation within
mach-orion/gpio.c. The functions orion_gpio_set_blink() and gpio_set_value()
implicitly turn off each others state.
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Acked-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Orion has fully programable address map. There's a separate address
map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
Gigabit Ethernet, DMA/XOR engines, etc.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
This patch adds support for PCI and PCI-E controllers in the
Orion, Orion-NAS and Orion2.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Herbert Valerio Riedel