Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-7-dmitry.baryshkov@linaro.org
Split and extend existing CLK_AIF_OSR_DIV macro to implement mi2s
clocks. This simplifies the driver and removes extra code duplication.
The clock mi2s_div_clk used .enable_reg/.enable_bit, however these
fields are not used with by the clk_regmap_div_ops, thus they are
silently dropped. Clock enablement is handled in the mi2s_bit_div_clk
clock.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-6-dmitry.baryshkov@linaro.org
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-5-dmitry.baryshkov@linaro.org
By the clk framework already reference counts prepare/unprepare,
this if statement should be never true.
Signed-off-by: Li Zhengyu <lizhengyu3@huawei.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220613063327.89320-1-lizhengyu3@huawei.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The Snapdragon 670 adds and removes some clocks, adds new frequencies, and
adds a new GPLL (Global Phase-Locked Loop) in reference to SDM845, while
also removing some GDSCs. Despite these differences, there are many
similarities with SDM670. Add data for SDM670 in the driver for SDM845 to
reuse the most of the clock data.
Advantages and disadvantages of this approach:
+ maintenance applies to both sdm670 and sdm845 by default
+ less duplicate code (clocks) means smaller distro/pre-built kernels
with all drivers enabled
- clocks for both SoC's must be compiled if the user wants clocks for one
specific SoC (both or none)
- additional testing needed for sdm845 devices
Link: 443bd8d6e2%5E%21/#F10
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220914013922.198778-4-mailingradian@gmail.com
This driver will support more than one SoC's set of clocks, and set of
GDSCs. This behavior would be unclean with hard-coded static variables.
Support it by grabbing clocks, GDSCs, and BCRs in the match data.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220914013922.198778-3-mailingradian@gmail.com
Change a53-pll driver to use clk_parent_data rather than always looking
up the xo clock in the system clock list.
Note, this change also switches the a53-pll from the global `xo' clock
to the `xo_board', the clock that is specified as the `xo' clock in the
DT file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220909103137.3727830-1-dmitry.baryshkov@linaro.org
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220909105136.3733919-4-dmitry.baryshkov@linaro.org
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220909105136.3733919-3-dmitry.baryshkov@linaro.org
While working on the Fxtec Pro1X device, this error shows up with
my own minimal configuration:
gcc-sm6115: probe of 1400000.clock-controller failed with error -38
The clock driver depends on CONFIG_QCOM_GDSC and after enabling
that, the driver probes successfully.
Signed-off-by: Dang Huynh <danct12@riseup.net>
Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220910170207.1592220-1-danct12@riseup.net
The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks.
Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after
disable as this clock signal is used by hardware to turn ON memories in
LPASS. Also add the external mclk to interface external MI2S.
Fixes: a9dd26639d ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-6-git-send-email-quic_c_skakit@quicinc.com
Move registration of lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk to
lpass_aon_cc_sc7280_probe and register them only if "qcom,adsp-pil-mode"
is enabled in the lpass_aon DT node.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-3-git-send-email-quic_c_skakit@quicinc.com
In commit 3f905469c8 ("clk: qcom: gcc: Use floor ops for SDCC clocks")
floor ops were applied to SDCC2 only, but flooring is also required on
the SDCC1 apps clock which is used by the eMMC card on Sony's Nile
platform, and otherwise result in the typicial "Card appears
overclocked" warnings observed on many other platforms before:
mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz
mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz
mmc0: Card appears overclocked; req 104000000 Hz, actual 192000000 Hz
Fixes: f2a76a2955 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714203822.186448-1-marijn.suijten@somainline.org
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-7-dmitry.baryshkov@linaro.org
The gcc_mss_q6_bimc_axi_clk clock depends on the bimc_ddr_clk_src clock.
Move it down in the file to come after the source clock.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-6-dmitry.baryshkov@linaro.org
Move GPLL definitions up, before the clock parent tables, so that we can
use gpll hw clock fields in the parent_data/parent_hws tables.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-5-dmitry.baryshkov@linaro.org
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
This conversion fixes an issue present since the first version of this
driver. For the gp1_clk_src, gp2_clk_src and gp3_clk_src it was
impossible to select sleep_clk as a prent of the clock, since
num_parents was limited to 3 rather than 4. Switching to use num_parents
automatically makes sleep_clk available for selection.
Fixes: 3966fab8b6 ("clk: qcom: Add MSM8916 Global Clock Controller support")
Cc: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-4-dmitry.baryshkov@linaro.org
The Qualcomm DWC3 driver suspend implementation appears to be incomplete
for SC8280XP so keep the USB power domains always-on for now so that the
controller survives a suspend cycle.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220805121250.10347-3-johan+linaro@kernel.org
The Qualcomm PCIe driver does not yet implement suspend so to keep the
PCIe power domains always-on for now to avoid crashing during resume.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220805121250.10347-2-johan+linaro@kernel.org
Convert clk-rpm driver to parent_data API.
We keep the old pxo/cxo_board parent naming to keep compatibility with
old DT and we use the new pxo/cxo for new implementation where these
clock are defined in DTS.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706225321.26215-4-ansuelsmth@gmail.com
The Venus clock frequencies are a copy/paste error from msm8916. Looking
at the original clock-gcc-8936.c ftbl_gcc_venus0_vcodec0_clk defines we
have:
- 133 MHz
- 200 MHz
- 266 MHz
These values are born out by the relevant qualcomm documentation for the
msm8936/msm8939 Venus core performance levels.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-4-bryan.odonoghue@linaro.org
Standard CCI bus clock clocks are 19.2 MHz and 37.5 MHz. We already define
the 19.2 MHz but are missing the 37.5 MHz.
See qcom kernel drivers/clk/qcom/clock-gcc-8936.c::ftbl_gcc_camss_cci_clk[]
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-3-bryan.odonoghue@linaro.org
Adding a new item to this frequency table I see the existing indentation is
incorrect.
Fixes: 1664014e46 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-2-bryan.odonoghue@linaro.org
When a GDSC is found to be enabled at boot the pm_runtime state will
be unbalanced as the GDSC is later turned off. Fix this by increasing
the usage counter on the power-domain, in line with how we handled the
regulator state.
Fixes: 1b771839de ("clk: qcom: gdsc: enable optional power domain support")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220713212818.130277-1-bjorn.andersson@linaro.org
Both dispcc and videocc use mmcx power domain now.
Lets drop the supply mmcx from every gdsc.
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 266e5cf39a ("arm64: dts: qcom: sm8250: remove mmcx regulator")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220713143200.3686765-1-abel.vesa@linaro.org
CONFIG_CC_VERSION_TEXT="x86_64-linux-gnu-gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0"
make ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-, will be failed, like this:
drivers/clk/qcom/gpucc-sm8350.c:111:2: error: initializer element is not constant
gpu_cc_parent,
^~~~~~~~~~~~~
drivers/clk/qcom/gpucc-sm8350.c:111:2: note: (near initialization for ‘gpu_cc_parent_data_0[0]’)
drivers/clk/qcom/gpucc-sm8350.c:126:2: error: initializer element is not constant
gpu_cc_parent,
^~~~~~~~~~~~~
drivers/clk/qcom/gpucc-sm8350.c:126:2: note: (near initialization for ‘gpu_cc_parent_data_1[0]’)
make[3]: *** [drivers/clk/qcom/gpucc-sm8350.o] Error 1
It seems that nested constant initializer is not supported in GCC 7.4.0. For portability resons, we should fix it.
Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: 160758b05a ("clk: qcom: add support for SM8350 GPUCC")
Signed-off-by: Ren Zhijie <renzhijie2@huawei.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220714121144.71062-1-renzhijie2@huawei.com
Add support to the SM8350 display clock controller by extending the SM8250
display clock controller, which is almost identical but has some minor
differences.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-5-robert.foss@linaro.org
The GPUCC manages the clocks for the Adreno GPU found on the
sm8350 SoCs.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-3-robert.foss@linaro.org
Add and export Rivian EVO PLL configuration and control functions to
clock controller drivers, the PLL is used by SM8450 camera clock
controller.
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062739.2757912-1-vladimir.zapolskiy@linaro.org
Add controls for Lucid EVO PLL configuration and export control functions
to clock controller drivers, the PLL is used by Qualcomm SM8450 camera
and display clock controllers.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062729.2757893-1-vladimir.zapolskiy@linaro.org
After merging lucid and trion pll functions in commit 0b01489475
("clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid")
the function clk_trion_pll_configure() is left with an old description
header, which results in a W=2 compile time warning, fix it.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062711.2757855-1-vladimir.zapolskiy@linaro.org
Currently gcc-msm8960 driver manually creates tsens platform device
manually. It would be better to follow IPQ8064 approach, where tsens
device is defined as gcc's child device in the device tree. If nothing
else, it removes gcc's dependency on QFPROM, thus allowing clock
controller to be probed earlier.
Don't create it in case there are available child nodes (tsens) inside
the gcc's device tree node.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220521151437.1489111-4-dmitry.baryshkov@linaro.org
msm8916 has (at least) 6 "General Purpose" clocks that can be muxed to
SoC pins. These clocks are:
GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux)
GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself)
GP_MN : GPIO_110 (Doesn't seem to be described in gcc,
ignored in this patch)
Those clocks may be used as e.g. PWM sources for external peripherals.
Add more frequencies to the table for those clocks so it's possible
for arbitrary peripherals to make use of them.
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220612145955.385787-5-nikita@trvn.ru
Sometimes calculation of d value may result in 0 because of the
rounding after integer division. This causes the following error:
[ 113.969689] camss_gp1_clk_src: rcg didn't update its configuration.
[ 113.969754] WARNING: CPU: 3 PID: 35 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc8/0xdc
Make sure that D value is never zero.
Fixes: 7f891faf59 ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220612145955.385787-3-nikita@trvn.ru
In cases when MND is not enabled (e.g. when only Half Integer Divider is
used), setting D registers makes no effect.
Fail instead of making ineffective write.
Fixes: 7f891faf59 ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220612145955.385787-2-nikita@trvn.ru
On SM8250 two found VFE GDSC power domains shall not be operated, if
titan top is turned off, thus the former power domains will be set as
subdomains by a GDSC registration routine.
Fixes: 5d66ca79b5 ("clk: qcom: Add camera clock controller driver for SM8250")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220519214133.1728979-3-vladimir.zapolskiy@linaro.org
On SDM845 two found VFE GDSC power domains shall not be operated, if
titan top is turned off, thus the former power domains will be set as
subdomains by a GDSC registration routine.
Fixes: 78412c2620 ("clk: qcom: Add camera clock controller driver for SDM845")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220519214133.1728979-2-vladimir.zapolskiy@linaro.org
Currently, attempting to enable the UBI clocks will cause the stuck at
off warning to be printed and clk_enable will fail.
[ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off'
Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY
flag on UBI clocks, so lets do the same.
Fixes: 5736294aef ("clk: qcom: ipq8074: add NSS clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-6-robimarko@gmail.com
The built-in PPE engine has a dedicated clock for the EIP-197 crypto
engine.
So, since the required clock currently missing add support for it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
NSS port 5 and 6 frequency tables are currently broken and are causing a
wide ranges of issue like 1G not working at all on port 6 or port 5 being
clocked with 312 instead of 125 MHz as UNIPHY1 gets selected.
So, update the frequency tables with the ones from the downstream QCA 5.4
based kernel which has already fixed this.
Fixes: 7117a51ed3 ("clk: qcom: ipq8074: add NSS ethernet port clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-3-robimarko@gmail.com
UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it
will cause the wait_for_pll() to timeout and thus return the error
indicating that the PLL failed to lock.
This is bug in Huayra PLL HW for which SW workaround
is to set bit 26 of TEST_CTL register.
This is ported from the QCA 5.4 based downstream kernel.
Fixes: b8e7e51962 ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-2-robimarko@gmail.com
Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration
to work.
So, obtain the regmap that is required for the Alpha PLL configuration
and thus utilize the qcom_cc_really_probe() as we already have the regmap.
Then utilize the Alpha PLL configs from the downstream QCA 5.4 based
kernel to configure them.
This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the
kernel.
Fixes: b8e7e51962 ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-1-robimarko@gmail.com
Qcom docs indciate the following peripherals operating from System NOC
MM not from System NOC clocks.
- MDP
- VFE
- JPEGe
- Venus
Switch over the relevant parent pointers.
Fixes: 1664014e46 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504163835.40130-5-bryan.odonoghue@linaro.org
The msm8939 has an additional higher operating point for the multi-media
peripherals. The higher throughput MM componets operate off of the
system-mm noc not the system noc.
system_mm_noc_bfdcd_clk_src is the source clock for the higher frequency
capable system noc mm.
Maximum frequency for the MM SNOC is 400 MHz.
Fixes: 1664014e46 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504163835.40130-4-bryan.odonoghue@linaro.org
Reviewing qcom docs for the 8939 we can see the command rcgr is pointing to
the wrong address. bimc_ddr_clk_src_rcgr is @ 0x01832024 not 0x01832004.
Fixes: 1664014e46 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504163835.40130-3-bryan.odonoghue@linaro.org
Use the new phy-mux clock implementation for the PCIe pipe clock muxes
so that the pipe clock source is set to the QMP PHY PLL when the
downstream pipe clock is enabled and restored to the always-on XO when
it is again disabled.
This is needed to prevent the corresponding GDSC from hanging when
enabling or disabling the PCIe power domain, something which requires a
ticking source.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220628085707.16214-1-johan+linaro@kernel.org
Add apq/ipq8064 errata workaround where the sec_src clock gating needs to
be disabled during switching. krait-cc compatible is not enough to
handle this and limit this workaround to apq/ipq8064. We check machine
compatible to handle this.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220430054458.31321-4-ansuelsmth@gmail.com
Unlock spinlock after the mux switch is completed to prevent any corner
case of mux request while the switch still needs to be done.
Fixes: 4d7dc77bab ("clk: qcom: Add support for Krait clocks")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220430054458.31321-3-ansuelsmth@gmail.com
Use regmap_read_poll_timeout macro instead of do-while structure to tidy
things up. Also set a timeout to prevent any sort of system stall.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com
The PCIe GDSCs can be shared with other masters and should use the APCS
collapse-vote register when updating the power state.
This is specifically also needed to be able to disable power domains
that have been enabled by boot firmware using the vote register.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-4-johan+linaro@kernel.org
Recent Qualcomm platforms have APCS collapse-vote registers that allow
for sharing GDSCs with other masters (e.g. LPASS).
Add support for using such vote registers instead of the control
register when updating the GDSC power state.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-3-johan+linaro@kernel.org
Add a helper for updating the SW_COLLAPSE bit during initialisation and
state updates.
Note that the update during initialisation was relying on the
SW_COLLAPSE bit not having been set earlier rather than passing in zero
explicitly to clear the collapse vote.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-2-johan+linaro@kernel.org
Access to I/O of SM8250 camera clock controller IP depends on enabled
GCC_CAMERA_AHB_CLK clock supplied by global clock controller, the latter
one is inited on subsys level, so, to satisfy the dependency, it would
make sense to deprive the init level of camcc-sm8250 driver.
If both drivers are compiled as built-in, there is a change that a board
won't boot up due to a race, which happens on the same init level.
Fixes: 5d66ca79b5 ("clk: qcom: Add camera clock controller driver for SM8250")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220518103554.949511-1-vladimir.zapolskiy@linaro.org
Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220608105238.2973600-4-dmitry.baryshkov@linaro.org
Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220608105238.2973600-3-dmitry.baryshkov@linaro.org
On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.
Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. Supplement the regmap-mux with
the new clk_regmap_phy_mux type, which implements such multiplexers
as a simple gate clocks.
This is possible since each of these multiplexers has just two clock
sources: one coming from the PHY and a reference (XO) one. If the clock
is running off the from-PHY source, report it as enabled. Report it as
disabled otherwise (if it uses reference source).
This way the PHY will disable the pipe clock before turning off the
GDSC, which in turn would lead to disabling corresponding pipe_clk_src
(and thus it being parked to a safe, reference clock source). And vice
versa, after enabling the GDSC the PHY will enable the pipe clock, which
would cause pipe_clk_src to be switched from a safe source to the
working one.
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220608105238.2973600-2-dmitry.baryshkov@linaro.org
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220617122922.769562-6-dmitry.baryshkov@linaro.org
Move clock parent tables down, after the MMPLL declrataions, so that we
can use gpll hw clock fields in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220617122922.769562-5-dmitry.baryshkov@linaro.org
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220617122922.769562-4-dmitry.baryshkov@linaro.org
The sleep/wake state doesn't need to be set here because of specific
RPMh behavior that carries over the active state when sleep/wake state
hasn't been modified. Add a note to the code so we aren't tempted to set
the sleep/wake states.
Cc: Alex Elder <elder@linaro.org>
Cc: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220517190949.2922197-1-swboyd@chromium.org
framework that simplifies a runtime PM call. Otherwise the majority of the diff
falls to a few SoC drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some
new hardware support and what comes along with that is quite a few lines of
data and some clk_ops code. Beyond the new hardware support we have the usual
pile of driver updates that add missing clks on already supported SoCs or fix
up problems like bad clk tree descriptions. It's nice to see that more drivers
are moving to clk_hw based APIs too.
New Drivers:
- Add STM32MP13 RCC driver (Reset Clock Controller)
- MediaTek MT8186 SoC clk support
- Airoha EN7523 SoC system clocks
- Clock driver for exynosautov9 SoC
- Renesas R-Car V4H and RZ/V2M SoCs
- Renesas RZ/G2UL SoC
- LPASS clk driver for Qualcomm sc7280 SoC
- GCC clk driver for Qualcomm SC8280XP SoC
Updates:
- SDCC uses floor clk ops on Qualcomm MSM8976
- Add modem reset and fix RPM clks on Qualcomm MSM8976
- Add the two missing CLKOUT clocks for U8500/DB8500 SoC
- Mark some clks critical on Ingenic X1000
- Convert ux500 to clk_hw
- Move MediaTek driver to clk_hw provider APIs
- Use i2c driver probe_new to avoid id scans
- Convert a number of Rockchip dt bindings to YAML
- Mark hclk_vo critical on Rockchip rk3568
- Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
- Various cleanups like memory allocation error checks and plugged leaks
- Allwinner H6 RTC clock support
- Allwinner H616 32 kHz clock support
- Add the Universal Flash Storage clock on Renesas R-Car S4-8
- Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas RZ/G2UL
- Add display clock support on Renesas RZ/G2L
- Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
- Add 27 MHz phy PLL ref clock on i.MX
- Add mcore_booted module parameter to tell kernel M core has already booted
for i.MX
- Remove snvs clock on i.MX because it was for secure world only
- Add dt bindings for i.MX8MN GPT
- Add DISP2 pixel clock for i.MX8MP
- Add clkout1/2 for i.MX8MP
- Fix parent clock of ubs_root_clk for i.MX8MP
- Implement better RCG parking on Qualcomm SoCs using the shared RCG clk ops
- Kerneldoc fixes
- Switch Tegra BPMP to determine_rate clk op
- Add a pointer to dt schema for generic clock bindings
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Mainly driver updates this time around.
There's a single patch to the core clk framework that simplifies a
runtime PM call. Otherwise the majority of the diff falls to a few SoC
drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some new
hardware support and what comes along with that is quite a few lines
of data and some clk_ops code.
Beyond the new hardware support we have the usual pile of driver
updates that add missing clks on already supported SoCs or fix up
problems like bad clk tree descriptions. It's nice to see that more
drivers are moving to clk_hw based APIs too.
New Drivers:
- Add STM32MP13 RCC driver (Reset Clock Controller)
- MediaTek MT8186 SoC clk support
- Airoha EN7523 SoC system clocks
- Clock driver for exynosautov9 SoC
- Renesas R-Car V4H and RZ/V2M SoCs
- Renesas RZ/G2UL SoC
- LPASS clk driver for Qualcomm sc7280 SoC
- GCC clk driver for Qualcomm SC8280XP SoC
Updates:
- SDCC uses floor clk ops on Qualcomm MSM8976
- Add modem reset and fix RPM clks on Qualcomm MSM8976
- Add the two missing CLKOUT clocks for U8500/DB8500 SoC
- Mark some clks critical on Ingenic X1000
- Convert ux500 to clk_hw
- Move MediaTek driver to clk_hw provider APIs
- Use i2c driver probe_new to avoid id scans
- Convert a number of Rockchip dt bindings to YAML
- Mark hclk_vo critical on Rockchip rk3568
- Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
- Various cleanups like memory allocation error checks and plugged
leaks
- Allwinner H6 RTC clock support
- Allwinner H616 32 kHz clock support
- Add the Universal Flash Storage clock on Renesas R-Car S4-8
- Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas
RZ/G2UL
- Add display clock support on Renesas RZ/G2L
- Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
- Add 27 MHz phy PLL ref clock on i.MX
- Add mcore_booted module parameter to tell kernel M core has already
booted for i.MX
- Remove snvs clock on i.MX because it was for secure world only
- Add dt bindings for i.MX8MN GPT
- Add DISP2 pixel clock for i.MX8MP
- Add clkout1/2 for i.MX8MP
- Fix parent clock of ubs_root_clk for i.MX8MP
- Implement better RCG parking on Qualcomm SoCs using the shared RCG
clk ops
- Kerneldoc fixes
- Switch Tegra BPMP to determine_rate clk op
- Add a pointer to dt schema for generic clock bindings"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (168 commits)
Revert "clk: qcom: regmap-mux: add pipe clk implementation"
Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()
clk: stm32mp13: add safe mux management
clk: stm32mp13: add multi mux function
clk: stm32mp13: add all STM32MP13 kernel clocks
clk: stm32mp13: add all STM32MP13 peripheral clocks
clk: stm32mp13: manage secured clocks
clk: stm32mp13: add composite clock
clk: stm32mp13: add stm32 divider clock
clk: stm32mp13: add stm32_gate management
clk: stm32mp13: add stm32_mux clock management
clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
clk: ti: clkctrl: replace usage of found with dedicated list iterator variable
clk: ti: composite: Prefer kcalloc over open coded arithmetic
dt-bindings: clock: exynosautov9: correct count of NR_CLK
clk: mediatek: mt8173: Switch to clk_hw provider APIs
clk: mediatek: Switch to clk_hw provider APIs
...
Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Pipe clocks
has been updated to use newer and simpler clk_regmap_phy_mux_ops. Drop
the regmap-mux-safe clock ops now.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220521005343.1429642-4-dmitry.baryshkov@linaro.org
Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Revert the
commit that switches gcc-sc7280 driver to use regmap_mux_safe.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220521005343.1429642-3-dmitry.baryshkov@linaro.org
Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Revert the
commit that switches gcc-sm8450 driver to use regmap_mux_safe.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220521005343.1429642-2-dmitry.baryshkov@linaro.org
As GDSCs are turned on and off some associated clocks are momentarily
enabled for house keeping purposes. For this, and similar, purposes the
"shared RCGs" will park the RCG on a source clock which is known to be
available.
When the RCG is parked, a safe clock source will be selected and
committed, then the original source would be written back and upon enable
the change back to the unparked source would be committed.
But starting with SM8350 this fails, as the value in CFG is committed by
the GDSC handshake and without a ticking parent the GDSC enablement will
time out.
This becomes a concrete problem if the runtime supended state of a
device includes disabling such rcg's parent clock. As the device
attempts to power up the domain again the rcg will fail to enable and
hence the GDSC enablement will fail, preventing the device from
returning from the suspended state.
This can be seen in e.g. the display stack during probe on SM8350.
To avoid this problem, the software needs to ensure that the RCG is
configured to a active parent clock while it is disabled. This is done
by caching the CFG register content while the shared RCG is parked on
this safe source.
Writes to M, N and D registers are committed as they are requested. New
helpers for get_parent() and recalc_rate() are extracted from their
previous implementations and __clk_rcg2_configure() is modified to allow
it to operate on the cached value.
Fixes: 7ef6f11887 ("clk: qcom: Configure the RCGs to a safe source as needed")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220426212136.1543984-1-bjorn.andersson@linaro.org
Add support for the Global Clock Controller found in the Qualcomm
SC8280XP platform.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org
Just like in case of other SoCs change SDCC1/SDCC2 ops
to floor to avoid overclocking controller.
This commit only sets SDCC1/SDCC2 which are used for EMMC/SDCARD.
Leave SDCC3 because on this platform it's mostly used for WIFI/BT chips,
like on Sony Loire familly devices.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220426073048.11509-2-a39.skl@gmail.com
MSM8976 does not have rpm clock named mmssnoc,
instead it's called sysmmnoc, drop define and reuse.
While we are at it add XO clock to list.
Fixes: 7d61e773c3 ("clk: qcom: smd: Add support for MSM8976 rpm clocks")
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220426090226.27293-1-a39.skl@gmail.com
Since the commit 948fb0969e ("clk: Always clamp the rounded rate"),
the clk_core_determine_round_nolock() would clamp the requested rate
between min and max rates from the rate request. Normally these fields
would be filled by clk_core_get_boundaries() called from
clk_round_rate().
However clk_gfx3d_determine_rate() uses a manually crafted rate request,
which did not have these fields filled. Thus the requested frequency
would be clamped to 0, resulting in weird frequencies being requested
from the hardware.
Fix this by filling min_rate and max_rate to the values valid for the
respective PLLs (0 and ULONG_MAX).
Fixes: 948fb0969e ("clk: Always clamp the rounded rate")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220419235447.1586192-1-dmitry.baryshkov@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reported-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add four clocks which need to be manipulated in order to initialize the AHB
bus which exposes the SCC block in the global address space.
If a device is known to be configured such that writing to these
registers from Linux is not permitted, the 'protected-clocks'
device tree property must be used to denote that fact.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411072156.24451-3-michael.srba@seznam.cz
The Low Power Audio subsystem core and audio clocks are required for
Audio client to be able to request for the clocks and power domains.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220223172248.18877-2-tdas@codeaurora.org
Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220323085010.1753493-4-dmitry.baryshkov@linaro.org
Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220323085010.1753493-3-dmitry.baryshkov@linaro.org
On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.
Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. As we are changing the parent
behind the back of the clock framework, also implement custom
set_parent() and get_parent() operations behaving accroding to the clock
framework expectations (cache the new parent if the clock is in disabled
state, return cached parent).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220323085010.1753493-2-dmitry.baryshkov@linaro.org
clk_set_rate_range() works so that the frequency is re-evaulated each time the
rate is changed. Previously we wouldn't let clk providers see a rate that was
different if it was still within the range, which could be bad for power if the
clk could run slower when a range expands. Now the clk provider can decide to
do something differently when the constraints change. This broke Nvidia's clk
driver so we had to wait for the fix for that to bake a little more in -next.
The rate range patch series also introduced a kunit suite for the clk framework
that we're going to extend in the next release. It already made it easy to find
corner cases in the rate range patches so I'm excited to see it cover more clk
code and increase our confidence in core framework patches in the future. I
also added a kunit test for the basic clk gate code and that work will continue
to cover more basic clk types: muxes, dividers, etc.
Beyond the core code we have the usual set of clk driver updates and additions.
Qualcomm again dominates the diffstat here with lots more SoCs being supported
and i.MX follows afer that with a similar number of SoCs gaining clk drivers.
Beyond those large additions there's drivers being modernized to use
clk_parent_data so we can move away from global string names for all the clks
in an SoC. Finally there's lots of little fixes all over the clk drivers for
typos, warnings, and missing clks that aren't critical and get batched up
waiting for the next merge window to open. Nothing super big stands out in the
driver pile. Full details are below.
Core:
- Make clk_set_rate_range() re-evaluate the limits each time
- Introduce various clk_set_rate_range() tests
- Add clk_drop_range() to drop a previously set range
New Drivers:
- i.MXRT1050 clock driver and bindings
- i.MX8DXL clock driver and bindings
- i.MX93 clock driver and bindings
- NCO blocks on Apple SoCs
- Audio clks on StarFive JH7100 RISC-V SoC
- Add support for the new Renesas RZ/V2L SoC
- Qualcomm SDX65 A7 PLL
- Qualcomm SM6350 GPU clks
- Qualcomm SM6125, SM6350, QCS2290 display clks
- Qualcomm MSM8226 multimedia clks
Updates:
- Kunit tests for clk-gate implementation
- Terminate arrays with sentinels and make that clearer
- Cleanup SPDX tags
- Fix typos in comments
- Mark mux table as const in clk-mux
- Make the all_lists array const
- Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add
support for dynamic mode
- Clock configuration on Microchip PolarFire SoCs
- Free allocations on probe error in Mediatek clk driver
- Modernize Mediatek clk driver by consolidating code
- Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on
Renesas R-Car S4-8
- Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates)
- Use of_device_get_match_data() instead of open-coding on Rockchip rk3568
- Reintroduce the expected fractional-divider behaviour that disappeared
with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
- Remove SYS PLL 1/2 clock gates for i.MX8M*
- Remove AUDIO MCLK ROOT from i.MX7D
- Add fracn gppll clock type used by i.MX93
- Add new composite clock for i.MX93
- Add missing media mipi phy ref clock for i.MX8MP
- Fix off by one in imx_lpcg_parse_clks_from_dt()
- Rework for the imx pll14xx
- sama7g5: One low priority fix for GCLK of PDMC
- Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
- Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
- Add CAN-FD clocks on Renesas R-Car V3U
- Qualcomm SC8280XP RPMCC
- Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
- Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML
- Convert various Qualcomm drivers to use clk_parent_data
- Remove test clocks from various Qualcomm drivers
- Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
- Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
- Better pixel clk frequency support on Qualcomm RCG2 clks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"There's one large change in the core clk framework here. We change how
clk_set_rate_range() works so that the frequency is re-evaulated each
time the rate is changed. Previously we wouldn't let clk providers see
a rate that was different if it was still within the range, which
could be bad for power if the clk could run slower when a range
expands. Now the clk provider can decide to do something differently
when the constraints change. This broke Nvidia's clk driver so we had
to wait for the fix for that to bake a little more in -next.
The rate range patch series also introduced a kunit suite for the clk
framework that we're going to extend in the next release. It already
made it easy to find corner cases in the rate range patches so I'm
excited to see it cover more clk code and increase our confidence in
core framework patches in the future. I also added a kunit test for
the basic clk gate code and that work will continue to cover more
basic clk types: muxes, dividers, etc.
Beyond the core code we have the usual set of clk driver updates and
additions. Qualcomm again dominates the diffstat here with lots more
SoCs being supported and i.MX follows afer that with a similar number
of SoCs gaining clk drivers. Beyond those large additions there's
drivers being modernized to use clk_parent_data so we can move away
from global string names for all the clks in an SoC. Finally there's
lots of little fixes all over the clk drivers for typos, warnings, and
missing clks that aren't critical and get batched up waiting for the
next merge window to open. Nothing super big stands out in the driver
pile. Full details are below.
Core:
- Make clk_set_rate_range() re-evaluate the limits each time
- Introduce various clk_set_rate_range() tests
- Add clk_drop_range() to drop a previously set range
New Drivers:
- i.MXRT1050 clock driver and bindings
- i.MX8DXL clock driver and bindings
- i.MX93 clock driver and bindings
- NCO blocks on Apple SoCs
- Audio clks on StarFive JH7100 RISC-V SoC
- Add support for the new Renesas RZ/V2L SoC
- Qualcomm SDX65 A7 PLL
- Qualcomm SM6350 GPU clks
- Qualcomm SM6125, SM6350, QCS2290 display clks
- Qualcomm MSM8226 multimedia clks
Updates:
- Kunit tests for clk-gate implementation
- Terminate arrays with sentinels and make that clearer
- Cleanup SPDX tags
- Fix typos in comments
- Mark mux table as const in clk-mux
- Make the all_lists array const
- Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding
and add support for dynamic mode
- Clock configuration on Microchip PolarFire SoCs
- Free allocations on probe error in Mediatek clk driver
- Modernize Mediatek clk driver by consolidating code
- Add watchdog (WDT), I2C, and pin function controller (PFC) clocks
on Renesas R-Car S4-8
- Improve the clocks for the Rockchip rk3568 display outputs
(parenting, pll-rates)
- Use of_device_get_match_data() instead of open-coding on Rockchip
rk3568
- Reintroduce the expected fractional-divider behaviour that
disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
- Remove SYS PLL 1/2 clock gates for i.MX8M*
- Remove AUDIO MCLK ROOT from i.MX7D
- Add fracn gppll clock type used by i.MX93
- Add new composite clock for i.MX93
- Add missing media mipi phy ref clock for i.MX8MP
- Fix off by one in imx_lpcg_parse_clks_from_dt()
- Rework for the imx pll14xx
- sama7g5: One low priority fix for GCLK of PDMC
- Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
- Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
- Add CAN-FD clocks on Renesas R-Car V3U
- Qualcomm SC8280XP RPMCC
- Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
- Rework Qualcomm GCC bindings and convert SDM845 camera bindig to
YAML
- Convert various Qualcomm drivers to use clk_parent_data
- Remove test clocks from various Qualcomm drivers
- Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
- Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
- Better pixel clk frequency support on Qualcomm RCG2 clks"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
clk: zynq: Update the parameters to zynq_clk_register_periph_clk
clk: zynq: trivial warning fix
clk: Drop the rate range on clk_put()
clk: test: Test clk_set_rate_range on orphan mux
clk: Initialize orphan req_rate
dt-bindings: clock: drop useless consumer example
dt-bindings: clock: renesas: Make example 'clocks' parsable
clk: qcom: gcc-msm8994: Fix gpll4 width
dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml
clk: rs9: Add Renesas 9-series PCIe clock generator driver
clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
clk: visconti: prevent array overflow in visconti_clk_register_gates()
dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
clk: sifive: Move all stuff into SoCs header files from C files
clk: sifive: Add SoCs prefix in each SoCs-dependent data
riscv: dts: Change the macro name of prci in each device node
dt-bindings: change the macro name of prci in header files and example
clk: sifive: duplicate the macro definitions for the time being
clk: qcom: sm6125-gcc: fix typos in comments
clk: ti: clkctrl: fix typos in comments
...
- Make clk_set_rate_range() re-evaluate the limits each time
- Introduce various clk_set_rate_range() tests
- Add clk_drop_range() to drop a previously set range
- Support for NCO blocks on Apple SoCs
* clk-range:
clk: Drop the rate range on clk_put()
clk: test: Test clk_set_rate_range on orphan mux
clk: Initialize orphan req_rate
clk: bcm: rpi: Run some clocks at the minimum rate allowed
clk: bcm: rpi: Set a default minimum rate
clk: bcm: rpi: Add variant structure
clk: Add clk_drop_range
clk: Always set the rate on clk_set_range_rate
clk: Use clamp instead of open-coding our own
clk: Always clamp the rounded rate
clk: Enforce that disjoints limits are invalid
clk: Introduce Kunit Tests for the framework
clk: Fix clk_hw_get_clk() when dev is NULL
* clk-uniphier:
clk: uniphier: Fix fixed-rate initialization
* clk-apple:
clk: clk-apple-nco: Allow and fix module building
MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE
clk: clk-apple-nco: Add driver for Apple NCO
dt-bindings: clock: Add Apple NCO
* clk-qcom: (61 commits)
clk: qcom: gcc-msm8994: Fix gpll4 width
dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml
clk: qcom: Add display clock controller driver for SM6125
dt-bindings: clock: add QCOM SM6125 display clock bindings
clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig
clk: qcom: gcc: Add emac GDSC support for SM8150
clk: qcom: gcc: sm8150: Fix some identation issues
clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150
clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
clk: qcom: clk-rcg2: Update the frac table for pixel clock
clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
clk: qcom: smd: Add missing MSM8998 RPM clocks
clk: qcom: smd: Add missing RPM clocks for msm8992/4
dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks
clk: qcom: gcc-ipq806x: add CryptoEngine resets
dt-bindings: reset: add ipq8064 ce5 resets
clk: qcom: gcc-ipq806x: add CryptoEngine clocks
dt-bindings: clock: add ipq8064 ce5 clk define
clk: qcom: gcc-ipq806x: add additional freq for sdc table
clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
...
The gpll4 postdiv is actually a div4, so make sure that Linux is aware of
this.
This fixes the following error messages:
mmc1: Card appears overclocked; req 200000000 Hz, actual 343999999 Hz
mmc1: Card appears overclocked; req 400000000 Hz, actual 687999999 Hz
Fixes: aec89f78cf ("clk: qcom: Add support for msm8994 global clock controller")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220319174940.341137-1-konrad.dybcio@somainline.org
Tested-by: Petr Vorel <petr.vorel@gmail.com>
Reviewed-by: Petr Vorel <petr.vorel@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the display clock controller found on SM6125
based devices. This allows display drivers to probe and
control their clocks.
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220303131812.302302-4-marijn.suijten@somainline.org
In order to keep at least the list of `CONFIG_SM_` drivers sorted
alphabetically, SDX_GCC_65 should have been moved one line up. This in
turn makes it easier and cleaner to add the followup SM_DISPCC_6125
driver in the right place, right before SM_DISPCC_8250.
Fixes: d79afa2013 ("clk: qcom: Add SDX65 GCC support")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220303131812.302302-2-marijn.suijten@somainline.org
Support the new numerator and denominator for pixel clock on SM8350 and
support rgb101010, RGB888 use cases on SM8450.
Fixes: 99cbd064b0 ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220227175536.3131-2-tdas@codeaurora.org
The display pixel clock has a requirement on certain newer platforms to
support M/N as (2/3) and the final D value calculated results in
underflow errors.
As the current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range.
Fixes: 99cbd064b0 ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org
Add missing RPM-provided clocks on msm8998 and reorder the definitions
where needed.
Tested-by: Jami Kettunen <jami.kettunen@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: Caleb Connolly <caleb@connolly.tech>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226214126.21209-3-konrad.dybcio@somainline.org
XO and MSS_CFG were omitted when first adding the clocks for these SoCs.
Add them, and while at it, move the XO clock to the top of the definition
list, as ideally everyone should start using it sooner or later..
Fixes: b429784499 ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226214126.21209-2-konrad.dybcio@somainline.org
Add additional freq supported for the sdc table. The ops are changed to
the floor_ops to handle a freq request of 52kHz where we need to provide
a freq of 51.2kHz instead for stability reason.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com
Add clk_rcg_floor_ops for clock that can't provide a stable freq and
require to use a floor freq to provide the requested frequency.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-10-ansuelsmth@gmail.com
Some clocks are used by other devices present on the SoC. For example
the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to
reject any regulator change command. These clock should never be
disabled.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-9-ansuelsmth@gmail.com
Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
clocked to 800MHz. Add these missing freq to the gcc driver.
Set the freq_tbl for the ubi32_cores to the correct values based on the
machine compatible.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com
Use ARRAY_SIZE for num_parents instead of hardcoding the value.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com
Convert parent_names to parent_data to modernize the driver.
Where possible use parent_hws directly.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com
The Qualcomm SC8280XP platform exposes 5 clocks through the RPMh clock
controller. Add these, and the relates active-only variants, to the RPMh
clock controller driver.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220223044516.3776637-2-bjorn.andersson@linaro.org
On SC7180 we observe black screens because the gdsc is being
enabled/disabled very rapidly and the GDSC FSM state does not work as
expected. This is due to the fact that the GDSC reset value is being
updated from SW.
The recommended transition delay for mdss core gdsc updated for
SC7180/SC7280/SM8250.
Fixes: dd3d066221 ("clk: qcom: Add display clock controller driver for SC7180")
Fixes: 1a00c962f9 ("clk: qcom: Add display clock controller driver for SC7280")
Fixes: 80a18f4a85 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/20220223185606.3941-2-tdas@codeaurora.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sboyd@kernel.org: lowercase hex]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
GDSCs have multiple transition delays which are used for the GDSC FSM
states. Older targets/designs required these values to be updated from
gdsc code to certain default values for the FSM state to work as
expected. But on the newer targets/designs the values updated from the
GDSC driver can hamper the FSM state to not work as expected.
On SC7180 we observe black screens because the gdsc is being
enabled/disabled very rapidly and the GDSC FSM state does not work as
expected. This is due to the fact that the GDSC reset value is being
updated from SW.
Thus add support to update the transition delay from the clock
controller gdscs as required.
Fixes: 45dd0e5531 ("clk: qcom: Add support for GDSCs)
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/20220223185606.3941-1-tdas@codeaurora.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use floor ops on SDCC1 APPS clock in order to round down selected clock
frequency and avoid overclocking SD/eMMC cards.
For example, currently HS200 cards were failling tuning as they were
actually being clocked at 384MHz instead of 192MHz.
This caused some boards to disable 1.8V I/O and force the eMMC into the
standard HS mode (50MHz) and that appeared to work despite the eMMC being
overclocked to 96Mhz in that case.
There was a previous commit to use floor ops on SDCC clocks, but it looks
to have only covered SDCC2 clock.
Fixes: 9607f6224b ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks")
Signed-off-by: Dirk Buchwalder <buchwalder@posteo.de>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220210173100.505128-1-robimarko@gmail.com
Just like in commit 05cf3ec00d ("clk: qcom: gcc-msm8996: Drop (again)
gcc_aggre1_pnoc_ahb_clk") adding NoC clocks turned out to be a huge
mistake, as they cause a lot of issues at little benefit (basically
letting Linux know about their children's frequencies), especially when
mishandled or misconfigured.
Adding these ones broke SDCC approx 99 out of 100 times, but that somehow
went unnoticed. To prevent further issues like this one, remove them.
This commit is effectively a revert of 74a33fac3a ("clk: qcom:
gcc-msm8994: Add missing NoC clocks") with ABI preservation.
Fixes: 74a33fac3a ("clk: qcom: gcc-msm8994: Add missing NoC clocks")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220217232408.78932-1-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Modify the existing MSM8974 multimedia clock controller driver to
support the MMCC found on MSM8226 based devices. This should allow most
multimedia device drivers to probe and control their clocks.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220207185411.19118-3-bartosz.dudziak@snejp.pl
The "xo" fixed_factor clock is a leftover/hack from a time when we
couldn't make rpmhcc the root of all clocks. It is going to be removed
once all users of this clock are converted to use clocks specified
through the DTS. Replace internal usage of the xo clock with the cxo
(RPM_SMD_BB_CLK1) parent, specifying xo_board as a fallback.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-17-dmitry.baryshkov@linaro.org
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-16-dmitry.baryshkov@linaro.org
Move clock parent tables down, after the GPLL declrataions, so that we
can use gpll hw clock fields in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-15-dmitry.baryshkov@linaro.org
In preparation of updating the msm8996 gcc driver, drop all unsupported
GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
Downstream kernel also does not provide support for these GPLL sources,
so it is safe to drop them.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-14-dmitry.baryshkov@linaro.org
If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-12-dmitry.baryshkov@linaro.org
Convert the clock driver to specify parent hws/data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-11-dmitry.baryshkov@linaro.org
Move clock parent tables down, after the PLL declrataions, so that we
can use pll hw clock fields in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-10-dmitry.baryshkov@linaro.org
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-9-dmitry.baryshkov@linaro.org
If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-7-dmitry.baryshkov@linaro.org
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-6-dmitry.baryshkov@linaro.org
If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-4-dmitry.baryshkov@linaro.org
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-3-dmitry.baryshkov@linaro.org
Two clocks are still using parent_names, use parent_hws instead.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-2-dmitry.baryshkov@linaro.org
they're mostly minor cleanups and some debugfs stuff. The real work
that's in here is the typical pile of clk driver updates and new SoC
support. Per usual (or maybe just recent trends), Qualcomm gains a
handful of SoC drivers additions and has the largest diffstat. After
that there are quite a few updates to the Allwinner (sunxi) drivers to
support modular drivers and Renesas is heavily updated to add more
support for various clks. Overall it looks pretty normal.
New Drivers:
- Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
- MediaTek mt7986 SoC basic support
- Clock and reset driver for Toshiba Visconti SoCs
- Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
- Allwinner D1 clks
- Lan966x Generic Clock Controller driver and associated DT bindings
- Qualcomm SDX65, SM8450, and MSM8976 GCC clks
- Qualcomm SDX65 and SM8450 RPMh clks
Updates:
- Set suppress_bind_attrs to true for i.MX8ULP driver
- Switch from do_div to div64_ul for throughout all i.MX drivers
- Fix imx8mn_clko1_sels for i.MX8MN
- Remove unused IPG_AUDIO_ROOT from i.MX8MP
- Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
- Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung
- Refactoring of the CPU clocks registration to use common interface
- An update of the Exynos850 driver (support for more clock domains)
required by the E850-96 development board
- Prep for runtime PM and generic power domains on Tegra
- Support modular Allwinner clk drivers via platform bus
- Lan966x clock driver extended to support clock gating
- Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
thermal (TSU) clocks and resets on Renesas RZ/G2L
- Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock
drivers, and in the Renesas SDHI driver
- Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
- Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add GPU clock and resets on Renesas RZ/G2L
- Add clk-provider.h to various Qualcomm clk drivers
- devm version of clk_hw_register_gate()
- kerneldoc fixes in a couple drivers
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have a couple patches in the framework core this time around but
they're mostly minor cleanups and some debugfs stuff. The real work
that's in here is the typical pile of clk driver updates and new SoC
support.
Per usual (or maybe just recent trends), Qualcomm gains a handful of
SoC drivers additions and has the largest diffstat. After that there
are quite a few updates to the Allwinner (sunxi) drivers to support
modular drivers and Renesas is heavily updated to add more support for
various clks.
Overall it looks pretty normal.
New Drivers:
- Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
- MediaTek mt7986 SoC basic support
- Clock and reset driver for Toshiba Visconti SoCs
- Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
- Allwinner D1 clks
- Lan966x Generic Clock Controller driver and associated DT bindings
- Qualcomm SDX65, SM8450, and MSM8976 GCC clks
- Qualcomm SDX65 and SM8450 RPMh clks
Updates:
- Set suppress_bind_attrs to true for i.MX8ULP driver
- Switch from do_div to div64_ul for throughout all i.MX drivers
- Fix imx8mn_clko1_sels for i.MX8MN
- Remove unused IPG_AUDIO_ROOT from i.MX8MP
- Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
- Removal of all remaining uses of __clk_lookup() in
drivers/clk/samsung
- Refactoring of the CPU clocks registration to use common interface
- An update of the Exynos850 driver (support for more clock domains)
required by the E850-96 development board
- Prep for runtime PM and generic power domains on Tegra
- Support modular Allwinner clk drivers via platform bus
- Lan966x clock driver extended to support clock gating
- Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
thermal (TSU) clocks and resets on Renesas RZ/G2L
- Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2
clock drivers, and in the Renesas SDHI driver
- Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
- Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add GPU clock and resets on Renesas RZ/G2L
- Add clk-provider.h to various Qualcomm clk drivers
- devm version of clk_hw_register_gate()
- kerneldoc fixes in a couple drivers"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits)
clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()
clk: mediatek: add mt7986 clock support
clk: mediatek: add mt7986 clock IDs
dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC
clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers
clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper
clk: x86: Fix clk_gate_flags for RV_CLK_GATE
clk: x86: Use dynamic con_id string during clk registration
ACPI: APD: Add a fmw property clk-name
drivers: acpi: acpi_apd: Remove unused device property "is-rv"
x86: clk: clk-fch: Add support for newer family of AMD's SOC
clk: ingenic: Add MDMA and BDMA clocks
dt-bindings: clk/ingenic: Add MDMA and BDMA clocks
clk: bm1880: remove kfrees on static allocations
clk: Drop unused COMMON_CLK_STM32MP157_SCMI config
clk: st: clkgen-mux: search reg within node or parent
clk: st: clkgen-fsyn: search reg within node or parent
clk: Enable/Disable runtime PM for clk_summary
MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller
clk: visconti: Add support common clock driver and reset driver
...
This introduces bindings and drivers for the global clock controllers
found in SDX65, SM8450 and MSM8976, as well as RPMh clock support for
SDX65 and SM8450.
It cleans up the SMD RPM clock driver and it adds includes for
clk-provider.h throughout the clock providers that was lacking this.
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Merge tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull qcom clk driver updates from Bjorn Andersson:
This introduces bindings and drivers for the global clock controllers
found in SDX65, SM8450 and MSM8976, as well as RPMh clock support for
SDX65 and SM8450.
It cleans up the SMD RPM clock driver and it adds includes for
clk-provider.h throughout the clock providers that was lacking this.
* tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits)
clk: qcom: turingcc-qcs404: explicitly include clk-provider.h
clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h
clk: qcom: mmcc-apq8084: explicitly include clk-provider.h
clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h
clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h
clk: qcom: gcc-sm6350: explicitly include clk-provider.h
clk: qcom: gcc-msm8994: explicitly include clk-provider.h
clk: qcom: gcc-sm8350: explicitly include clk-provider.h
clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver
dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller
clk: qcom: Add clock driver for SM8450
clk: qcom: Add SDX65 GCC support
clk: qcom: Add LUCID_EVO PLL type for SDX65
dt-bindings: clock: Add SM8450 GCC clock bindings
dt-bindings: clock: Add SDX65 GCC clock bindings
clk: qcom: rpmh: add support for SM8450 rpmh clocks
dt-bindings: clock: Add RPMHCC bindings for SM8450
clk: qcom: smd-rpm: Drop binary value handling for buffered clock
clk: qcom: smd-rpm: Drop the use of struct rpm_cc
clk: qcom: smd-rpm: Drop MFD qcom-rpm reference
...
The gcc cfg noc lpass clock is required to be always enabled for the
LPASS core and audio drivers to be functional.
Fixes: a3cc092196 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1640018638-19436-4-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
PLL poll for lock detection can take more than 100us for certain type
of Lucid PLLs and also the new PLLs types(Lucid EVO), thus update to 200us.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1640018638-19436-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215113803.620032-9-vkoul@kernel.org
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215113803.620032-8-vkoul@kernel.org
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215113803.620032-7-vkoul@kernel.org
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215113803.620032-6-vkoul@kernel.org
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215113803.620032-5-vkoul@kernel.org
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215113803.620032-4-vkoul@kernel.org
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215113803.620032-3-vkoul@kernel.org
Per Stephen, clk providers need to include clk-provider.h, so include in
this driver as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215113803.620032-2-vkoul@kernel.org
Add support for the global clock controller found on MSM8956
and MSM8976 SoCs.
Since the multimedia clocks are actually in the GCC on these
SoCs, this will allow drivers to probe and control basically
all the required clocks.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211208091036.132334-3-marijn.suijten@somainline.org
This adds Global Clock controller (GCC) driver for SM8450 SoC including
the gcc resets and gdsc.
This patch is based on initial code downstream by Vivek Aknurwar
<viveka@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211207114003.100693-3-vkoul@kernel.org
Without this change eMMC runs at overclocked freq.
Swap the ops to not OC the eMMC.
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Link: https://lore.kernel.org/r/20211130212015.25232-1-martin.botka@somainline.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 4b8d6ae57c ("clk: qcom: Add SM6125 (TRINKET) GCC driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The buffered clock binary value handling added by commit 36354c32bd
("clk: qcom: smd-rpm: Add .recalc_rate hook for clk_smd_rpm_branch_ops")
is redundant, because buffered clock is branch type, and the binary
value handling for branch clock has been handled by
clk_smd_rpm_prepare/unprepare functions.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211031020715.21636-4-shawn.guo@linaro.org
Considering that struct rpm_cc is now identical to rpm_smd_clk_desc,
and function qcom_smdrpm_clk_hw_get() uses rpm_cc in a read-only manner,
rpm_cc can be dropped by getting the function use rpm_smd_clk_desc
directly.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211031020715.21636-3-shawn.guo@linaro.org
The MFD qcom-rpm interface is not used by this driver. Drop the 'struct
qcom_rpm' reference and include of <dt-bindings/mfd/qcom-rpm.h>.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211031020715.21636-2-shawn.guo@linaro.org
In the event that the bootloader has configured the Trion PLL as source
for the display clocks, e.g. for the continuous splashscreen, then there
will also be RCGs that are clocked by this instance.
Reconfiguring, and in particular disabling the output of, the PLL will
cause issues for these downstream RCGs and has been shown to prevent
them from being re-parented.
Follow downstream and skip configuration if it's determined that the PLL
is already running.
Fixes: 59128c20a6 ("clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20211123162508.153711-1-bjorn.andersson@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The function mux_get_parent() uses qcom_find_src_index() to find the
parent clock index, which is incorrect: qcom_find_src_index() uses src
enum for the lookup, while mux_get_parent() should use cfg field (which
corresponds to the register value). Add qcom_find_cfg_index() function
doing this kind of lookup and use it for mux parent lookup.
Fixes: df96401649 ("clk: qcom: add parent map for regmap mux")
Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20211115233407.1046179-1-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
a little more time to soak in linux-next.
- Use modern i2c probe in vc5
- Cleanup some includes
- Update links to datasheets
- Add UniPhier NX1 SoC clk support
- Fix DT bindings for SiFive FU740
- Revert the module platform driver support for Rockchip out
because it wasn't actually tested
- Fix the composite clk code again as the previous fix had a
one line bug that broke rate changes for clks that want to use
the same parent still
- Use the right table for a divider in ast2600 driver
- Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because
its critical but unused
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull more clk updates from Stephen Boyd:
"This is the second batch of clk driver updates that needed a little
more time to soak in linux-next.
- Use modern i2c probe in vc5
- Cleanup some includes
- Update links to datasheets
- Add UniPhier NX1 SoC clk support
- Fix DT bindings for SiFive FU740
- Revert the module platform driver support for Rockchip because it
wasn't actually tested
- Fix the composite clk code again as the previous fix had a one line
bug that broke rate changes for clks that want to use the same
parent still
- Use the right table for a divider in ast2600 driver
- Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because
its critical but unused"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk
clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites
clk/ast2600: Fix soc revision for AHB
clk: composite: Fix 'switching' to same clock
clk: rockchip: drop module parts from rk3399 and rk3568 drivers
Revert "clk: rockchip: use module_platform_driver_probe"
clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c
dt-bindings: clock: fu740-prci: add reset-cells
clk: uniphier: Add SoC-glue clock source selector support for Pro4
dt-bindings: clock: uniphier: Add clock binding for SoC-glue
clk: uniphier: Add NX1 clock support
dt-bindings: clock: uniphier: Add NX1 clock binding
clk: uniphier: Add audio system and video input clock control for PXs3
clk: si5351: Update datasheet references
clk: vc5: Use i2c .probe_new
clk/actions/owl-factor.c: remove superfluous headers
clk: ingenic: Fix bugs with divided dividers
The gcc_aggre1_pnoc_ahb_clk is crucial for the proper MSM8996/APQ8096
functioning. If it gets disabled, several subsytems will stop working
(including eMMC/SDCC and USB). There are no in-kernel users of this
clock, so it is much simpler to remove from the kernel.
The clock was first removed in the commit 9e60de1cf2 ("clk: qcom:
Remove gcc_aggre1_pnoc_ahb_clk from msm8996") by Stephen Boyd, but got
added back in the commit b567752144 ("clk: qcom: Add some missing gcc
clks for msm8996") by Rajendra Nayak.
Let's remove it again in hope that nobody adds it back.
Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Fixes: b567752144 ("clk: qcom: Add some missing gcc clks for msm8996")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20211104011155.2209654-1-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
terms of lines it's mainly Qualcomm and Mediatek code, supporting
various SoCs and their multitude of clk controllers.
New Drivers:
- GCC and RPMcc support for Qualcomm QCM2290 SoCs
- GCC support for Qualcomm MSM8994/MSM8992 SoCs
- LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
- Support for Mediatek MT8195 SoCs
- Initial clock driver for the Exynos850 SoC
- Add i.MX8ULP clock driver and related bindings
Updates:
- Clock power management for new SAMA7G5 SoC
- Updates to the master clock driver and sam9x60-pll to be able to use
cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while
changing the frequency via DVFS
- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- Make Mediatek clk drivers tristate
- Refactoring of the CPU clock code and conversion of Samsung Exynos5433
CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Samsung Kconfig help text
- Update video path realted clocks for Amlogic meson8
- Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
- Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Remove unused helpers from i.MX specific clock header
- Rework all i.MX clk based helpers to use clk_hw based ones
- Rework i.MX gate/mux/divider wrappers
- Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
- Update i.MX pllv4 and composite clocks to support i.MX8ULP
- Disable i.MX7ULP composite clock during initialization
- Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
- Disable the i.MX pfd when set pfdv2 clock rate
- Add support for i.MX8ULP in pfdv2
- Add the pcc reset controller support on i.MX8ULP
- Fix the build break when clk-imx8ulp is built as module
- Move csi_sel mux to correct base register in i.MX6UL clock drivr
- Fix csi clk gate register in i.MX6UL clock driver
- Fix build bug making CLK_IMX8ULP select MXC_CLK
- Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
- Add Ethernet clocks on Renesas RZ/G2L
- Move Rockchip to use module_platform_probe
- Enable usage of Coresight related clocks on Rockchip rk3399
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The usual collection of clk driver updates and new driver additions.
In terms of lines it's mainly Qualcomm and Mediatek code, supporting
various SoCs and their multitude of clk controllers.
New Drivers:
- GCC and RPMcc support for Qualcomm QCM2290 SoCs
- GCC support for Qualcomm MSM8994/MSM8992 SoCs
- LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
- Support for Mediatek MT8195 SoCs
- Initial clock driver for the Exynos850 SoC
- Add i.MX8ULP clock driver and related bindings
Updates:
- Clock power management for new SAMA7G5 SoC
- Updates to the master clock driver and sam9x60-pll to be able to
use cpufreq-dt driver and avoid overclocking of CPU and MCK0
domains while changing the frequency via DVFS
- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- Make Mediatek clk drivers tristate
- Refactoring of the CPU clock code and conversion of Samsung
Exynos5433 CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Samsung Kconfig help text
- Update video path realted clocks for Amlogic meson8
- Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
- Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Remove unused helpers from i.MX specific clock header
- Rework all i.MX clk based helpers to use clk_hw based ones
- Rework i.MX gate/mux/divider wrappers
- Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
- Update i.MX pllv4 and composite clocks to support i.MX8ULP
- Disable i.MX7ULP composite clock during initialization
- Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
- Disable the i.MX pfd when set pfdv2 clock rate
- Add support for i.MX8ULP in pfdv2
- Add the pcc reset controller support on i.MX8ULP
- Fix the build break when clk-imx8ulp is built as module
- Move csi_sel mux to correct base register in i.MX6UL clock drivr
- Fix csi clk gate register in i.MX6UL clock driver
- Fix build bug making CLK_IMX8ULP select MXC_CLK
- Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
- Add Ethernet clocks on Renesas RZ/G2L
- Move Rockchip to use module_platform_probe
- Enable usage of Coresight related clocks on Rockchip rk3399"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits)
clk: use clk_core_get_rate_recalc() in clk_rate_get()
clk: at91: sama7g5: set low limit for mck0 at 32KHz
clk: at91: sama7g5: remove prescaler part of master clock
clk: at91: clk-master: add notifier for divider
clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
clk: at91: clk-master: fix prescaler logic
clk: at91: clk-master: mask mckr against layout->mask
clk: at91: clk-master: check if div or pres is zero
clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
clk: at91: pmc: add sama7g5 to the list of available pmcs
clk: at91: clk-master: improve readability by using local variables
clk: at91: clk-master: add register definition for sama7g5's master clock
clk: at91: sama7g5: add securam's peripheral clock
clk: at91: pmc: execute suspend/resume only for backup mode
clk: at91: re-factor clocks suspend/resume
clk: ux500: Add driver for the reset portions of PRCC
dt-bindings: clock: u8500: Rewrite in YAML and extend
clk: composite: Use rate_ops.determine_rate when also a mux is available
clk: samsung: describe drivers in Kconfig
clk: samsung: exynos5433: update apollo and atlas clock probing
...
On sm8250 dispcc and videocc registers are powered up by the MMCX power
domain. Currently we use a regulator to enable this domain on demand,
however this has some consequences, as genpd code is not reentrant.
Make gdsc code also use pm_runtime calls to ensure that registers are
accessible during the gdsc_enable/gdsc_disable operations.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210829154757.784699-6-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
On sm8250 dispcc and videocc registers are powered up by the MMCX power
domain. Use runtime PM calls to make sure that required power domain is
powered on while we access clock controller's registers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210829154757.784699-5-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
On sm8250 dispcc and videocc registers are powered up by the MMCX power
domain. Use runtime PM calls to make sure that required power domain is
powered on while we access clock controller's registers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210829154757.784699-4-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
After commit 3165d1e3c7 ("clk: qcom: gcc: Remove CPUSS clocks control
for SC7280") this array is unused. Remove it.
Reported-by: kernel test robot <lkp@intel.com>
Cc: Taniya Das <tdas@codeaurora.org>
Fixes: 3165d1e3c7 ("clk: qcom: gcc: Remove CPUSS clocks control for SC7280")
Link: https://lore.kernel.org/r/20211014191259.1689641-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the camera clock controller found on SC7280 based
devices.
This would allow camera drivers to probe and control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1633567425-11953-2-git-send-email-tdas@codeaurora.org
[sboyd@kernel.org: Make some VCOs unsigned long]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the lpass clock controller found on SC7280 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1633484416-27852-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Don't rely on the programmer to enter the name of array elements, since the
computer can compute it with much less chance of making a mistake.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210923162645.23257-9-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This should be the last "add missing clocks" commit, as to
my knowledge there are no more clocks registered within gcc.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210923162645.23257-5-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for RPM-managed clocks on the QCM2290 platform.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210917030434.19859-4-shawn.guo@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As there is a `rate` field in clk_smd_rpm, clk_smd_rpm_recalc_rate() can
be used by branch clocks to report rate as well, rather than assuming
the rate is always same as parent clock. This assumption doesn't hold
on platforms like QCM2290, where xo_board is 38.4MHz while bi_tcxo is
19.2MHz.
To get this work, XO buffered clocks need the following updates.
- Assign a correct rate rather than the fake one which is being used to
generate binary value for clk_smd_rpm_req interface.
- Explicitly handle the clk_smd_rpm_req interface value for XO buffered
clocks (.rpm_res_type being QCOM_SMD_RPM_CLK_BUF_A).
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210917030434.19859-2-shawn.guo@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sboyd@kernel.org: Do cpu_to_le32() again to keep sparse happy]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add Global Clock Controller (GCC) driver for QCM2290. This is a porting
of gcc-scuba driver from CAF msm-4.19, with GDSC support added on top.
Because the alpha_pll on the platform has a different register
layout (offsets), its own clk_alpha_pll_regs_offset[] is used in the
driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210919023308.24498-3-shawn.guo@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Drop duplicate includes, clk.h include, module alias]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It looks that the offset 0x7d060 is a copy & paste from above
hlos1_vote_turing_mmu_tbu1_gdsc. Correct it to 0x7d07c as per
downstream kernel.
Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210919022308.24046-1-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The CPUSS clocks are kept always ON and at a fixed frequency of 100MHZ
from the bootloader and no longer required to be controlled from HLOS.
Fixes: a3cc092196 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1633579571-25475-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: Kai Song <songkai01@inspur.com>
Link: https://lore.kernel.org/r/20211006043627.5125-1-songkai01@inspur.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
A previous patch removes the "xo" clock from the global namespace making
it impossible to acquire by that ".name". The device-tree for msm8998
already provides the "xo" and "gpll0" clock since the addition of the
gpucc node making it unnecessary to have this fallback at all.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-8-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-6-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-5-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Now that all clock controllers and the DSI PLL clocks rely on "xo" being
passed in DT as phandle instead of looking it up by the global "xo" name
this transient clock can be removed, leaving only the fixed-factor
"xo_board" clock in DT.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-4-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use parent_data and parent_hws to specify internal relations using
pointers instead of names, and use .fw_name to retrieve external clocks
from clock-names in the DT rather than the global clock tree.
Note that this change relies on the "xo" and "sleep_clk" clocks to be
provided in DT, as per the relevant qcom,gcc-mnsm8998.yaml dt-bindings.
These clocks have been added in a prior patch [1].
[1]: https://lore.kernel.org/linux-arm-msm/20210911120101.248476-1-marijn.suijten@somainline.org/
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-3-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Prepare for a future patch where we use .hw pointers to these GPLL
clocks in the parent mapping instead of name references. This requires
the GPLL clocks to be decared before parent_data arrays.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-2-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Link: https://lore.kernel.org/r/20210907084858.4101-1-caihuoqing@baidu.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Link: https://lore.kernel.org/r/20210907084851.4050-1-caihuoqing@baidu.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Link: https://lore.kernel.org/r/20210907084843.3999-1-caihuoqing@baidu.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The necessary clocks for this driver are already fully specified in
sdm630 DT under the .fw_name, and do not need an implicit fallback to
their global name.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829204822.289829-5-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data instead of hardcoding a number that relies on an array
defined hundreds of lines above.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829204822.289829-2-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In the commit "clk: qcom: Add SM6350 GCC driver" (no hash yet) an unused
variable has been overlooked. Remove it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/5b7edab0-4756-94d0-d601-050120cbf4cb@somainline.org
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
some updates to the basic clk types to use determine_rate for the
divider type and add a power of two fractional divider flag though.
Otherwise, this is a collection of clk driver updates. More than half
the diffstat is in the Qualcomm clk driver where we add a bunch of data
to describe clks on various SoCs and fix bugs. The other big new thing
in here is the Mediatek MT8192 clk driver. That's been under review for
a while and it's nice to see that it's finally upstream.
Beyond that it's the usual set of minor fixes and tweaks to clk drivers.
There are some non-clk driver bits in here which have all been acked by
the respective maintainers.
New Drivers:
- Support video, gpu, display clks on qcom sc7280 SoCs
- GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
- Multimedia clks (MMCC) on qcom MSM8994/MSM8992
- RPMh clks on qcom SM6350 SoCs
- Support for Mediatek MT8192 SoCs
- Add display (DU and DSI) clocks on Renesas R-Car V3U
- Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
resets on Renesas RZ/G2L
Updates:
- Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
- Add power of two flag to fractional divider clk type
- Migrate some clk drivers to clk_divider_ops.determine_rate
- Migrate to clk_parent_data in gcc-sdm660
- Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
- Switch from .round_rate to .determine_rate in clk-divider-gate
- Fix clock tree update for TF-A controlled clocks for all i.MX8M
- Add missing M7 core clock for i.MX8MN
- YAML conversion of rk3399 clock controller binding
- Removal of GRF dependency for the rk3328/rk3036 pll types
- Drop CLK_IS_CRITICAL flag from Tegra fuse clk
- Make CLK_R9A06G032 Kconfig symbol invisible
- Convert various DT bindings to YAML
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Nothing changed in the clk framework core this time around. We did get
some updates to the basic clk types to use determine_rate for the
divider type and add a power of two fractional divider flag though.
Otherwise, this is a collection of clk driver updates. More than half
the diffstat is in the Qualcomm clk driver where we add a bunch of
data to describe clks on various SoCs and fix bugs. The other big new
thing in here is the Mediatek MT8192 clk driver. That's been under
review for a while and it's nice to see that it's finally upstream.
Beyond that it's the usual set of minor fixes and tweaks to clk
drivers. There are some non-clk driver bits in here which have all
been acked by the respective maintainers.
New Drivers:
- Support video, gpu, display clks on qcom sc7280 SoCs
- GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
- Multimedia clks (MMCC) on qcom MSM8994/MSM8992
- RPMh clks on qcom SM6350 SoCs
- Support for Mediatek MT8192 SoCs
- Add display (DU and DSI) clocks on Renesas R-Car V3U
- Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
resets on Renesas RZ/G2L
Updates:
- Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
- Add power of two flag to fractional divider clk type
- Migrate some clk drivers to clk_divider_ops.determine_rate
- Migrate to clk_parent_data in gcc-sdm660
- Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
- Switch from .round_rate to .determine_rate in clk-divider-gate
- Fix clock tree update for TF-A controlled clocks for all i.MX8M
- Add missing M7 core clock for i.MX8MN
- YAML conversion of rk3399 clock controller binding
- Removal of GRF dependency for the rk3328/rk3036 pll types
- Drop CLK_IS_CRITICAL flag from Tegra fuse clk
- Make CLK_R9A06G032 Kconfig symbol invisible
- Convert various DT bindings to YAML"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits)
dt-bindings: clock: samsung: fix header path in example
clk: tegra: fix old-style declaration
clk: qcom: Add SM6350 GCC driver
MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
dt-bindings: clock: samsung: convert Exynos4 to dtschema
dt-bindings: clock: samsung: convert Exynos3250 to dtschema
dt-bindings: clock: samsung: convert Exynos542x to dtschema
dt-bindings: clock: samsung: add bindings for Exynos external clock
dt-bindings: clock: samsung: convert Exynos5250 to dtschema
clk: vc5: Add properties for configuring SD/OE behavior
clk: vc5: Use dev_err_probe
dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
clk: zynqmp: Fix kernel-doc format
clk: at91: clk-generated: Limit the requested rate to our range
clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
clk: zynqmp: Fix a memory leak
clk: zynqmp: Check the return type
...
This adds Global Clock controller (GCC) driver for SM6350 SoC
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210820203624.232268-3-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for RPMH clocks on SM6350 SoCs.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210820203243.230157-3-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Commit 5658e8cf1a ("clk: qcom: add video clock controller driver for
SM8150") and commit 0e94711a1f ("clk: qcom: add video clock controller
driver for SM8250") add config SM_VIDEOCC_8150 and config SM_VIDEOCC_8250,
which select the non-existing configs SDM_GCC_8150 and SDM_GCC_8250,
respectively.
Hence, ./scripts/checkkconfigsymbols.py warns:
SDM_GCC_8150
Referencing files: drivers/clk/qcom/Kconfig
SDM_GCC_8250
Referencing files: drivers/clk/qcom/Kconfig
It is probably just a typo (or naming confusion of using SM_GCC_xxx and
SDM_GCC_xxx for various Qualcomm clock drivers) in the config definitions
for config SM_VIDEOCC_8150 and SM_VIDEOCC_8250, and intends to select the
existing SM_GCC_8150 and SM_GCC_8250, respectively.
Adjust the selects to the existing configs.
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20210816135930.11810-1-lukas.bulwahn@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the global clock controller found on SM6115
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation. GDSCs ported from downstream DT.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210805161107.1194521-3-iskren.chernev@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add a driver for managing MultiMedia SubSystem clocks on msm8994
and its derivatives.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210618111435.595689-2-konrad.dybcio@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This driver provides clocks, resets and power domains for MSM8953
and compatible SoCs: APQ8053, SDM450, SDA450, SDM632, SDA632.
Signed-off-by: Vladimir Lypak <junak.pub@gmail.com>
Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com>
Link: https://lore.kernel.org/r/IPvVnyRWbHuQFswiFz0W08Kj1dKoH55ddQVyIIPhMJw@cp7-web-043.plabs.ch
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Using parent_data and parent_hws, instead of parent_names, does protect
against some cases of incompletely defined clock trees. While it turns
out that the bug being chased this time was totally unrelated, this
patch converts the SDM660 GCC driver to avoid such issues.
The "xo" fixed_factor clock is unused within the gcc driver, but
referenced from the DSI PHY. So it's left in place until the DSI driver
is updated.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210825204517.1278130-1-bjorn.andersson@linaro.org
[sboyd@kernel.org: Reduce diff by moving enum and tables back to
original position in previous patch]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In the next patch we're going to change these tables to reference the
PLL structures directly. Let's move them here so the diff is easier to
read. No functional change in this patch.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use two new helpers instead of pm_runtime_enable() and pm_clk_create(),
removing the need for calling pm_runtime_disable and pm_clk_destroy().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210731195034.979084-4-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
MSM8939 has 3 a53pll clocks with different frequency table for Cluster0,
Cluster1 and CCI. It adds function qcom_a53pll_get_freq_tbl() to create
pll_freq_tbl from OPP, so that those a53pll frequencies can be defined
in DT with operating-points-v2 bindings rather than being coded in the
driver. In this case, one compatible rather than three would be needed
for these 3 a53pll clocks.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-5-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Different from MSM8916 which has only one a53pll/mux clock, MSM8939 gets
three for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache
Coherent Interconnect). That said, a53pll/mux clock needs to be named
uniquely. Append @unit-address of device node to the clock name, so
that a53pll/mux will be named like below on MSM8939.
a53pll@b016000
a53pll@b116000
a53pll@b1d0000
a53mux@b1d1000
a53mux@b011000
a53mux@b111000
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-3-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The clock source for MSM8916 cpu cores is like below.
|\
a53pll --------| \ a53mux +------+
| |------------| cpus |
gpll0_vote --------| / +------+
|/
So a53mux rather than a53pll is actually the parent clock of cpu cores.
It makes more sense to flag a53mux as critical instead, so that when
either a53pll or gpll0_vote is used by cpu cores, the clock will be kept
enabled while the other can be disabled.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-2-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The GPU clock controller found in SC8180x is a variant of the same block
found in SM8150, but with one additional clock frequency for the
gmu_clk_src clock.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210721225329.3035779-1-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add definitions for RPM clocks used on MSM8953 platform.
Signed-off-by: Vladimir Lypak <junak.pub@gmail.com>
Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com>
Link: https://lore.kernel.org/r/QZ0fkozlubDdc7CvqjZPhAviFmjJ28ht7Y4PT3rYM@cp4-web-038.plabs.ch
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add rpm smd clocks, PMIC and bus clocks which are required on
SM4250/6115 for clients to vote on.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210731164827.2756798-2-iskren.chernev@gmail.com
[sboyd@kernel.org: Drop duplicate define, merge with sm6125 support]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As GDSCs are registered and found to be already enabled gdsc_init()
ensures that 1) the kernel state matches the hardware state, and 2)
votable GDSCs are properly enabled from this master as well.
But as the (optional) supply regulator is enabled deep into
gdsc_toggle_logic(), which is only executed for votable GDSCs, the
kernel's state of the regulator might not match the hardware. The
regulator might be automatically turned off if no other users are
present or the next call to gdsc_disable() would cause an unbalanced
regulator_disable().
Given that the votable case deals with an already enabled GDSC, most of
gdsc_enable() and gdsc_toggle_logic() can be skipped. Reduce it to just
clearing the SW_COLLAPSE_MASK and enabling hardware control to simply
call regulator_enable() in both cases.
The enablement of hardware control seems to be an independent property
from the GDSC being enabled, so this is moved outside that conditional
segment.
Lastly, as the propagation of ALWAYS_ON to GENPD_FLAG_ALWAYS_ON needs to
happen regardless of the initial state this is grouped together with the
other sc->pd updates at the end of the function.
Cc: stable@vger.kernel.org
Fixes: 37416e5549 ("clk: qcom: gdsc: Handle GDSC regulator supplies")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210721224056.3035016-1-bjorn.andersson@linaro.org
[sboyd@kernel.org: Rephrase commit text]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The clock controller has two additional clock source pairs, in order to
support more than a single DisplayPort PHY. List these, so it's possible
to describe them all.
Also drop the unnecessary freq_tbl for the link clock sources, to allow
these parents to be used.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210721224610.3035258-1-bjorn.andersson@linaro.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the video clock controller found on SC7280
based devices. This would allow video drivers to probe and
control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-8-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the graphics clock controller found on SC7280
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-6-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the display clock controller found on SC7280
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-4-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Caught this when looking at alpha-pll code. Untested but it is clear that
this was intended to write to PLL_CAL_L_VAL and not PLL_ALPHA_VAL.
Fixes: 691865bad6 ("clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210609022852.4151-1-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the camera clock controller found on SM8250.
Based on the downstream driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20210609022051.2171-4-jonathan@marek.ca
[sboyd@kernel.org: Add UL to avoid decimal problems]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Fix gcc '-Wunused-const-variable' warnings:
drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: 'gcc_xo_gpll0_gpll1'
defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: 'gcc_xo_gpll0_gpll1_map'
defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: 'gcc_xo_sleep' defined
but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: 'gcc_xo_sleep_map'
defined but not used [-Wunused-const-variable=]
Let's remove them.
Signed-off-by: Pu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/r/20210609061848.87415-1-pulehui@huawei.com
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add compatible for rpm smd clocks, PMIC and bus clocks which are required
on MSM8226 for clients to vote on.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20210605104040.12960-1-bartosz.dudziak@snejp.pl
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies
which are different in this older chip. Register all the clocks to the
framework for the clients to be able to request for them.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20210418122909.71434-3-bartosz.dudziak@snejp.pl
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the clocks supported in global clock controller, which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Link: https://lore.kernel.org/r/20210605121040.282053-2-martin.botka@somainline.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sboyd@kernel.org: Mark gcc_sm6125_hws array static]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
There is a requirement to support 52MHz for qup clocks for bluetooth
usecase, thus update the frequency table to support the frequency.
Fixes: a3cc092196 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1624449471-9984-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
During my big cleanup I managed to assign an AO clock to its
non-AO binding. Fix this.
Reported-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210606192657.51037-1-konrad.dybcio@somainline.org
Fixes: a0384ecfe2 ("clk: qcom: smd-rpm: De-duplicate identical entries")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The display clock controller in SC8180x is reused from SM8150, so add
the necessary compatible and wire up the driver to enable this.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210511041719.591969-1-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It makes negative sense to keep repeating the same definitions
over and over and over and over again, just with changed names..
De-duplicate to make for a drastically smaller file size. This makes the
object file size 55% smaller according to bloat-o-meter:
Total: Before=70713, After=31353, chg -55.66%
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210524225456.398817-2-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to parent_data and with that fix the longstanding issue where
if there wasn't a clock precisely named "xo_board", rpmcc would not play
along well. This started to show lately when "xo_board" was being changed to
"xo-board" so as to align with DTS naming spec.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210524225456.398817-1-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The dev_err_probe() function prints an error message if the error
code is not -EPROBE_DEFER. If we know the error code in is -ENODEV
then there is no reason to check.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/YJotlJBJ1CVAgvMT@mwanda
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dev_err_probe() returns the error code passed as second parameter. Also if
the error code is -EPROBE_DEFER dev_err_probe() is silent, so there is no
need to check for this value before calling dev_err_probe().
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Link: https://lore.kernel.org/r/20210427164522.2886825-1-uwe@kleine-koenig.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all the boundary conditions and enable setting the desired duty-cycle
as per the consumer.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1619334502-9880-2-git-send-email-tdas@codeaurora.org
[sboyd@kernel.org: Remove _val everywhere]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The IPA core clock is required for SDX55. Define it.
Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20210409134407.841137-1-elder@linaro.org
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210409183004.1617777-4-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210409183004.1617777-3-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
CONFIG_IPQ_APSS_PLL is tristate option and therefore this driver can
be compiled as a module. This patch adds missing MODULE_DEVICE_TABLE
definition which generates correct modalias for automatic loading of
this driver when it is built as an external module.
Fixes: ecd2bacfbb ("clk: qcom: Add ipq apss pll driver")
Signed-off-by: Chen Hui <clare.chenhui@huawei.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210409082352.233810-4-clare.chenhui@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
CONFIG_QCOM_A53PLL is tristate option and therefore this driver can be
compiled as a module. This patch adds missing MODULE_DEVICE_TABLE
definition which generates correct modalias for automatic loading of
this driver when it is built as an external module.
Fixes: 0c6ab1b8f8 ("clk: qcom: Add A53 PLL support")
Signed-off-by: Chen Hui <clare.chenhui@huawei.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210409082352.233810-3-clare.chenhui@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
CONFIG_QCOM_A7PLL is tristate option and therefore this driver can be
compiled as a module. This patch adds missing MODULE_DEVICE_TABLE
definition which generates correct modalias for automatic loading of
this driver when it is built as an external module.
Fixes: 5a5223ffd7 ("clk: qcom: Add A7 PLL support")
Signed-off-by: Chen Hui <clare.chenhui@huawei.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210409082352.233810-2-clare.chenhui@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-34-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-33-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-32-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-31-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-30-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-29-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-28-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-27-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-26-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-25-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-24-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-23-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-22-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-21-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-20-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-19-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-18-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-17-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-16-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-15-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-14-dmitry.baryshkov@linaro.org
[sboyd@kernel.org: Silence checkpatch block comments]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-13-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-12-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Some of the RCGs could be always ON from the XO source and could be used
as the clock on signal for the GDSC to be operational. In the cases where
the GDSCs are parked at different source with the source clock disabled,
it could lead to the GDSC to be stuck at ON/OFF during gdsc disable/enable.
Thus park the RCGs at XO during clock disable and update the rcg_ops to
use the shared_ops.
Fixes: 15d09e830b ("clk: qcom: camcc: Add camera clock controller driver for SC7180")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1616809265-11912-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
While picking commit a8cd989e1a ("mmc: sdhci-msm: Warn about
overclocking SD/MMC") back to my tree I was surprised that it was
reporting warnings. I thought I fixed those! Looking closer at the
fix, I see that I totally bungled it (or at least I halfway bungled
it). The SD card clock got fixed (and that was the one I was really
focused on fixing), but I totally adjusted the wrong clock for eMMC.
Sigh. Let's fix my dumb mistake.
Now both SD and eMMC have floor for the "apps" clock.
This doesn't matter a lot for the final clock rate for HS400 eMMC but
could matter if someone happens to put some slower eMMC on a sc7180.
We also transition through some of these lower rates sometimes and
having them wrong could cause problems during these transitions.
These were the messages I was seeing at boot:
mmc1: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz
mmc1: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz
mmc1: Card appears overclocked; req 104000000 Hz, actual 192000000 Hz
Fixes: 6d37a8d192 ("clk: qcom: gcc-sc7180: Use floor ops for sdcc clks")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210224095013.1.I2e2ba4978cfca06520dfb5d757768f9c42140f7c@changeid
Reviewed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In case the mux is not divided parent_req was mistakenly not assigned to
leading __clk_determine_rate to determine the best frequency setting for
a requested rate of 0, resulting in the msm8996 platform not booting.
Rectify this by refactoring the logic to unconditionally assign to
parent_req.rate with the clock rate the caller is expecting.
Fixes: 7cbb78a99d ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers")
Reported-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210302234106.3418665-1-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The bi_tcxo clock source for SC7280 requires a div 4 to derive 19.2MHz
from the xo_board. Thus update the same.
Fixes: fff2b9a651 ("clk: qcom: rpmh: Add support for RPMH clocks on SC7280")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1615400283-20100-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk drivers that dominate the diffstat because we add support for six SoCs from
that particular vendor. The other big change is the removal of various clk
drivers that are no longer used now that the kernel is dropping support for
those SoCs. Beyond that there's the usual non-critical fixes for existing
drivers and a good number of patches from Lee Jones that cleanup a bunch of W=1
enabled builds.
Removed Drivers:
- Remove efm32 clk driver
- Remove tango4 clk driver
- Remove zte zx clk driver
- Remove sirf prima2/atlast clk drivers
- Remove u300 clk driver
New Drivers:
- PLL support on MStar/SigmaStar ARMv7 SoCs
- CPU clks for Qualcomm SDX55
- GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
- GCC clks for Qualcomm SM8350
- GPU clks for Qualcomm SDM660/SDM630
Updates:
- Video clk fixups on Qualcomm SM8250
- Improvements for multimedia clks on Qualcomm MSM8998
- Fix many warnings with W=1 enabled builds under drivers/clk/
- Support crystal load capacitance for Versaclock VC5
- Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot
- Convert Xilinx VCU clk driver to a proper clk provider driver
- Expose Xilinx ZynqMP clk driver to more platforms
- Amlogic pll driver fixup
- Amlogic meson8b clock controller dt support clean up
- Remove mipi clk from the Amlogic axg clock controller
- New Rockchip rk3368 clock ids related to camera input
- Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk reparenting
- A series from Liu Ying that adds some SCU clocks support for i.MX8qxp
DC0/MIPI-LVDS subsystems
- A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ, and
clkout1/2 support for i.MX8MM/MN
- Add I2c and Ethernet (RAVB) clocks on Renesas R-Car V3U
- Add timer (TMU) clocks on most Renesas R-Car Gen3 SoCs
- Add video-related (FCPVD/VSPD/VSPX), watchdog (RWDT), serial
(HSCIF), pincontrol/GPIO (PFC/GPIO), SPI (MSIOF), SDHI, and DMA
(SYS-DMAC) clocks on Renesas R-Car V3U
- Add support for the USB 2.0 clock selector on Renesas RZ/G2 SoCs
- Allwinner H616 SoC clk support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This is all driver updates, the majority of which is a bunch of new
Qualcomm clk drivers that dominate the diffstat because we add support
for six SoCs from that particular vendor.
The other big change is the removal of various clk drivers that are no
longer used now that the kernel is dropping support for those SoCs.
Beyond that there's the usual non-critical fixes for existing drivers
and a good number of patches from Lee Jones that cleanup a bunch of
W=1 enabled builds.
Removed Drivers:
- Remove efm32 clk driver
- Remove tango4 clk driver
- Remove zte zx clk driver
- Remove sirf prima2/atlast clk drivers
- Remove u300 clk driver
New Drivers:
- PLL support on MStar/SigmaStar ARMv7 SoCs
- CPU clks for Qualcomm SDX55
- GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
- GCC clks for Qualcomm SM8350
- GPU clks for Qualcomm SDM660/SDM630
Updates:
- Video clk fixups on Qualcomm SM8250
- Improvements for multimedia clks on Qualcomm MSM8998
- Fix many warnings with W=1 enabled builds under drivers/clk/
- Support crystal load capacitance for Versaclock VC5
- Add a "skip recall" DT binding for Silicon Labs' si570 to avoid
glitches at boot
- Convert Xilinx VCU clk driver to a proper clk provider driver
- Expose Xilinx ZynqMP clk driver to more platforms
- Amlogic pll driver fixup
- Amlogic meson8b clock controller dt support clean up
- Remove mipi clk from the Amlogic axg clock controller
- New Rockchip rk3368 clock ids related to camera input
- Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk
reparenting
- A series from Liu Ying that adds some SCU clocks support for
i.MX8qxp DC0/MIPI-LVDS subsystems
- A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ,
and clkout1/2 support for i.MX8MM/MN
- Add I2c and Ethernet (RAVB) clocks on Renesas R-Car V3U
- Add timer (TMU) clocks on most Renesas R-Car Gen3 SoCs
- Add video-related (FCPVD/VSPD/VSPX), watchdog (RWDT), serial
(HSCIF), pincontrol/GPIO (PFC/GPIO), SPI (MSIOF), SDHI, and DMA
(SYS-DMAC) clocks on Renesas R-Car V3U
- Add support for the USB 2.0 clock selector on Renesas RZ/G2 SoCs
- Allwinner H616 SoC clk support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (171 commits)
clk: mstar: msc313-mpll: Fix format specifier
clk: mstar: Allow MStar clk drivers to be compile tested
clk: qoriq: use macros to generate pll_mask
clk: qcom: Add Global Clock controller (GCC) driver for SC7280
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: rpmh: Add support for RPMH clocks on SC7280
dt-bindings: clock: Add RPMHCC bindings for SC7280
clk: qcom: gcc-sm8350: add gdsc
dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
clk: qcom: gdsc: Implement NO_RET_PERIPH flag
clk: mstar: MStar/SigmaStar MPLL driver
...
Add support for the global clock controller found on SC7280
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1612981579-17391-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In the previous commit ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong
parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops) were
generalized in order to be able to reuse the same ops for more than just
one clock for one SoC: follow the change here in the MSM8996 MMCC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-7-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The function clk_gfx3d_determine_rate is selecting different PLLs
to manage the GFX3D clock source in a special way: this one needs
to be ping-pong'ed on different PLLs to ensure stability during
frequency switching (set a PLL rate, let it stabilize, switch the
RCG to the new PLL) and fast frequency transitions.
This technique is currently being used in the MSM8996 SoC and the
function was assuming that the parents were always at a specific
index in the parents list, which is TRUE, if we use this only on
the MSM8996 MMCC.
Unfortunately, MSM8996 is not the only SoC that needs to ping-pong
the graphics RCG, so choices are:
1. Make new special ops just to hardcode *again* other indexes,
creating code duplication for (imo) no reason; or
2. Generalize this function, so that it becomes usable for a range
of SoCs with slightly different ping-pong configuration.
In this commit, the second road was taken: define a new "special"
struct clk_rcg2_gfx3d, containing the ordered list of parents to
ping-pong the graphics clock on, and the "regular" rcg2 clock
structure in order to generalize the clk_gfx3d_determine_rate
function and make it working for other SoCs.
As for the function itself it is left with the assumption that we
need to ping-pong over three parents. The reasons for this are:
1. The initial model was MSM8996, which has 3 parents for the
graphics clock pingpong;
2. The other example that was taken into consideration is the
SDM630/636/660 SoC gpu clock controller, which is ping-ponging
over two dynamic clocked and one fixed clock PLL.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-6-angelogioacchino.delregno@somainline.org
[sboyd@kernel.org: Grow some local variables, drop do_div() usage in
favor of plain division, we're not dealing with a u64 here]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add a driver for the multimedia clock controller found on SDM660
based devices. This should allow most multimedia device drivers
to probe and control their clocks.
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[angelogioacchino.delregno@somainline.org: Cleaned up SDM630 clock fixups]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-4-angelogioacchino.delregno@somainline.org
[sboyd@kernel.org: Silence NULL pointer sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dmitry Baryshkov